CN106484064B - Power supply control circuit of singlechip system - Google Patents
Power supply control circuit of singlechip system Download PDFInfo
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- CN106484064B CN106484064B CN201611032080.4A CN201611032080A CN106484064B CN 106484064 B CN106484064 B CN 106484064B CN 201611032080 A CN201611032080 A CN 201611032080A CN 106484064 B CN106484064 B CN 106484064B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a power supply control circuit of a singlechip system, which comprises a power supply input end, a power supply output end, a reset chip, a key, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube, wherein the source electrode of the fourth MOS tube is connected with the power supply input end, and the drain electrode of the fourth MOS tube is connected with the power supply output end; the drain electrode of the second MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode is grounded by pressing a key, and the detection end of the reset chip is connected in parallel, and the grid electrode is connected with the power input end through a second resistor; the drain electrode of the fifth MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, and the grid electrode is connected with the power supply output end through a fourth resistor; the source electrode of the third MOS tube is grounded, and the grid electrode of the third MOS tube is connected with the grid electrode of the second MOS tube; the grid electrode of the fourth MOS tube is connected with the power input end through the third resistor. The power supply control circuit has the advantages of simple structure, smaller volume and lower cost.
Description
[ technical field ]
The present invention relates to power control circuits, and more particularly, to a power control circuit for a single chip system.
[ background Art ]
At present, singlechip systems are widely used, and a considerable part of application scenes need control circuits to predict and control power-off time so as to store data, remind users and other necessary operations.
The power control circuit of the SCM system is generally controlled by a mechanical control or an application specific integrated circuit. The mechanical control directly controls the on-off of the power supply through a mechanical switch (such as a ship-shaped switch), and the special integrated circuit controls the on-off of the power supply through a power management chip or a special controller chip. The mechanical control function is single, can only be used for controlling a power supply, and cannot be reused by a later-stage circuit; the control circuit of the special integrated circuit is complex; the cost is high; system interface resources such as I2C, SPI are required to be occupied.
The volume-sensitive single-chip microcomputer system cannot be provided with a plurality of key switches to realize the functions of power control, user key pressing, manual reset and the like, and the cost-sensitive single-chip microcomputer system cannot bear the high cost of a special power management integrated circuit.
[ summary of the invention ]
The invention aims to solve the technical problem of providing a power supply control circuit of a singlechip system, which has the advantages of simple structure, small volume and low cost.
In order to solve the technical problems, the invention adopts the technical scheme that the power supply control circuit of the singlechip system comprises a power supply input end, a power supply output end, a reset chip, a key, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube, wherein the second MOS tube, the third MOS tube and the fifth MOS tube are NMOS tubes, and the fourth MOS tube is a PMOS tube; the source electrode of the fourth MOS tube is connected with the power input end, and the drain electrode of the fourth MOS tube is connected with the power output end; the drain electrode of the second MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode is grounded by pressing a key, and the detection end of the reset chip is connected in parallel, and the grid electrode is connected with the power input end through a second resistor; the drain electrode of the fifth MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, and the grid electrode is connected with the power supply output end through a fourth resistor; the source electrode of the third MOS tube is grounded, and the grid electrode of the third MOS tube is connected with the grid electrode of the second MOS tube; the grid electrode of the fourth MOS tube is connected with the power input end through the third resistor.
The power supply control circuit comprises a first MOS tube and a key state detection end, wherein the first MOS tube is an NMOS tube; the drain electrode of the first MOS tube is connected with the key state detection end, the source electrode is grounded, and the grid electrode is connected with the source electrode of the second MOS tube.
The power supply control circuit comprises a second capacitor and a first resistor, wherein the second capacitor is connected with the key in parallel, and the first resistor is connected between the source electrode of the second MOS tube and the power supply input end.
The power supply control circuit comprises a power-off control end, wherein the power-off control end is connected with the grid electrode of the fifth MOS tube.
The power supply control circuit comprises a diode, wherein the anode of the diode is connected with the grid electrode of the fourth MOS tube, and the cathode of the diode is connected with the drain electrode of the second MOS tube.
In the power supply control circuit, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube are connected with the output end of the reset chip; in the power-on state, when the key is pressed for a long time to set time, the output end of the reset chip outputs a low level, the second MOS tube and the third MOS tube are turned off, and then the fourth MOS tube and the fifth MOS tube are turned off.
The power supply control circuit has the advantages of simple structure, smaller volume and lower cost.
[ description of the drawings ]
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a schematic block diagram of a power control circuit of a single chip microcomputer system according to an embodiment of the present invention.
Port description of the circuit of FIG. 1:
vsource: power supply input
Vload: power supply output
up_detect: the latter circuit detects the state of the system key SW1 through uP_detection, when uP_detection is detected to be at a low level, the key is in a release state, otherwise, the key is in a pressing state;
uP_control: the latter circuit controls the state of the latter power supply Vload through uP_control, pulls down uP_control to power off the latter power supply Vload, and pulls uP to keep the latter power supply Vload powered on.
Detailed description of the preferred embodiments
The power Control circuit of the singlechip system according to the embodiment of the invention is shown in fig. 1, and comprises a power input end Vsource, a power output end Vload, a power-off Control end up_control, a system key SW1 state detection end up_detect, a reset chip U1, a system key SW1, a diode D1, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4 and a MOS transistor Q5, wherein the MOS transistor Q1, the MOS transistor Q2, the MOS transistor Q3 and the MOS transistor Q5 are NMOS transistors, and the MOS transistor Q4 is a PMOS transistor. The system key SW1 is a tact switch, and the reset chip U1 is a chip STM6519.
The source electrode of the MOS transistor Q4 is connected with the power input end Vsource, and the drain electrode is connected with the power output end Vload.
The drain electrode of the MOS tube Q2 is connected with the grid electrode of the MOS tube Q4 through a diode D1, the anode electrode of the diode D1 is connected with the grid electrode of the MOS tube Q4, and the cathode electrode is connected with the drain electrode of the MOS tube Q2.
The source electrode of the MOS tube Q2 is grounded through a system key SW1, and is connected with the detection end nSR of the reset chip U1 in parallel, and the grid electrode is connected with the power input end Vsource through a resistor R2.
The drain electrode of the MOS tube Q5 is connected with the grid electrode of the MOS tube Q4, the source electrode is connected with the drain electrode of the MOS tube Q3, and the grid electrode is connected with the power supply output end Vload through the resistor R4.
The source electrode of the MOS tube Q3 is grounded, and the grid electrode of the MOS tube Q2 is connected with the grid electrode. The grid electrode of the MOS tube Q4 is connected with the power input end Vsource through a resistor R3.
The grid electrode of the MOS tube Q2 and the grid electrode of the MOS tube Q3 are connected with the output end nRST of the reset chip U1.
The capacitor C2 is connected in parallel with the system key SW1, and the resistor R1 is connected between the source of the MOS transistor Q2 and the power input end Vsource.
The drain electrode of the MOS tube Q1 is connected with the state detection end uP_Detector of the system key SW1, the source electrode is grounded, and the grid electrode is connected with the source electrode of the MOS tube Q2.
The power-off Control end uP_control is connected with the grid electrode of the MOS transistor Q5.
The working process of the power supply control circuit of the singlechip system in the embodiment of the invention is as follows:
and (3) current-up process: in the power-off state, the user presses the system key SW1 to trigger the power-on process. The action process is as follows: under the power-off state, the MOS tube Q2, the MOS tube Q4 and the MOS tube Q5 are in the off state, the MOS tube Q1 and the MOS tube Q3 are in the on state, the system key SW1 is pressed down, and the source electrode of the MOS tube Q2 is pulled down to the ground, so that the MOS tube Q2 is conducted. The grid electrode of the MOS tube Q4 is turned into a low level, and the MOS tube Q4 is conducted to enable the post-stage power supply Vload to be electrified. After the power-on of the post-stage power supply Vload, the level of the grid electrode of the MOS tube Q5 is raised, so that the MOS tube Q5 is conducted. MOS transistor Q5 turns on pull-down MOS transistor Q4 gate to ground, keeping MOS transistor Q4 in the on state. At this time, no matter what state the system key SW1 is, the state of the MOS transistor Q4 is not changed, i.e. the post-stage power Vload is always in the power-on state. The whole process is extremely short (nanosecond level), the response speed is extremely high, and the functions of powering on and maintaining in a short time in a power-off state are realized.
User key flow: in the power-on state, the user presses the system key SW1 to trigger the user key flow, and the action process is as follows: in the power-on state, the MOS tube Q1, the MOS tube Q3, the MOS tube Q4 and the MOS tube Q5 are in a conducting state, the MOS tube Q2 is in a cut-off state, a system key SW1 is pressed, the grid electrode of the MOS tube Q1 and the source electrode of the MOS tube Q2 are pulled down to the ground, the MOS tube Q1 is cut off, the MOS tube Q2 is conducted, and then the MOS tube Q4 is conducted, and the MOS tube Q4 is in a conducting state, so that the process cannot influence the state of a rear-stage power supply Vload, but the cut-off of the MOS tube Q1 disconnects uP_detect from the ground until the key is released, the rear-stage circuit can Detect the key state by detecting the level state of uP_detect, and the system key SW1 is used as a user key in the power-on state;
normal power-off flow: in the power-on state, the level of uP_control is pulled down by a system post-stage circuit, and a normal power-off flow is triggered. The action process is as follows: in the power-on state, the MOS tube Q1, the MOS tube Q3, the MOS tube Q4 and the MOS tube Q5 are in a conducting state, the MOS tube Q2 is in a cut-off state, the system key SW1 is in a release state, the level of uP_control is pulled down by a later-stage circuit, the MOS tube Q5 is cut off, the grid level of the MOS tube Q4 is pulled uP, the MOS tube Q4 is cut off, the later-stage power supply Vload is immediately powered off, and the function of controlling the power-off of the later-stage circuit is realized;
forced power-off flow: in the power-on state, the system key SW1 is continuously pressed for a specific duration (the shortest duration is determined by the model of the chip U1), and the forced power-off process is triggered. The action process is as follows: in the power-on state, the MOS tube Q1, the MOS tube Q3, the MOS tube Q4 and the MOS tube Q5 are in a conducting state, the MOS tube Q2 is in a cut-off state, the system key SW1 is continuously pressed down, the MOS tube Q2 is conducted, the detection end nSR of the STM6519 is continuously pulled down, when the length reaches a set value, the STM6519 output end nRST outputs a low level, the grid electrodes of the MOS tube Q2 and the MOS tube Q3 are simultaneously pulled down, the MOS tube Q2 and the MOS tube Q3 are cut off, the MOS tube Q4 and the MOS tube Q5 are further cut off, the post-stage power supply Vload is cut off, and the power-on state long-time forced power-off function is realized;
key debounce flow: because the system key SW1 is directly grounded, the short-time abnormal release after the key is pressed is regarded as key shake, and the key shake removing process is triggered, and the action process is as follows: when the system key SW1 is in a pressed state, if abnormal release is carried out, C2 charges through R1, the grid voltage of the MOS tube Q1 gradually rises, and if abnormal release is eliminated before reaching the on threshold voltage, the grid of the MOS tube Q1 is immediately pulled down, the MOS tube Q1 always keeps in a cut-off state in the process, the abnormal release of the key can not be detected by a later-stage circuit, and the function of key debouncing is realized.
According to the embodiment of the invention, the touch switch is used as a system key, the low-on-resistance P-channel MOSFET is used as a power supply control switch, the ST company reset chip STM6519 is used for detecting the long-time press of the key, and the control logic circuit is formed by a plurality of N-channel MOSFETs and resistors in a specific connection mode, so that the functions of short-time press power-up in the power-off state, long-time press power-off in the power-on state, user key in the power-on state, power-off control of a later-stage circuit and the like are realized. And a capacitor is connected in parallel with the key position to realize the key debouncing function. When the detection terminal nSR (pin 3) of STM6519 detects a continuous low level signal of a specific duration (the shortest duration is determined by the STM6519 sub-model), the output terminal nRST (pin 1) is immediately pulled down to ground and continues until the low level of the detection terminal nSR is withdrawn, by which feature the STM6519 can be used to detect a key long press and turn off the system power when the long time reaches the set value.
The embodiment of the invention can realize power-on, user key-press and forced power-off of the power supply by using the tact switch, the reset chip and the simple peripheral circuit, the subsequent singlechip system can detect the key-press state, and autonomously determine the power supply to keep or power-off according to the running state, thereby having low cost, small volume and complete functions.
Claims (4)
1. The power supply control circuit of the singlechip system comprises a power supply input end and a power supply output end, and is characterized by comprising a reset chip, a key state detection end, a power-off control end, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube, wherein the first MOS tube, the second MOS tube, the third MOS tube and the fifth MOS tube are NMOS tubes, and the fourth MOS tube is a PMOS tube; the source electrode of the fourth MOS tube is connected with the power input end, and the drain electrode of the fourth MOS tube is connected with the power output end; the drain electrode of the second MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode is grounded by pressing a key, and the detection end of the reset chip is connected in parallel, and the grid electrode is connected with the power input end through a second resistor; the drain electrode of the fifth MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, and the grid electrode is connected with the power supply output end through a fourth resistor; the power-off control end is connected with the grid electrode of the fifth MOS tube; the source electrode of the third MOS tube is grounded, and the grid electrode of the third MOS tube is connected with the grid electrode of the second MOS tube; the grid electrode of the fourth MOS tube is connected with the power input end through a third resistor; the drain electrode of the first MOS tube is connected with the key state detection end, the source electrode is grounded, and the grid electrode is connected with the source electrode of the second MOS tube.
2. The power control circuit of claim 1, comprising a second capacitor and a first resistor, the second capacitor being in parallel with the key, the first resistor being connected between the source of the second MOS transistor and the power input.
3. The power control circuit of claim 1, comprising a diode having an anode coupled to the gate of the fourth MOS transistor and a cathode coupled to the drain of the second MOS transistor.
4. The power control circuit of claim 1, wherein the gate of the second MOS transistor and the gate of the third MOS transistor are connected to the output end of the reset chip, and the output end of the reset chip outputs a low level when the key is pressed for a long time in the power-on state, the second MOS transistor and the third MOS transistor are turned off, and the fourth MOS transistor and the fifth MOS transistor are turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611032080.4A CN106484064B (en) | 2016-11-22 | 2016-11-22 | Power supply control circuit of singlechip system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611032080.4A CN106484064B (en) | 2016-11-22 | 2016-11-22 | Power supply control circuit of singlechip system |
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| Publication Number | Publication Date |
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| CN106484064A CN106484064A (en) | 2017-03-08 |
| CN106484064B true CN106484064B (en) | 2023-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611032080.4A Active CN106484064B (en) | 2016-11-22 | 2016-11-22 | Power supply control circuit of singlechip system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109831195B (en) * | 2019-01-29 | 2023-12-12 | 维沃移动通信有限公司 | Key control circuit and mobile terminal |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104914966A (en) * | 2015-06-09 | 2015-09-16 | 四川汇源光通信有限公司 | Single-chip microcomputer self-outage restarting circuit |
| CN105720960A (en) * | 2016-03-11 | 2016-06-29 | 武汉中旗生物医疗电子有限公司 | On-off circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI464717B (en) * | 2012-09-03 | 2014-12-11 | Hon Hai Prec Ind Co Ltd | Time control circuit and electronic device using the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104914966A (en) * | 2015-06-09 | 2015-09-16 | 四川汇源光通信有限公司 | Single-chip microcomputer self-outage restarting circuit |
| CN105720960A (en) * | 2016-03-11 | 2016-06-29 | 武汉中旗生物医疗电子有限公司 | On-off circuit |
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| CN106484064A (en) | 2017-03-08 |
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