CN210157162U - Key combined circuit for realizing hardware reset - Google Patents
Key combined circuit for realizing hardware reset Download PDFInfo
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- CN210157162U CN210157162U CN201921298086.5U CN201921298086U CN210157162U CN 210157162 U CN210157162 U CN 210157162U CN 201921298086 U CN201921298086 U CN 201921298086U CN 210157162 U CN210157162 U CN 210157162U
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Abstract
The utility model discloses a realize button combination circuit that hardware resets, including switching signal control circuit and reset circuit, switching signal control circuit includes first resistance, and second resistance and key switch K2 are connected to first resistance, and key switch K1, key switch K2 and third resistance are connected respectively to the second resistance, and key switch K1 and third resistance are connected and ground connection; the reset circuit comprises a fourth resistor, the fourth resistor is connected with a node VA, the base of the triode Q1 is connected with the fourth resistor, the emitting electrode of the triode Q1 is grounded, the collecting electrode of the triode Q1 is connected with the grid electrodes of the seventh resistor, the capacitor C1 and the MOS tube through the sixth resistor respectively, the source electrode of the MOS tube is connected with the power input end, and the drain electrode of the MOS tube is connected with the power output end. The common key circuit is combined, the switching control of a system main power supply is realized by utilizing the switching characteristics of a triode and an MOS (metal oxide semiconductor) tube, and the hardware forced power-off reset function of an electronic product is realized.
Description
Technical Field
The utility model relates to the field of electronic technology, specific saying so, a realize button combination circuit that hardware resets.
Background
Mobile electronic products such as mobile phones, tablet computers, notebook computers, learning machines and handheld instruments are more and more, and the unified characteristics are as follows: batteries with different capacities are built in, a plurality of control keys are arranged, most products only have a soft-off function (a main chip MCU receives a power-off instruction, responds the power-off instruction and executes system standby), and a hardware disconnecting device of a main power supply is not provided. When the system crashes, the system cannot respond to external operation input, cannot be restarted after forced outage of the system, can only wait for the electric quantity of a battery to be exhausted, or is disconnected for forced outage, and is very inconvenient.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a realize button combination circuit that hardware resets for when the system appears the problem of halting among the solution prior art, will not respond outside operation input, can't let the system force the outage restart, can only wait for battery power to exhaust, perhaps tear open and force the outage, very inconvenient problem.
The utility model discloses carry out the integrated design with 2 keying circuits, realize the different function of controlling respectively when pressing separately, can export low-voltage signal when pressing 2 buttons simultaneously, and then control MOS pipe or power management chip disconnection system power supply, loosen the power recovery behind the button to realize that system hardware resets, specifically as follows:
a key combination circuit for realizing hardware reset comprises a switch signal control circuit and a reset circuit, wherein the switch signal control circuit comprises a first resistor, the first end of the first resistor is connected with an upper pull voltage V, the second end of the first resistor is respectively connected with the first end of a second resistor and the first end of a key switch K2, the second end of the second resistor is respectively connected with the first end of a key switch K1, the second end of the key switch K2 and the first end of a third resistor, and the second end of the key switch K1 is connected with the second end of the third resistor and grounded;
the reset circuit comprises a fourth resistor, the first end of the fourth resistor is connected with a node between the first resistor and the key switch K2, the second end of the fourth resistor is respectively connected with the first end of the fifth resistor and the base of the triode Q1, the second end of the fifth resistor is grounded, the emitter of the triode Q1 is grounded, the collector of the triode Q1 is respectively connected with the first end of the seventh resistor through the sixth resistor, the first end of the capacitor C1 and the grid electrode of the MOS transistor, the source electrode of the MOS transistor is connected with the second end of the capacitor C1, the second end of the seventh resistor is connected with the power input end, and the drain electrode of the MOS transistor is connected with the power output end.
The power input end and the power output end are controlled through an MOS (metal oxide semiconductor) tube, the connection and disconnection of the MOS tube are controlled through an MOS tube grid signal, if the MOS tube grid signal is low voltage, the MOS tube is connected, and the system supplies power; if the grid signal of the MOS tube is high voltage, the MOS tube is cut off, and the system is powered off. And the grid signal of the MOS tube is controlled by an NPN type triode.
The power supply control signal is connected with the base level of an NPN triode Q1, when the base of the triode Q1 is low voltage, the triode Q1 is cut off, the grid signal of the MOS transistor is high voltage, and the system is powered off; when the base of the triode Q1 is at high voltage, the collector and emitter of the triode are connected, the gate signal of the MOS tube is at low voltage, and the system supplies power.
The power supply control signal is generated by the switch signal control circuit, and the key modes of the key switch K1 and the key switch K2 are as follows:
(1) key switch K1 and key switch K2 are both off:
the power supply control signal input into the fourth resistor is obtained by dividing the voltage of the first resistor, the second resistor and the third resistor;
(2) key switch K1 is closed:
the power supply control signal input into the fourth resistor is obtained by dividing voltage by the first resistor and the second resistor;
(3) key switch K2 is closed:
the power supply control signal input into the fourth resistor is obtained by dividing voltage by the first resistor and the third resistor;
by reasonably configuring the values of the first resistor, the second resistor and the third resistor, power supply control signals in 3 states can be obtained, and the power supply control signals need to satisfy the condition that the voltage between the base electrode and the emitting electrode of the triode Q1 is higher than the breakover voltage of the triode Q1.
(4) Key switch K1 and key switch K2 are both closed:
the power supply control signal input into the fourth resistor is 0, the triode Q1 works in a cut-off state, the grid signal of the MOS tube is high voltage, and the system is powered off. And simultaneously, when the key is released or only one key is released, the triode Q1 is restored to be conducted, so that the conduction of the MOS tube is controlled, the system power is restored, and the hardware forced reset process is completed.
Compared with the prior art, the utility model, following advantage and beneficial effect have:
(1) the utility model discloses a carry out the integrated design to ordinary key circuit, utilize the on-off characteristic of triode, MOS pipe to realize the on-off control to the system main power, disconnect the system power when 2 buttons are pressed simultaneously, loosen the back and resume the power supply. The circuit does not influence the normal functions of the keys, simultaneously realizes the function of forced power-off reset of hardware of electronic products with batteries, can be restarted easily when the system is halted, and does not need to wait for the exhaustion of the batteries or the disassembly and maintenance.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples, but the present invention is not limited thereto.
Example 1:
with reference to fig. 1, a key combination circuit for implementing hardware reset includes a switch signal control circuit and a reset circuit, where the switch signal control circuit includes a resistor R11, a first end of the resistor R11 is connected to a pull-up voltage V, a second end of the resistor R11 is respectively connected to a first end of the resistor R22 and a first end of the key switch K2, a second end of the resistor R22 is respectively connected to a first end of the key switch K1, a second end of the key switch K2 and a first end of the resistor R33, and a second end of the key switch K1 is connected to a second end of the resistor R33 and grounded;
the reset circuit comprises a resistor R2, the first end of a resistor R2 is connected with a node VA between a resistor R11 and a key switch K2, the second end of the resistor R2 is respectively connected with the first end of a resistor R3 and the base of a triode Q1, the second end of the resistor R3 is grounded, the emitter of the triode Q1 is grounded, the collector of the triode Q1 is respectively connected with the first end of the resistor R1 through the resistor RV30, the first end of a capacitor C1 and the grid of a MOS (metal oxide semiconductor) transistor, the source of the MOS transistor is connected with the second end of a capacitor C1, the second end of the resistor R1 is connected with a power supply input end, and the drain of the MOS transistor is.
The power input end Vin and the power output end Vout are controlled by an MOS (metal oxide semiconductor) tube, the connection and disconnection of the MOS tube are controlled by a grid signal of the MOS tube, and if the grid signal of the MOS tube is low voltage, the MOS tube is connected and the system supplies power; if the grid signal of the MOS tube is high voltage, the MOS tube is cut off, and the system is powered off. And the grid signal of the MOS tube is controlled by an NPN type triode.
The power supply control signal is connected with the base level of an NPN triode Q1, when the base of the triode Q1 is low voltage, the triode Q1 is cut off, the grid signal of the MOS transistor is high voltage, and the system is powered off; when the base of the triode Q1 is at high voltage, the collector and emitter of the triode are connected, the gate signal of the MOS tube is at low voltage, and the system supplies power.
The power supply control signal is generated by the switch signal control circuit, and the key modes of the key switch K1 and the key switch K2 are as follows:
(1) key switch K1 and key switch K2 are both off:
the power supply control signal input into the power supply R2 is obtained by dividing voltage by a resistor R11, a resistor R22 and a resistor R33;
(2) key switch K1 is closed:
the power supply control signal input into the resistor R2 is obtained by dividing voltage by a resistor R11 and a resistor R22;
(3) key switch K2 is closed:
the power supply control signal input into the resistor R2 is obtained by dividing voltage by a resistor R11 and a resistor R33;
by reasonably configuring the values of the resistor R11, the resistor R22 and the resistor R33, power supply control signals under 3 states can be obtained, and the power supply control signals need to satisfy the condition that the voltage between the base electrode and the emitter electrode of the triode Q1 is higher than the conduction voltage of the triode Q1.
(4) Key switch K1 and key switch K2 are both closed:
the power supply control signal of the input resistor R2 is 0, the triode Q1 works in a cut-off state, the grid signal of the MOS tube is high voltage, and the system is powered off. And simultaneously, when the key is released or only one key is released, the triode Q1 is restored to be conducted, so that the conduction of the MOS tube is controlled, the system power is restored, and the hardware forced reset process is completed.
Although the present invention has been described herein with reference to the illustrated embodiments thereof, which are merely preferred embodiments of the present invention, it is to be understood that the present invention is not limited thereto, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.
Claims (1)
1. A key combination circuit for realizing hardware reset is characterized by comprising a switch signal control circuit and a reset circuit, wherein the switch signal control circuit comprises a first resistor, the first end of the first resistor is connected with a pull-up voltage V, the second end of the first resistor is respectively connected with the first end of a second resistor and the first end of a key switch K2, the second end of the second resistor is respectively connected with the first end of a key switch K1, the second end of the key switch K2 and the first end of a third resistor, and the second end of the key switch K1 is connected with the second end of the third resistor and grounded;
the reset circuit comprises a fourth resistor, the first end of the fourth resistor is connected with a node between the first resistor and the key switch K2, the second end of the fourth resistor is respectively connected with the first end of the fifth resistor and the base of the triode Q1, the second end of the fifth resistor is grounded, the emitter of the triode Q1 is grounded, the collector of the triode Q1 is respectively connected with the first end of the seventh resistor through the sixth resistor, the first end of the capacitor C1 and the grid electrode of the MOS transistor, the source electrode of the MOS transistor is connected with the second end of the capacitor C1, the second end of the seventh resistor is connected with the power input end, and the drain electrode of the MOS transistor is connected with the power output end.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921298086.5U CN210157162U (en) | 2019-08-12 | 2019-08-12 | Key combined circuit for realizing hardware reset |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921298086.5U CN210157162U (en) | 2019-08-12 | 2019-08-12 | Key combined circuit for realizing hardware reset |
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| CN210157162U true CN210157162U (en) | 2020-03-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111583434A (en) * | 2020-04-27 | 2020-08-25 | 深圳市阿尔艾富信息技术股份有限公司 | Internet of things information processing terminal and system |
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- 2019-08-12 CN CN201921298086.5U patent/CN210157162U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111583434A (en) * | 2020-04-27 | 2020-08-25 | 深圳市阿尔艾富信息技术股份有限公司 | Internet of things information processing terminal and system |
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