CN106445869B - A kind of high-speed data exchange method based on FPGA and PCIe - Google Patents
A kind of high-speed data exchange method based on FPGA and PCIe Download PDFInfo
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- CN106445869B CN106445869B CN201610833434.9A CN201610833434A CN106445869B CN 106445869 B CN106445869 B CN 106445869B CN 201610833434 A CN201610833434 A CN 201610833434A CN 106445869 B CN106445869 B CN 106445869B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The present invention provides a kind of high-speed data exchange methods based on FPGA and PCIe, and general or special purpose computer platform and the data exchange module based on fpga chip is arranged；The binary channels DMA cores that the data exchange module is provided with the PCIe stones that PCIe buses are connected with computer platform and is connected with PCIe stones are provided with DMA channel one and DMA channel two in the binary channels DMA cores；The DMA channel one is connected with input processing module, and the DMA channel two is connected with output processing module.The present invention has the advantages that speed is fast, flexibility is strong, vdiverse in function, at low cost and reliability is high.
Description
Technical field
The present invention relates to a kind of high-speed data exchange methods based on FPGA and PCIe, belong to field of communication technology, also fall within
In field of computer technology and Radar Technology field.
Background technology
With being constantly progressive for science and technology, radar system, communication system, remote sensing system, image capturing system and high speed
Data collecting system etc. increasingly improves data transmission rates demands, needs to hand over using the transfer bus of high speed and efficient data
Framework is changed to carry out data transmission.
PCI-Express (PCIe) is a kind of widely applied very fast high-bandwidth transfer bus, is particularly suitable for high speed number
According to transmission and exchange.For single system and slow data transmission, mostly used using the technical solution that PCIe carries out data transmission
Special integrated chip（ASSP）Or the FPGA of simple framework is realized.But existing solution cannot be satisfied complex data
The demand of exchange system, and have the shortcomings that speed is slow and flexibility is poor.
Invention content
To overcome available data switching solution speed slow and the disadvantage of flexibility difference, for complex data exchange system
High speed data transfer, the present invention proposes a kind of high-speed data exchange method based on FPGA and PCIe.
Technical solution of the present invention is as follows：
Computer platform and the number based on fpga chip is arranged in a kind of high-speed data exchange method based on FPGA and PCIe
According to Switching Module；
The data exchange module be provided with the PCIe stones that PCIe buses are connected with computer platform and with
The binary channels DMA cores that PCIe stones are connected are provided with DMA channel one and DMA channel two in the binary channels DMA cores；
The DMA channel one is connected with input processing module, and the DMA channel two is connected with output processing module.
As a further improvement on the present invention：The input processing module includes the input being connected with DMA channel one
AXI4 buses further include several optical receiver modules；It is defeated that each optical receiver module is connected with one by the high-speed serial I/O of FPGA respectively
Enter fifo buffer, each input fifo buffer turns AXI4 interface modules by a FIFO respectively and is connected with input AXI4 buses
It connects.
As a further improvement on the present invention：The input bit wide of the input fifo buffer is 16bit, and output bit wide is
128bit。
As a further improvement on the present invention：The output processing module be provided be connected with DMA channel two it is N number of defeated
Go out FIFO first-level buffers area, the data in the DMA channel two are divided into and N number of output FIFO level-ones according to DMA interface address
The corresponding roads N output data, the roads N output data are respectively delivered to corresponding output FIFO first-level buffers to buffering area one by one
Qu Zhong；
The output processing module is additionally provided with M output AXI4 level-one bus, and M is less than N, N number of output FIFO mono-
It is corresponding and connect with an output AXI4 level-one buses respectively that the output of grade buffering area is divided into M groups, each group；
Each output AXI4 level-one buses are connected separately with a virtual fifo module, and the virtual fifo module is connected with a use
In data cached DDR chips, an output AXI4 secondary bus, the output AXI4 is also respectively connected in each virtual fifo module
Secondary bus is connected with several output FIFO Secondary buffers, each output FIFO bis- that the output AXI4 secondary bus is connected
Each output FIFO first-level buffers area that grade buffering area is connect with branch where output AXI4 secondary bus corresponds, to
The roads the N output data that DMA channel two exports is respectively delivered to N number of output FIFO level 2 bufferings by M virtual fifo module
Qu Zhong；
Each output FIFO Secondary buffers are connected separately with a pre- place for completing packet header detection and rejecting redundant information
Manage module；
The output processing module is additionally provided with data simultaneous module, each preprocessing module with the data simultaneous module
It is connected, is exported respectively by the high-speed serial I/O of a FPGA and an optical transmission module by synchronous each road output data；Or
A high-speed serial I/O is passed sequentially through without synchronization, respectively for the output data of person, each preprocessing module and an optical transmission module is defeated
Go out.
As a further improvement on the present invention：The input bit wide of the output FIFO Secondary buffers is 64bit, carry-out bit
Width is 256bit.
Compared with the existing technology, the present invention has the following advantages：（1）This framework uses more AXI4 buses, multichannel data
The technological means such as parallel processing, big bit wide, multi-level buffer, multichannel virtual fifo and more DDR chips, ensure that the parallel of data
High-speed transfer；（2）The present invention is handled using computer system and external multipath high-speed input processing module and multipath high-speed output
Module realizes data exchange jointly, disclosure satisfy that the demand of complex data exchange system；（3）This framework is using binary channels DMA knots
Structure, can avoid the blocking effect of single DMA channel, and make to output and input independently of each other, be independent of each other；（4）Speedy carding process number
Can also be asynchronous output according to that can be synchronism output；（5）Data exchange module is based on fpga chip, strong with flexibility,
Advantage vdiverse in function.
Description of the drawings
Fig. 1 is the overall architecture schematic diagram of the present invention.
Fig. 2 is DMA channel one and the framework schematic diagram of input processing module part.
Fig. 3 is DMA channel two and the framework schematic diagram of output processing module part.
Specific implementation mode
The technical solution that the invention will now be described in detail with reference to the accompanying drawings：
Such as Fig. 1, computer platform is arranged in a kind of high-speed data exchange method based on FPGA and PCIe（Including general meter
Calculation machine and special purpose computer）With the data exchange module based on fpga chip；
The data exchange module is provided with the PCIe stones that PCIe buses are connected with computer platform（That is PCIe
X8 IP core）The binary channels DMA cores being connected with PCIe stones are provided with one He of DMA channel in the binary channels DMA cores
DMA channel two；PCIe buses are connected to PCIe stones by the high-speed serial I/O in FPGA；
The DMA channel one is connected with input processing module, and the DMA channel two is connected with output processing module.
Such as Fig. 2, a kind of input processing module of 4 tunnel input is provided in the present embodiment, the input processing module includes
The input AXI4 buses that are connected with DMA channel one further include 4 optical receiver modules；Each optical receiver module passes through FPGA respectively
High-speed serial I/O be connected with an input fifo buffer, each fifo buffer that inputs turns AXI4 interface moulds by a FIFO respectively
Block is connected with input AXI4 buses.
The input bit wide of the input fifo buffer is 16bit, and output bit wide is 128bit；
Input FIFO is sent into after the high speed serialization I O process that outer input data passes through optical fiber, optical receiver module and FPGA
Buffering area, computer platform read the number in input fifo buffer by PCIe buses, DMA channel one and input AXI4 buses
According to.
Such as Fig. 3, a kind of output processing module of 6 tunnel output, the output processing module setting are provided in the present embodiment
There are 6 output FIFO first-level buffers areas being connected with DMA channel two, the data in the DMA channel two are according to DMA interface
Location is divided into that corresponding 6 tunnel output data, 6 tunnel output datas are conveyed respectively one by one with 6 output FIFO first-level buffers areas
Into corresponding output FIFO first-level buffers area；
The output processing module is additionally provided with 2 output AXI4 level-one buses, 6 output FIFO first-level buffers area
3 at one group, each group it is corresponding and connect with an output AXI4 level-one buses respectively；
Each output AXI4 level-one buses are connected separately with a virtual fifo module VFIFO_X3, and the virtual fifo module connects
The DDR3 chips for caching mass data are connected to, it is total that an output AXI4 two levels are also respectively connected in each virtual fifo module
Line, each AXI4 secondary bus that exports are connected separately with 3 output FIFO Secondary buffers, and the output AXI4 secondary bus connects
Each output FIFO level-ones that each output FIFO Secondary buffers connect are connect with branch where output AXI4 secondary bus are slow
Area's one-to-one correspondence is rushed, to which the 6 tunnel output datas that DMA channel two exports are respectively delivered to 6 by 2 virtual fifo modules
It exports in FIFO Secondary buffers；The input bit wide of the output FIFO Secondary buffers is 64bit, and output bit wide is
256bit；
The output AXI4 level-ones bus and output AXI4 secondary bus all have AXI4-Stream functions；
Each output FIFO Secondary buffers are connected separately with a pre- place for completing packet header detection and rejecting redundant information
Manage module；
The output processing module is additionally provided with data simultaneous module, each preprocessing module with the data simultaneous module
It is connected, is exported respectively by the high-speed serial I/O of a FPGA and an optical transmission module by synchronous each road output data；Or
A high-speed serial I/O is passed sequentially through without synchronization, respectively for the output data of person, each preprocessing module and an optical transmission module is defeated
Go out.
This framework uses binary channels DMA structures, can avoid the blocking effect of single DMA channel, and make to output and input phase
It is mutually independent, it is independent of each other；It is empty that more AXI buses, multichannel data parallel transmission, big bit wide, multi-level buffer, multichannel are additionally used simultaneously
The quasi- technological means such as FIFO and more DDR chips ensure the parallel high-speed transmission of data.By experimental verification, this framework is used
Carry out data transmission, using PCIe2.0 buses, be configured to X8 forms（8 parallel data channels）When, input data exchange rate
Up to 2.5GBps, output data exchange rate is up to 2.3GBps.
Claims (4)
1. a kind of high-speed data exchange method based on FPGA and PCIe, it is characterised in that：Computer platform is set and is based on
The data exchange module of fpga chip；
The data exchange module is provided with PCIe stones that PCIe buses are connected with computer platform and hard with PCIe
The binary channels DMA cores of nuclear phase connection, are provided with DMA channel one and DMA channel two in the binary channels DMA cores；
The DMA channel one is connected with input processing module, and the DMA channel two is connected with output processing module；
The input processing module includes the input AXI4 buses being connected with DMA channel one, further includes several optical receiver modules；
Each optical receiver module is connected with an input fifo buffer by the high-speed serial I/O of FPGA respectively, each to input fifo buffer point
Do not turn AXI4 interface modules by a FIFO with input AXI4 buses to be connected.
2. the high-speed data exchange method based on FPGA and PCIe as described in claim 1, it is characterised in that：The input
The input bit wide of fifo buffer is 16bit, and output bit wide is 128bit.
3. the high-speed data exchange method based on FPGA and PCIe as claimed in claim 1 or 2, it is characterised in that：It is described defeated
Go out processing module and is provided with the N number of output FIFO first-level buffers area being connected with DMA channel two, the number in the DMA channel two
According to being divided into according to DMA interface address, the corresponding roads N output data, the roads N export one by one with N number of output FIFO first-level buffers area
Data are respectively delivered in corresponding output FIFO first-level buffers area；
The output processing module is additionally provided with M output AXI4 level-one bus, and M is less than N, and N number of output FIFO level-ones are slow
Rushing the output in area, to be divided into M groups, each group corresponding and connect with an output AXI4 level-one buses respectively；
Each output AXI4 level-one buses are connected separately with a virtual fifo module, and the virtual fifo module is connected with one for delaying
An output AXI4 secondary bus, the output AXI4 two levels is also respectively connected in the DDR chips of deposit data, each virtual fifo module
Bus is connected with several output FIFO Secondary buffers, and each output FIFO two levels that the output AXI4 secondary bus is connected are slow
It rushes each output FIFO first-level buffers area that area is connect with branch where output AXI4 secondary bus to correspond, thus will
The roads the N output data that DMA channel two exports is respectively delivered to N number of output FIFO Secondary buffers by M virtual fifo module
In；
Each output FIFO Secondary buffers are connected separately with a pretreatment mould for completing packet header detection and rejecting redundant information
Block；
The output processing module is additionally provided with data simultaneous module, and each preprocessing module is connected with the data simultaneous module
It connects, is exported respectively by the high-speed serial I/O of a FPGA and an optical transmission module by synchronous each road output data；Alternatively, each
The output data of preprocessing module passes sequentially through a high-speed serial I/O and optical transmission module output without synchronization, respectively.
4. the high-speed data exchange method based on FPGA and PCIe as claimed in claim 3, it is characterised in that：The output
The input bit wide of FIFO Secondary buffers is 64bit, and output bit wide is 256bit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610833434.9A CN106445869B (en) | 2016-09-20 | 2016-09-20 | A kind of high-speed data exchange method based on FPGA and PCIe |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108519857B (en) * | 2018-03-16 | 2020-02-11 | 中北大学 | Multi-source unformatted broadband data high-speed mass formatted storage and feature preservation method |
| CN109388590B (en) * | 2018-09-28 | 2021-02-26 | 中国电子科技集团公司第五十二研究所 | Dynamic cache block management method and device for improving multichannel DMA (direct memory access) access performance |
| CN109975764A (en) * | 2019-03-19 | 2019-07-05 | 安徽雷炎电子科技有限公司 | A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application |
| CN113655956B (en) * | 2021-07-26 | 2024-02-02 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
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| CN103559156A (en) * | 2013-11-11 | 2014-02-05 | 北京大学 | Communication system between FPGA (field programmable gate array) and computer |
| CN204256732U (en) * | 2014-11-13 | 2015-04-08 | 海德盟数控技术（深圳）有限公司 | The high-speed data transmission apparatus of Based PC I-Express interface |
| CN105550133A (en) * | 2015-12-08 | 2016-05-04 | 天津津航计算技术研究所 | AXIS-FIFO bridge circuit based on ZYNQ and data transmission method using same |
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- 2016-09-20 CN CN201610833434.9A patent/CN106445869B/en not_active Expired - Fee Related
Patent Citations (5)
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|---|---|---|---|---|
| CN201465562U (en) * | 2009-06-29 | 2010-05-12 | 北京理工大学 | Two-channel digital radiofrequency storage board |
| CN102185833A (en) * | 2011-03-30 | 2011-09-14 | 无锡众志和达存储技术有限公司 | Fiber channel (FC) input/output (I/O) parallel processing method based on field programmable gate array (FPGA) |
| CN103559156A (en) * | 2013-11-11 | 2014-02-05 | 北京大学 | Communication system between FPGA (field programmable gate array) and computer |
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