CN106341153A

CN106341153A - High-speed transceiver

Info

Publication number: CN106341153A
Application number: CN201510402603.9A
Authority: CN
Inventors: 褚秀清
Original assignee: Individual
Current assignee: Individual
Priority date: 2015-07-10
Filing date: 2015-07-10
Publication date: 2017-01-18

Abstract

The invention provides a high-speed transceiver which has the advantages of low power consumption, small size, easy configuration, high efficiency, greatly reduced communication cost and the like. The high-speed transceiver provided by the invention comprises FPGA, a transmitter channel and a receiver channel. The receiver channel is composed of a physical coding sublayer and a physical medium additional sublayer. The receiver channel is composed of a physical coding sublayer and a physical medium additional sublayer. The physical coding sublayer of the transmitter channel and the receiver channel is composed of phase compensation FIFO, a byte serializer, an 8B/10B encoder, a word aligner, rate matching FIFO, an 8B/10B decoder, a byte deserializer, a byte sequencer and phase compensation FIFO. The physical medium additional sublayer of the transmitter channel and the receiver channel is composed of an I/O buffer analog circuit, a CDR and a serializer/deserializer. The CDR comprises a phase lock controller, a phase difference device, a phase detector and a phase frequency divider. The signal output end of the phase lock controller is connected with the signal input end of the phase difference device. The transmitter channel and the receiver channel are connected with the FPGA.

Description

A kind of high-speed transceiver

Technical field

The invention belongs to digital display circuit technical field, more particularly to a kind of high-speed transceiver.

Background technology

With the continuous development of technology, high speed serialization i/o technology replaces Traditional parallel i/o technology and has become as current trend.Fastest 133 mb/s for ata7 of parallel bus interface, the transfer rate that issuing satal.0 specification in 2003 provides just has reached 150mb/s, sata3.0 theoretical velocity has even more reached the speed of 600 mb/s, when equipment is operated in high speed, parallel bus is subject to interference and crosstalk so that wiring is considerably complicated.And designing with energy simplified topology of serial transceiver, reduce adapter quantity.When having identical bus bandwidth, the power consumption of serial line interface is also little than parallel port.And equipment mode of operation is changed into serial transmission from parallel transmission, the speed of serial just can increase exponentially with the raising of frequency.

Embedded gb rate level and low power architecture advantage are had based on current fpga, it can make designer utilize the variation issue of the quick resolution protocol of efficient eda instrument and speed.With the extensive application of fpga, transceiver is incorporated in fpga, becomes an effective way solving device transmission speed issue.

Content of the invention

The present invention is aiming at the problems referred to above, provides a kind of high-speed transceiver；The present invention has the advantages that low-power consumption, small size, easily configuration, high efficiency, decreases required transmission channel and device pin number, thus substantially reducing communications cost.

For realizing the above-mentioned purpose of the present invention, the present invention adopts the following technical scheme that.

A kind of high-speed transceiver of the present invention, including fpga, transmitter channel and receiver channel；Described transmitter channel is made up of with physical medium additional sub-layer Physical Coding Sublayer, and described receiver channel is also made up of with physical medium additional sub-layer Physical Coding Sublayer；Its structural feature is: the Physical Coding Sublayer of described transmitter channel and receiver channel includes phase compensation fifo, byte serial device, 8b/10b encoder, word aligner, rate-matched fifo, 8b/10b decoder, byte deserializer, byte sorting unit, phase compensation fifo, and the physical medium additional sub-layer of described transmitter channel and receiver channel includes the analog circuit of i/o buffer, cdr, serializer/de-serializers；Described cdr includes PGC demodulation controller, phase difference value device, phase detectors, phase place frequency divider, and the signal output part of described PGC demodulation controller is connected with the signal input part of phase difference value device；Described transmitter channel is connected with fpga with receiver channel.

As a preferred embodiment of the present invention, described deserializer adopts the high speed recovered clock on cdr.

The invention has the beneficial effects as follows.

The present invention provides a kind of high-speed transceiver, high-speed transceiver makes that mass data is point-to-point to be transmitted being possibly realized, this serial communication technology makes full use of the channel capacity of transmission media, compared with conventional parallel data bus line, decrease required transmission channel and device pin number, thus substantially reducing communications cost.The transceiver of the present invention possesses the advantages of low-power consumption, small size, easy configuration, high efficiency, so that it is easily integrated in bus system.In high-speed serial data host-host protocol, the performance of transceiver plays conclusive effect to EBI transfer rate, also have impact on the performance of this kind of EBI system to a certain extent.The present invention has parsed realization on fpga platform for the high-speed transceiver module, also provides beneficial reference for the realization of various high speed serialization agreements.

Brief description

Fig. 1 is a kind of system assumption diagram of high-speed transceiver of the present invention.

Fig. 2 is a kind of cdr structure chart of high-speed transceiver of the present invention.

Specific embodiment

Referring to shown in Fig. 1 and Fig. 2, a kind of high-speed transceiver of the present invention, including fpga, transmitter channel and receiver channel；Described transmitter channel is made up of with physical medium additional sub-layer Physical Coding Sublayer, and described receiver channel is also made up of with physical medium additional sub-layer Physical Coding Sublayer；Its structural feature is: the Physical Coding Sublayer of described transmitter channel and receiver channel includes phase compensation fifo, byte serial device, 8b/10b encoder, word aligner, rate-matched fifo, 8b/10b decoder, byte deserializer, byte sorting unit, phase compensation fifo, and the physical medium additional sub-layer of described transmitter channel and receiver channel includes the analog circuit of i/o buffer, cdr, serializer/de-serializers；Described cdr includes PGC demodulation controller, phase difference value device, phase detectors, phase place frequency divider, and the signal output part of described PGC demodulation controller is connected with the signal input part of phase difference value device；Described transmitter channel is connected with fpga with receiver channel.

As shown in Figure 2, the signal output part of described PGC demodulation controller is connected with the signal input part of phase difference value device, the outfan of described phase difference value device is divided into high speed clk and low speed clk, described low speed clk is exported by frequency divider, described phase interpolator output clock sampling signal passes to phase detectors, and the signal output part of described phase detectors is connected with phase interpolator again.

Described deserializer adopts the high speed recovered clock on cdr.

Described 8b/10b encoder receives 8 data and 1 control code, is translated into 10 code set.Encoder one side can make the 0 and 1 of data transfer equal number, most 5 full 0s or complete 1, there is provided DC balance well, and have good transition density, be conducive to improving the reliability of transmission, thus reducing intersymbol interference, so that receptor locking phase in the data flow receiving；On the other hand can provide, for data, the pattern that specifically can more preferably identify border, set up word boundary in a stream, receptor can divide byte using specific pattern.

Described byte serial device is divided equally to the parallel data bit wide carrying out APC automatic phase compensation fifo module.Forward effective low byte first, then forward effective high byte.Reduce system transfers clock rate while maintaining system transfers data rate, that is, while meeting maximum fpga framework frequency limitation, realize making sendaisle run under higher data rate.

Described phase compensation fifo compensates to the phase difference between low-speed parallel clock and fpga framework high-speed interface clock, is a kind of shallow fifo, compensates the phase contrast of clock between fifo kernel and transceiver pcs.

Described deserializer is corresponding with transmitter byte serial device, and the serial data receiving is converted to 8 or 10 bit parallel data by it.Deserializer adopts the high speed recovered clock on cdr, operates in the frequency of serial data rate half.

Described 8b/10b decoder receives 10 data, and is decoded into 8 data and 1 control identifier.Using two 8b/10b decoders, detect incorrect coding code character, detect parity error, can be bypassed.

It is understandable that, above with respect to the specific descriptions of the present invention, it is merely to illustrate the present invention and is not limited to the technical scheme described by the embodiment of the present invention, it will be understood by those within the art that, still the present invention can be modified or equivalent, to reach identical technique effect；As long as meeting and using needs, all within protection scope of the present invention.

Claims

1. a kind of high-speed transceiver, including fpga, transmitter channel and receiver channel；Described transmitter channel is made up of with physical medium additional sub-layer Physical Coding Sublayer, and described receiver channel is also made up of with physical medium additional sub-layer Physical Coding Sublayer；It is characterized in that: the Physical Coding Sublayer of described transmitter channel and receiver channel includes phase compensation fifo, byte serial device, 8b/10b encoder, word aligner, rate-matched fifo, 8b/10b decoder, byte deserializer, byte sorting unit, phase compensation fifo, and the physical medium additional sub-layer of described transmitter channel and receiver channel includes the analog circuit of i/o buffer, cdr, serializer/de-serializers；Described cdr includes PGC demodulation controller, phase difference value device, phase detectors, phase place frequency divider, and the signal output part of described PGC demodulation controller is connected with the signal input part of phase difference value device；Described transmitter channel is connected with fpga with receiver channel.

2. a kind of high-speed transceiver according to claim 1 it is characterised in that: described deserializer adopt cdr on high speed recovered clock.