CN106325764B

CN106325764B - Memory management method, memory control circuit unit and memory storage device

Info

Publication number: CN106325764B
Application number: CN201510396806.1A
Authority: CN
Inventors: 颜鸿圣; 陈国荣
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2015-07-08
Filing date: 2015-07-08
Publication date: 2021-02-26
Anticipated expiration: 2035-07-08
Also published as: CN106325764A

Abstract

The invention provides a memory management method, a memory control circuit unit and a memory storage device. The method comprises the following steps: receiving a first write-in command and writing data corresponding to the first write-in command into a first idle physical erasing unit in the physical erasing units; detecting a number of second idle physical erase units that do not include the first idle physical erase unit; judging whether the number of the second idle physical erasing units is less than a threshold value; if the number of the second idle physical erasing units is less than the threshold value, executing a first program; the first program includes: moving a plurality of effective data in the physical erasing unit to at least one third idle physical erasing unit in the physical erasing unit; and adjusting the threshold value from the first threshold value to a second threshold value. The invention can solve the problem of unstable data access speed caused by the fact that the rewritable nonvolatile memory storage device carries out the moving of effective data.

Description

Memory management method, memory control circuit unit and memory storage device

Technical Field

The present invention relates to a memory management mechanism, and more particularly, to a memory management method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, cell phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years.

Generally, the rewritable nonvolatile memory storage device executes a valid data transfer and reassembly program once at intervals, and the basis for determining whether to execute the valid data transfer and reassembly program is determined when the rewritable nonvolatile memory storage device is shipped. However, the execution efficiency of the effective data moving and reorganizing program is good and bad, which often results in the data access speed of the rewritable nonvolatile memory storage device being neglected.

Therefore, it is one of the objectives of the art to balance the execution of the valid data relocation and reassembly procedure and the maintenance of the data access speed of the rewritable nonvolatile memory storage device.

Disclosure of Invention

The invention provides a memory management method, a memory control circuit unit and a memory storage device, which can solve the problem of unstable data access speed of a rewritable nonvolatile memory storage device caused by the fact that effective data are moved.

An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory management method comprises the steps of receiving a first write command and writing data corresponding to the first write command into a first idle physical erasing unit in the physical erasing units; detecting a number of second idle physical erase units of the physical erase units that do not include the first idle physical erase unit; judging whether the number of the second idle physical erasing units is smaller than a threshold value; if the number of the second idle physical erasing units is smaller than the threshold value, executing a first program, wherein the first program comprises moving a plurality of effective data in the physical erasing units to at least one third idle physical erasing unit in the physical erasing units; and adjusting the threshold value from a first threshold value to a second threshold value.

In an exemplary embodiment of the present invention, the step of adjusting the threshold value from the first threshold value to the second threshold value includes recording the number of the at least one third idle physical erase unit storing valid data; and determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data.

In an exemplary embodiment of the invention, the step of recording the number of the at least one third idle physical erase unit storing valid data comprises: judging whether the number of a plurality of first non-idle physical erasing units of which the valid data stored in the physical erasing units are moved accords with a preset number or not; and recording the number of the at least one third idle physical erase unit storing valid data if the number of the first non-idle physical erase units meets the preset number.

In an exemplary embodiment of the present invention, the determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data comprises determining a difference between the first threshold and the second threshold according to a reference value corresponding to the predetermined number and the number of the at least one third idle physical erase unit storing valid data, wherein the reference value is the predetermined number minus one.

In an exemplary embodiment of the invention, the memory management method further includes configuring a plurality of logic units; and determining the preset number according to the total physical capacity of the physical erasing units and the total logical capacity of the logical units, wherein the total physical capacity is larger than the total logical capacity.

In an exemplary embodiment of the present invention, the first procedure further includes selecting the first non-idle physical erase unit from the physical erase units according to a first rule; and after determining that the number of the first non-idle physical erase units meets the preset number, selecting at least one second non-idle physical erase unit not including the first non-idle physical erase unit from the physical erase units according to a second rule, wherein the first rule is different from the second rule.

In an exemplary embodiment of the invention, the memory management method further includes receiving a second write command after executing the first program; detecting a number of a fourth plurality of idle physical erase units in the physical erase units; judging whether the number of the fourth idle physical erasing units is larger than the second threshold value; and if the number of the fourth idle physical erase units is greater than the second threshold, stopping executing the first program and adjusting the threshold from the second threshold to a third threshold.

In an exemplary embodiment of the present invention, the third threshold is equal to the first threshold.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for receiving a first write command and sending a write command sequence to indicate that data corresponding to the first write command is written into a first idle physical erasing unit in the physical erasing units. The memory management circuit is further configured to detect a number of second idle physical erase units, which do not include the first idle physical erase unit, among the physical erase units, and determine whether the number of the second idle physical erase units is less than a threshold value. The memory management circuit is further configured to execute a first procedure if the number of second idle physical erase units is less than the threshold value. The first program comprises a plurality of effective data in the physical erasing units are moved to at least one third idle physical erasing unit in the physical erasing units; and adjusting the threshold value from a first threshold value to a second threshold value.

In an exemplary embodiment of the present invention, the operation of the memory management circuit adjusting the threshold value from the first threshold value to the second threshold value includes recording the number of the at least one third idle physical erase unit storing valid data; and determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data.

In an exemplary embodiment of the invention, the operation of the memory management circuit recording the number of the at least one third idle physical erase unit storing valid data includes determining whether the number of first non-idle physical erase units in which all valid data stored in the physical erase units have been shifted matches a predetermined number; and recording the number of the at least one third idle physical erase unit storing valid data if the number of the first non-idle physical erase units meets the preset number.

In an exemplary embodiment of the present invention, the operation of the memory management circuit determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data comprises determining a difference between the first threshold and the second threshold according to a reference value corresponding to the predetermined number and the number of the at least one third idle physical erase unit storing valid data, wherein the reference value is the predetermined number minus one.

In an exemplary embodiment of the invention, the memory management circuit is further configured to configure a plurality of logic units, and determine the predetermined number according to a total physical capacity of the physical erase unit and a total logical capacity of the logic units, wherein the total physical capacity is greater than the total logical capacity.

In an example embodiment of the present invention, the operation in which the memory management circuit executes the first program further includes selecting the first non-idle physical erase unit from the physical erase units according to a first rule; and after determining that the number of the first non-idle physical erase units meets the preset number, selecting at least one second non-idle physical erase unit not including the first non-idle physical erase unit from the physical erase units according to a second rule, wherein the first rule is different from the second rule.

In an exemplary embodiment of the invention, the memory management circuit is further configured to receive a second write command after the first program is executed. The memory management circuit is further configured to detect a number of fourth idle physical erase units in the physical erase units, and determine whether the number of the fourth idle physical erase units is greater than the second threshold. If the number of the fourth idle physical erase units is greater than the second threshold, the memory management circuit is further configured to stop executing the first program and adjust the threshold from the second threshold to a third threshold.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for receiving a first write command and sending a write command sequence to instruct to write data corresponding to the first write command into a first idle physical erasing unit in the physical erasing units. The memory control circuit unit is further configured to detect a number of second idle physical erase units, which do not include the first idle physical erase unit, among the physical erase units, and determine whether the number of the second idle physical erase units is less than a threshold value. The memory control circuit unit is further configured to execute a first procedure if the number of the second idle physical erase units is less than the threshold value. The first program comprises a plurality of effective data in the physical erasing units are moved to at least one third idle physical erasing unit in the physical erasing units; and adjusting the threshold value from a first threshold value to a second threshold value.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the threshold value from the first threshold value to the second threshold value includes recording the number of the at least one third idle physical erase unit storing valid data; and determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit recording the number of the at least one third idle physical erase unit storing valid data includes determining whether the number of first non-idle physical erase units in which all valid data stored in the physical erase units have been shifted matches a predetermined number; and recording the number of the at least one third idle physical erasing unit for storing valid data if the number of the first non-idle physical erasing units accords with the preset number.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data includes determining a difference between the first threshold and the second threshold according to a reference value corresponding to the predetermined number and the number of the at least one third idle physical erase unit storing valid data, wherein the reference value is the predetermined number minus one.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to configure a plurality of logic units, and determine the predetermined number according to a total physical capacity of the physical erase unit and a total logical capacity of the logic units, wherein the total physical capacity is greater than the total logical capacity.

In an exemplary embodiment of the present invention, the operation in which the memory control circuit unit executes the first program further includes selecting the first non-idle physical erase unit from the physical erase units according to a first rule; and after determining that the number of the first non-idle physical erase units meets the preset number, selecting at least one second non-idle physical erase unit not including the first non-idle physical erase unit from the physical erase units according to a second rule, wherein the first rule is different from the second rule.

In an exemplary embodiment of the invention, after the first program is executed, the memory control circuit unit is further configured to receive a second write command and detect a number of a fourth plurality of idle physical erase units among the physical erase units. The memory control circuit unit is further configured to determine whether the number of the fourth idle physical erase units is greater than the second threshold. If the number of the fourth idle physical erase units is greater than the second threshold, the memory control circuit unit is further configured to stop executing the first program and adjust the threshold from the second threshold to a third threshold.

Based on the above, the memory management method, the memory control circuit unit and the memory storage device provided by the invention can dynamically adjust the threshold value for determining whether to execute the moving operation of the valid data. Therefore, the data access speed of the rewritable nonvolatile memory module can be more stable by controlling the transfer operation of the trigger effective data.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 2 is a diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram illustrating the memory storage device shown in FIG. 1;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIGS. 7A and 7B are schematic diagrams illustrating a first process according to an exemplary embodiment of the present invention;

FIG. 8 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

Description of reference numerals:

10: a memory storage device;

11: a host system;

12: a computer;

122: a microprocessor;

124: a random access memory;

126: a system bus;

128: a data transmission interface;

13: input/output (I/O) devices;

21: a mouse;

22: a keyboard;

23: a display;

24: a printer;

25: a portable disk;

26: a memory card;

27: a solid state disk;

31: a digital camera;

32: an SD card;

33: an MMC card;

34: a memory stick;

35: a CF card;

36: an embedded storage device;

402: a connection interface unit;

404: a memory control circuit unit;

406: a rewritable non-volatile memory module;

502: a memory management circuit;

504: a host interface;

506: a memory interface;

508: an error checking and correcting circuit;

510: a buffer memory;

512: a power management circuit;

600(0) to 600 (R): a physical erase unit;

610(0) to 610 (D): a logic unit;

602: a storage area;

606: a system area;

s801 to S806: and (5) carrying out the following steps.

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention. FIG. 2 is a diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment of the invention.

Referring to FIG. 1, a host system 11 generally includes a computer 12 and an input/output (I/O) device 13. Computer 12 includes a microprocessor 122, a Random Access Memory (RAM) 124, a system bus 126, and a data transfer interface 128. The input/output device 13 includes a mouse 21, a keyboard 22, a display 23, and a printer 24 as shown in fig. 2. It should be understood that the device shown in fig. 2 is not limited to the input/output device 13, and that the input/output device 13 may include other devices.

In an exemplary embodiment, the memory storage device 10 is electrically connected to other components of the host system 11 through the data transmission interface 128. Data may be written to or read from memory storage device 10 by operation of microprocessor 122, random access memory 124 and input/output device 13. For example, the memory storage device 10 can be a rewritable nonvolatile memory storage device such as a flash Drive 25, a memory card 26, or a Solid State Drive (SSD) 27 shown in fig. 2.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention.

In general, host system 11 is any system that may substantially cooperate with memory storage device 10 to store data. Although the host system 11 is illustrated as a computer system in the present exemplary embodiment, the host system 11 may be a digital camera, a video camera, a communication device, an audio player, a video player, or the like in another exemplary embodiment. For example, when the host system is a digital camera (camcorder) 31, the rewritable nonvolatile memory storage device is an SD card 32, an MMC card 33, a memory stick (memory stick)34, a CF card 35, or an embedded storage device 36 (as shown in fig. 3). The Embedded storage device 36 includes an Embedded multimedia card (eMMC). It should be noted that the embedded multimedia card is directly electrically connected to the substrate of the host system.

Fig. 4 is a schematic block diagram illustrating the memory storage device shown in fig. 1.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the Multimedia Memory Card (Multimedia Card) interface standard, eMMC) interface standard, Universal Flash memory (Universal Flash Storage, short for: UFS) interface standard, Compact Flash (short for: CF) interface standard, Integrated Device Electronics (abbreviated: IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a software type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit of data in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking and correcting circuit 508.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to write, read, and erase data during operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in the form of software. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a physical unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The physical unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The physical unit management circuit is used for managing a physical erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction sequence to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations.

The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the command sequences may include a write command sequence for indicating writing data, a read command sequence for indicating reading data, an erase command sequence for indicating erasing data, and corresponding command sequences for indicating various memory operations (e.g., changing the read voltage level or performing a garbage collection procedure, etc.), which are not described herein in detail. The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes the read identification code, the memory address, and other information.

The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting processes to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512. The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. It should be understood that when describing the operation of the physical erase unit of the rewritable nonvolatile memory module 406, it is a logical concept to operate the physical erase unit by the words "select", "group", "partition", "associate", and the like. That is, the physical erase unit of the rewritable nonvolatile memory module is not physically located, but is logically operated.

The memory cells of the rewritable nonvolatile memory module 406 constitute a plurality of physical programming units, and the physical programming units constitute a plurality of physical erasing units 600(0) -600 (R). Specifically, the memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, in MLC NAND flash memory, the Least Significant Bit (LSB) of a cell belongs to the lower physical programming cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical programming cell. Generally, the writing speed of the lower physical program unit is greater than that of the upper physical program unit, or the reliability of the lower physical program unit is higher than that of the upper physical program unit.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical program cell is the smallest unit to which data is written. For example, a physical programming unit is a physical page or a physical fan (sector). If the physical programming units are physical pages, each physical programming unit generally includes a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., error correction codes). In the exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, 8, 16, or a greater or lesser number of physical fans may be included in the data bit region, and the size of each physical fan may also be greater or lesser. On the other hand, the physical erase unit is the minimum unit of erase. That is, each physical erase unit contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block.

Referring to FIG. 6, the memory management circuit 502 can logically divide the physical erase units 600(0) -600 (R) of the rewritable nonvolatile memory module 406 into a plurality of areas, such as a storage area 602 and a system area 606.

The physical erase unit of the storage area 602 is used to store data from the host system 11. The memory area 602 stores valid data and invalid data. For example, when a host system is to delete a copy of valid data, the deleted data may still be stored in storage area 602, but may be marked as invalid data. In the following exemplary embodiments, a physical erase unit that does not store valid data is also referred to as an idle (spare) physical erase unit. For example, the physical erase unit after being erased becomes an idle physical erase unit. In addition, in the following exemplary embodiments, there are physical erase units storing valid data, which are also referred to as non-spare physical erase units.

In an example embodiment, if there is a defect in the memory area 602 or the system area 606, the physical erase unit in the memory area 602 may also be used to replace the defective physical erase unit. If there are no physical erase units available in the storage area 602 to replace the defective physical erase units, the memory management circuitry 502 may declare the entire memory storage 10 to be in a write protect (write protect) state and no longer write data.

The physical erase units of the system area 606 are used to record system data, wherein the system data includes information about the manufacturer and model of the memory chip, the number of physical erase units of the memory chip, the number of physical program units per physical erase unit, and the like.

In an example embodiment, the number of physical erase units of the memory area 602 and the system area 606 may vary according to different memory specifications. In addition, it should be understood that the grouping relationship of the physical erase units associated with the memory areas 602 and the system areas 606 may change dynamically during the operation of the memory storage device 10. For example, when a physical erase unit in the system area 606 is damaged and replaced by a physical erase unit of the storage area 602, the physical erase unit originally in the storage area 602 is associated with the system area 606.

In the exemplary embodiment, memory management circuitry 502 configures logical units 610(0) - (610D) to map to physical erase units 600(0) - (600A) in memory area 602. For example, in the present exemplary embodiment, the host system 11 accesses the data in the storage area 602 by the logical address, and therefore, each of the logical units 610(0) - (610D) refers to a logical address. In addition, in an exemplary embodiment, each of the logic units 610(0) - (610D) may also refer to a logic fan, a logic programming unit, a logic erasing unit, or a plurality of consecutive logic addresses.

In the exemplary embodiment, each of logic units 610(0) - (610D) is mapped to one or more physical units. In the present exemplary embodiment, one physical unit refers to one physical erase unit. However, in another exemplary embodiment, a physical unit may be a physical address, a physical fan, a physical programming unit, or be composed of a plurality of consecutive physical addresses, and the present invention is not limited thereto. The memory management circuit 502 records the mapping relationship between the logical unit and the physical unit in at least one logical-to-physical mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-to-physical mapping table.

Generally, after receiving a write command from the host system 11, the free physical erase unit in the storage area 602 is used to store data corresponding to the write command. If the idle physical erase units in the memory area 602 are not sufficient, the memory management circuit 502 instructs the rewritable nonvolatile memory module 406 to perform a data merging procedure. In an exemplary embodiment, the data merging procedure is also called a garbage collection (garbel collection) procedure.

In the data merging procedure, part of valid data scattered in the memory area 602 is collected and collectively moved to some idle physical erase units to release the physical erase units storing invalid data. If a piece of data originally marked as valid data is moved from a non-idle physical erase unit, the piece of data is marked as invalid data in the non-idle physical erase unit. If all valid data stored in a non-idle physical erase unit has been moved out (i.e. all data stored in the non-idle physical erase unit has been marked as invalid data), the non-idle physical erase unit can be erased to become a new idle physical erase unit. On the other hand, the idle physical erase unit used to store the collected valid data in the data merging procedure becomes a new non-idle physical erase unit.

In the exemplary embodiment, the memory management circuit 502 receives a write command (hereinafter also referred to as a first write command) from the host system 11 and selects a physical erase unit from the memory area 602 according to the first write command. In the present exemplary embodiment, the selected physical erase unit is an idle physical erase unit (hereinafter also referred to as a first idle physical erase unit). However, in another exemplary embodiment, the selected physical erase unit may be an idle physical erase unit that already stores other write data.

The memory management circuit 502 sends a write command sequence to the rewritable nonvolatile memory module 406 to instruct to write data (hereinafter also referred to as first data) corresponding to the first write command into the first idle physical erase unit. For example, the first data is the data indicated by the write command to be stored. After selecting the first idle physical erase unit, the memory management circuit 502 detects the number of idle physical erase units (hereinafter also referred to as second idle physical erase units) in the memory area 602 that do not include the first idle physical erase unit. For example, the number of second idle physical erase units is the total number of idle physical erase units remaining in the memory area 602 after the first idle physical erase unit is selected.

The memory management circuit 502 determines whether the number of second idle physical erase units is less than a threshold. For example, the operation of determining whether the number of second idle physical erase units is less than the threshold is performed in response to the memory management circuit 502 receiving a first write command or selecting a first idle physical erase unit. The threshold value can be used as a basis for determining whether the number of remaining idle physical erase units in the memory area 602 is sufficient. For example, in the exemplary embodiment, the threshold value may be "6". However, in another exemplary embodiment, the threshold value may be a larger or smaller positive integer. If the number of second idle physical erase units is less than the threshold, it indicates that the remaining idle physical erase units in the memory area 602 are about to be insufficient, so the memory management circuit 502 performs a data merging procedure (hereinafter also referred to as a first procedure) to release the physical erase units with invalid data. However, if the number of second idle physical erase units is not less than the threshold, it indicates that the number of idle physical erase units remaining in the memory area 602 is still sufficient, so the memory management circuit 502 may choose not to perform the first procedure.

If it is determined to execute the first program, the memory management circuit 502 selects another idle physical erase unit from the memory area 602 to store valid data collected in the first program. After determining to execute the first program, corresponding to the memory management circuit 502 writing a data from the host system 11 into one of the first idle physical erase units, a plurality of data (i.e. valid data) are moved from "N" consecutive or non-consecutive physical program units in the storage area 602 to the idle physical erase unit for storing valid data collected in the first program until the first program is stopped. The "N" contiguous or non-contiguous physical program cells may be included in one or more physical erase cells. For example, if "N" is "2", in the first program, corresponding to writing the first data into one of the first idle physical erase units, "2" valid data are moved from "2" consecutive or discontinuous physical program units in the storage area 602 to the idle physical erase unit for storing the collected valid data.

If more write commands are received before the first program is stopped, more data from the host system 11 will be stored in the first idle physical erase unit and more valid data from the storage area 602 will be collected and concentrated in the idle physical erase unit for storing the collected valid data. If the first free physical erase unit is already or will be full, more free physical erase units may be selected to store data from the host system 11. In the following exemplary embodiment, each idle physical erase unit of the first program selected to store data from the host system 11 may also be referred to as a first idle physical erase unit.

If one or more idle physical erase units currently selected to store the collected valid data are full or are about to be full before the first process is stopped, more idle physical erase units may be selected and used to store the collected valid data. In the following exemplary embodiment, the idle physical erase unit of the first program expected to be selected to store the collected valid data may also be referred to as a third idle physical erase unit.

In the first procedure, the memory management circuit 502 selects a plurality of idle physical erase units (i.e., third idle physical erase units) from the storage area 602 and instructs the rewritable nonvolatile memory module 406 to move valid data stored in the non-idle physical erase units of the storage area 602 to the third idle physical erase units. For example, in an exemplary embodiment, the first procedure is to write the collected valid data to "N" idle physical erase units (i.e., the third idle physical erase unit) in advance to release at least "N + 1" new physical erase units available for storing data from the host system 11. Each idle physical erase unit for storing the collected valid data becomes a non-idle physical erase unit, and each non-idle physical erase unit for storing the valid data that has been moved out becomes an idle physical erase unit.

In the first procedure, the memory management circuit 502 also adjusts the threshold value for determining whether to execute the first procedure from a current value (hereinafter also referred to as a first threshold value) to another value (hereinafter also referred to as a second threshold value). In the present exemplary embodiment, the second threshold is greater than the first threshold. After determining to stop the first process, the memory management circuit 502 adjusts the threshold value from the second threshold value to another value (hereinafter also referred to as a third threshold value). In an exemplary embodiment, the first threshold, the second threshold and the third threshold are each a predetermined value, which does not change with the execution of the first process. However, in the exemplary embodiment, the first threshold is a predetermined value, the second threshold is determined in real time according to the execution status of the first program, and the third threshold is equal to the first threshold.

In the exemplary embodiment, during the process of moving the valid data to the third idle physical erase unit, the memory management circuit 502 determines whether the number of non-idle physical erase units (hereinafter also referred to as the first non-idle physical erase unit) in which the stored valid data are moved matches a predetermined number. For example, the predetermined number is "N + 1". After the valid data is completely moved out of a first non-idle physical erasing unit, the first non-idle physical erasing unit becomes a released idle physical erasing unit. Therefore, in an exemplary embodiment, the operation of determining whether the number of the first non-idle physical erase units meets the predetermined number may be regarded as the operation of determining whether the number of the idle physical erase units released in the first procedure reaches the predetermined number.

If the number of the first non-idle physical erase units is determined to meet the predetermined number, the memory management circuit 502 records the number of at least one physical erase unit currently storing the valid data moved in the first program. In other words, in some exemplary embodiments, the third idle physical erase unit is a physical erase unit that is preset in the first program and is used to store the collected valid data, and the number of the at least one physical erase unit that stores the moved valid data in the first program refers to the total number of physical erase units that currently store the collected valid data in the third idle physical erase units. The memory management circuit 502 determines the second threshold according to the recorded number (i.e. the number of at least one physical erase unit currently storing valid data to be shifted in the first procedure).

Fig. 7A and 7B are schematic diagrams illustrating a first procedure according to an exemplary embodiment of the invention.

Referring to FIG. 7A, in the first procedure, it is expected that "N + 1" idle physical erase units will be released only when valid data that can be written to "N" idle physical erase units (i.e., the third idle physical erase unit) is collected.

Referring to fig. 7B, in the exemplary embodiment, if only valid data written or full with "M" physical erase units is collected in the first procedure, and "N + 1" physical erase units are released, the value "M" is recorded. M may be a positive integer less than or equal to N.

In the present exemplary embodiment, the memory management circuit 502 determines the difference between the first threshold and the second threshold according to a reference value corresponding to the predetermined number and the recorded number (e.g., "M"). Then, the memory management circuit 502 determines the second threshold according to the difference. For example, assuming that the preset number is "N + 1", the reference value corresponding to the preset number may be set to "N" (i.e., the preset number is reduced by one), and the memory management circuit 502 may subtract "M" from the reference value "N" to obtain a difference "E" (i.e., E ═ N-M) between the first threshold and the second threshold. Thereafter, the memory management circuit 502 may add the current first threshold "T1" to the difference "E" to obtain a second threshold "T2" (i.e., T2 ═ T1+ E).

It should be noted that, in the above exemplary embodiment, the difference between the second threshold and the first threshold is related to the distribution of valid data to be collected in the memory area 602 in the first program or the execution efficiency of the first program. For example, if the distribution of valid data to be collected in the first program in the storage area 602 is more concentrated (i.e., if valid data is collected from a few non-idle physical erase units, a predetermined number of new idle physical erase units can be released), the recorded "M" may be smaller, and the difference between the second threshold "T2" and the first threshold "T1" may be larger; conversely, if the distribution of valid data to be collected in the first procedure in the storage area 602 is more distributed (i.e., valid data needs to be collected from a number of non-idle physical erase units to release a new number of idle physical erase units corresponding to the predetermined number), the recorded "M" may be larger (e.g., M may approach N), and the difference between the second threshold "T2" and the first threshold "T1" may be smaller.

In addition, it should be noted that, in the above exemplary embodiment, the concept of calculating the second threshold value "T2" can be simplified as follows: the second threshold value "T2" — the first threshold value "T1" + the reference value "N" — the recorded "M". However, in another exemplary embodiment, the concept can be implemented with any logic operation based on practical requirements. Alternatively, in another exemplary embodiment, the first threshold "T1", the reference value "N" (or the predetermined number "N + 1"), and the recorded parameters "M" may be input into a predetermined algorithm or a table lookup may be performed to obtain the second threshold "T2".

In an exemplary embodiment, the memory management circuit 502 further determines the predetermined number (or the reference value) according to a total capacity of all the physical erase units in the memory area 602 (hereinafter also referred to as a total physical capacity) and a total capacity of all the available logical units configured (hereinafter also referred to as a total logical capacity). Wherein the total physical capacity may be greater than the total logical capacity. For example, the total logical capacity is equal to a maximum capacity set by the host system 11 or the memory management circuit 502 for storing user data.

For example, in the exemplary embodiment of FIG. 8, assuming that all of the available logical units 610(0) to 610(D) corresponding to the rewritable nonvolatile memory module 406 can be or have been used to store valid data and the storage area 602 includes the physical erase units 600(0) to 600(A), the predetermined number "N + 1" (or the reference value "N") can be determined according to the total logical capacity "L" of the logical units 610(0) to 610(D) and the total physical capacity "P" of the physical erase units 600(0) to 600 (A). For example, the following can be followed: total logical capacity "L"/(total physical capacity "P" -total logical capacity "L") to obtain reference value "N". In the present exemplary embodiment, if the preliminarily calculated reference value "N" is not a positive integer, then: the result of the total logical capacity "L"/(total physical capacity "P" -total logical capacity "L") takes the decimal point rounded off, takes the decimal point unconditional carry, takes the gaussian or takes some nearest meaningful (e.g., 2 to the power) positive integer, etc. to obtain the reference value "N". In another exemplary embodiment, the operation of obtaining the reference value "N" may be implemented with any logic operation according to practical requirements. In addition, in another exemplary embodiment, the total logical capacity "L" and the total physical capacity "P" may be input into a predetermined algorithm or a table lookup to obtain the reference value "N" (or the predetermined number "N + 1").

In another example embodiment of FIG. 8, the total physical capacity "P" may also include the capacity of at least one physical erase unit in the system area 606. In an exemplary embodiment, the total physical capacity may be replaced by a total number of physical units (e.g., physical erase units) used to calculate the total physical capacity, and the total logical capacity may be replaced by a total number of logical units used to calculate the total logical capacity. In an exemplary embodiment, the calculated "N" is, for example, "32", but if the specifications of the memory storage devices 10 are different, the "N" may be a larger or smaller positive integer.

After the first program starts to be executed, if the memory management circuit 502 receives another write command (hereinafter also referred to as a second write command) from the host system 11, the memory management circuit 502 detects the number of idle physical erase units (hereinafter also referred to as a fourth idle physical erase unit) currently in the storage area 602. For example, the number of the fourth idle physical erase units refers to the total number of all idle physical erase units currently in the memory area 602, and the fourth idle physical erase units may include the idle physical erase unit released in the first procedure. The memory management circuit 502 determines whether the number of the fourth idle physical erase units is greater than a threshold.

It should be noted that in the present exemplary embodiment, the threshold value is adjusted from the first threshold value to the second threshold value, so that the memory management circuit 502 actually determines whether the number of the fourth idle physical erase units in the memory area 602 is greater than the second threshold value. If the number of the fourth idle physical erase units is not greater than the second threshold, the memory management circuit 502 continues to execute the first process. How to execute the first program is described above, and therefore, the description thereof is omitted here. In addition, if the number of the fourth idle physical erase units is greater than the second threshold, the memory management circuit 502 stops executing the first program.

In the exemplary embodiment, if it is determined to stop executing the first program, the memory management circuit 502 further adjusts the threshold for determining whether to execute the first program from the second threshold back to the predetermined first threshold. Thus, after the first program is stopped, if it is necessary to determine whether the remaining idle physical erase units are enough corresponding to a certain write command from the host system 11, the memory management circuit 502 will use the first threshold value again to determine whether to execute the next first program. If the next first program is determined to be executed, the memory management circuit 502 determines the corresponding second threshold again according to the execution status of the first program. Thereafter, the memory management circuit 502 determines whether to stop executing the first program according to the determined second threshold and adjusts the threshold again corresponding to the stop of executing the first program (e.g., adjusts the threshold again from the second threshold back to the first threshold or other values, etc.). Operations of how to determine whether to execute the first program by using the first threshold, how to determine the corresponding second threshold, and how to stop the first program by using the second threshold are described in the above exemplary embodiments, and thus are not described herein.

In other words, compared to the method for determining whether to start executing the data merging procedure and the method for determining whether to stop executing the data merging procedure both use the same threshold value, the present invention can correspondingly set the threshold value for stopping the data merging procedure according to the execution status of each data merging procedure. For example, after the execution of the data merging procedure is determined to start, the threshold corresponding to the stop of the data merging procedure may be increased according to the execution status of the current data merging procedure, so as to prolong the execution of the data merging procedure.

In an exemplary embodiment, if the number of the first non-idle physical erase units is detected to meet the predetermined number, the rule for selecting the non-idle physical erase units in the first program from which valid data is to be extracted may be changed. For example, in an exemplary embodiment, before detecting that the number of the first non-idle physical erase units meets the predetermined number, the memory management circuit 502 selects the non-idle physical erase unit (i.e., the first non-idle physical erase unit) from the memory area 602 to extract valid data according to a predetermined rule (hereinafter also referred to as a first rule). For example, the first rule may include selecting the non-idle physical erase unit having better moving efficiency for valid data, such as storing less valid data than a predetermined value or storing more invalid data than the predetermined value. After detecting that the number of the first non-idle physical erase units meets the predetermined number, the memory management circuit 502 selects at least one non-idle physical erase unit (hereinafter also referred to as a second non-idle physical erase unit) from the memory area 602, which still needs to be extracted with valid data in the first procedure, according to another predetermined rule (hereinafter also referred to as a second rule). Wherein the second rule is different from the first rule. For example, the second rule may include selecting a non-idle physical erase unit that stores more valid data than the predetermined value, stores less invalid data than the predetermined value, or randomly selects a physical erase unit that is less efficient in moving valid data.

Taking the example embodiment of fig. 7A and 7B as an example, it is assumed that valid data that can be written to "N" idle physical erase units (i.e., the third idle physical erase unit) is scheduled to be collected in the first procedure (as shown in fig. 7A), but "N + 1" new idle physical erase units are released when valid data that can be written to "M" physical erase units is collected (as shown in fig. 7B). In this case, the valid data written to the "M" physical erase units is, for example, extracted from a plurality of non-idle physical erase units (i.e., first non-idle physical erase units) selected according to a first rule, and the valid data written to the remaining "N-M" or more idle physical erase units is, for example, extracted from non-idle physical erase units (i.e., second non-idle physical erase units) selected according to a second rule.

In other words, the first rule is more strict for screening non-idle physical erase units than the second rule, and selecting non-idle physical erase units according to the first rule may consume more system resources than selecting non-idle physical erase units according to the second rule. Therefore, in an exemplary embodiment, after detecting that the predetermined number of free physical erase units has been released, system resources consumed in finding the free physical erase units can be saved by using the second rule to select the remaining non-free physical erase units from which valid data is to be extracted. In addition, in another exemplary embodiment, it may also be maintained to use the first rule or the second rule to select all non-idle physical erase units from which valid data is to be extracted in the first procedure, which is not limited in the present invention.

Referring to fig. 8, in step S801, a write command is received, and an idle physical erase unit is selected from a plurality of physical erase units of the rewritable nonvolatile memory module according to the write command to write data corresponding to the write command. In step S802, the number of remaining idle physical erase units of the physical erase units that do not include the idle physical erase unit selected in step S801 is detected. In step S803, it is determined whether the number of idle physical erase units detected in step S802 is less than a threshold. Here, the threshold is a first threshold. If the detected number of idle physical erase units is not less than the first threshold, step S801 may be repeated.

If the number of the remaining idle physical erase units is smaller than the first threshold, in step S804, a data merging procedure (i.e., the first procedure) is performed to release new idle physical erase units. In addition, in step S804, the first threshold for determining whether to execute the first process is adjusted according to the execution status of the first process. Here, the threshold value is adjusted from the first threshold value to the second threshold value. How to execute the first procedure and how to adjust the threshold value are described in the foregoing exemplary embodiments, and are not described herein again.

In step S805, it is determined whether the number of idle physical erase units in the rewritable nonvolatile memory module is greater than the second threshold set in step S804. If the determination result in step S805 is "no", it indicates that the number of idle physical erase units is still insufficient, so step S804 is repeated to release more idle physical erase units. If the determination result in step S805 is yes, in step S806, the execution of the first routine is stopped and the threshold value is adjusted again. For example, the threshold value is adjusted from the current second threshold value to the third threshold value. For example, the second threshold may be the first threshold or any predetermined value. After step S806, step S801 is repeated.

It should be noted that, in step S804, it may be further determined whether the currently used threshold is the first threshold (or the second threshold). If the currently used threshold is the first threshold, the threshold can be adjusted to the second threshold according to the execution status of the executing first program. If the threshold value currently in use is not the first threshold value, for example, the threshold value currently in use is already the adjusted second threshold value, the threshold value will not be adjusted again. Therefore, the threshold value can be prevented from being repeatedly adjusted.

However, the steps in fig. 8 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 8 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 8 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, the memory management method, the memory control circuit unit and the memory storage device provided by the invention can dynamically adjust the threshold value for determining whether to execute the move operation (i.e. the data merging procedure) for the valid data. In particular, when the release efficiency of the idle physical erase unit is good, the adjustment range of the threshold value can be increased; when the release efficiency of the idle physical erase unit is not good, the adjustment range of the threshold value can be reduced. Therefore, the data access speed of the rewritable nonvolatile memory module can be more stable by controlling the triggering of the moving operation of the effective data, for example, prolonging the executed moving operation of the effective data.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical erasing units, the memory management method comprising:

receiving a first write-in command and writing data corresponding to the first write-in command into a first idle physical erase unit of a plurality of idle physical erase units in the physical erase units;

detecting a number of second idle physical erase units of the plurality of physical erase units that do not include the first idle physical erase unit, wherein the number of the second idle physical erase units is a total number of idle physical erase units remaining in the plurality of idle physical erase units after the first idle physical erase unit is selected;

judging whether the number of the second idle physical erasing units is less than a threshold value; and

if the number of the second idle physical erase units is less than the threshold value, executing a first procedure,

wherein the first program includes:

moving a plurality of effective data in the physical erasing units to at least one third idle physical erasing unit in the physical erasing units; and

the threshold value is adjusted from a first threshold value to a second threshold value.

2. The method of claim 1, wherein the step of adjusting the threshold value from the first threshold value to the second threshold value comprises:

recording the number of the at least one third idle physical erase unit storing valid data; and

determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data.

3. The method of claim 2, wherein the step of recording the number of the at least one third idle physical erase unit storing valid data comprises:

judging whether the number of a plurality of first non-idle physical erasing units of which the effective data stored in the physical erasing units are moved accords with a preset number or not; and

if the number of the first non-idle physical erasing units accords with the preset number, recording the number of the at least one third idle physical erasing unit for storing valid data.

4. The method of claim 3, wherein determining the second threshold based on the number of the at least one third idle physical erase unit storing valid data comprises:

determining a difference between the first threshold and the second threshold according to a reference value corresponding to the predetermined number and a number of the at least one third idle physical erase unit storing valid data,

wherein the reference value is the preset number minus one.

5. The memory management method of claim 3, further comprising:

configuring a plurality of logic units; and

determining the predetermined number according to the total physical capacity of the physical erase units and the total logical capacity of the logical units,

wherein the total physical capacity is greater than the total logical capacity.

6. The memory management method according to claim 3, wherein the first program further comprises:

selecting the first non-idle physical erase units from the physical erase units according to a first rule; and

selecting at least one second non-idle physical erase unit not including the first non-idle physical erase units from the physical erase units according to a second rule after determining that the number of the first non-idle physical erase units meets the preset number,

wherein the first rule is different from the second rule.

7. The memory management method of claim 1, further comprising:

receiving a second write instruction after executing the first program;

detecting the number of a plurality of fourth idle physical erasing units in the physical erasing units;

judging whether the number of the fourth idle physical erasing units is larger than the second threshold value or not; and

if the number of the fourth idle physical erase units is greater than the second threshold, the first program is stopped and the threshold is adjusted from the second threshold to a third threshold.

8. The method of claim 7, wherein the third threshold is equal to the first threshold.

9. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical erasing units; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is configured to receive a first write command and send a write command sequence to instruct data corresponding to the first write command to be written into a first idle physical erase unit of a plurality of idle physical erase units of the physical erase units,

wherein the memory management circuit is further configured to detect a number of second idle physical erase units of the plurality of physical erase units that do not include the first idle physical erase unit, wherein the number of the second idle physical erase units is a total number of idle physical erase units remaining in the plurality of idle physical erase units after the first idle physical erase unit is selected,

wherein the memory management circuit is further configured to determine whether the number of the second idle physical erase units is less than a threshold,

wherein if the number of the second idle physical erase units is less than the threshold value, the memory management circuit is further configured to execute a first procedure,

wherein the first program includes:

10. The memory control circuit unit of claim 9, wherein the operation of the memory management circuit to adjust the threshold value from the first threshold value to the second threshold value comprises:

11. The memory control circuit unit of claim 10, wherein the operation of the memory management circuit to record the number of the at least a third idle physical erase unit storing valid data comprises:

12. The memory control circuit unit of claim 11, wherein the operation of the memory management circuit determining the second threshold according to the number of the at least one third idle physical erase unit storing valid data comprises:

wherein the reference value is the preset number minus one.

13. The memory control circuit unit of claim 11, wherein the memory management circuit is further configured to configure a plurality of logic units,

wherein the memory management circuit is further configured to determine the predetermined number according to a total physical capacity of the physical erase units and a total logical capacity of the logical units,

wherein the total physical capacity is greater than the total logical capacity.

14. The memory control circuit unit of claim 11, wherein the memory management circuit to execute the operation of the first program further comprises:

wherein the first rule is different from the second rule.

15. The memory control circuit unit of claim 9, wherein the memory management circuit is further configured to receive a second write instruction after the first program is executed,

wherein the memory management circuit is further configured to detect a number of a fourth plurality of idle physical erase units in the plurality of physical erase units,

wherein the memory management circuit is further configured to determine whether the number of the fourth idle physical erase units is greater than the second threshold,

if the number of the fourth idle physical erase units is greater than the second threshold, the memory management circuit is further configured to stop executing the first program and adjust the threshold from the second threshold to a third threshold.

16. The memory control circuit unit of claim 15, wherein the third threshold is equal to the first threshold.

17. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of physical erasing units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to receive a first write command and send a write command sequence to instruct to write data corresponding to the first write command into a first idle physical erase unit of a plurality of idle physical erase units of the physical erase units,

wherein the memory control circuit unit is further configured to detect a number of second idle physical erase units of the plurality of physical erase units that do not include the first idle physical erase unit, wherein the number of the second idle physical erase units is a total number of idle physical erase units remaining in the plurality of idle physical erase units after the first idle physical erase unit is selected,

wherein the memory control circuit unit is further configured to determine whether the number of the second idle physical erase units is less than a threshold value,

wherein the memory control circuit unit is further configured to execute a first procedure if the number of the second idle physical erase units is less than the threshold value,

wherein the first program includes:

18. The memory storage device of claim 17, wherein the operation of the memory control circuit unit to adjust the threshold value from the first threshold value to the second threshold value comprises:

19. The memory storage device of claim 18, wherein the operation of the memory control circuit unit recording the number of the at least a third idle physical erase unit storing valid data comprises:

and recording the number of the at least one third idle physical erasing unit for storing the effective data if the number of the first non-idle physical erasing units accords with the preset number.

20. The memory storage device of claim 19, wherein the operation of the memory control circuit unit determining the second threshold value according to the number of the at least one third idle physical erase unit storing valid data comprises:

wherein the reference value is the preset number minus one.

21. The memory storage device of claim 19, wherein the memory control circuitry unit is further configured to configure a plurality of logic units,

wherein the memory control circuit unit is further configured to determine the predetermined number according to a total physical capacity of the physical erase units and a total logical capacity of the logical units,

wherein the total physical capacity is greater than the total logical capacity.

22. The memory storage device according to claim 19, wherein the operation of the memory control circuit unit to execute the first program further comprises:

wherein the first rule is different from the second rule.

23. The memory storage device of claim 17, wherein the memory control circuitry unit, after execution of the first program, is further to receive a second write instruction,

wherein the memory control circuit unit is further configured to detect a number of a fourth plurality of idle physical erase units among the physical erase units,

wherein the memory control circuit unit is further configured to determine whether the number of the fourth idle physical erase units is greater than the second threshold,

if the number of the fourth idle physical erase units is greater than the second threshold, the memory control circuit unit is further configured to stop executing the first program and adjust the threshold from the second threshold to a third threshold.

24. The memory storage device of claim 23, wherein the third threshold is equal to the first threshold.