CN106293616B - True Random Number Generator based on time delay feedback oscillator - Google Patents
True Random Number Generator based on time delay feedback oscillator Download PDFInfo
- Publication number
- CN106293616B CN106293616B CN201610665531.1A CN201610665531A CN106293616B CN 106293616 B CN106293616 B CN 106293616B CN 201610665531 A CN201610665531 A CN 201610665531A CN 106293616 B CN106293616 B CN 106293616B
- Authority
- CN
- China
- Prior art keywords
- time delay
- xor
- group
- random number
- xor gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
Abstract
The invention discloses a kind of True Random Number Generator based on time delay feedback oscillator, mainly solve the problems, such as that the generation true random number rate of real random number generator in the prior art is low and randomness is poor.It includes oscillating circuit and sample circuit, and the oscillating circuit is for generating Random Oscillation signal.It is same by several time delay feedback exclusive or oscillators and several time delay feedbacks or oscillator group is constituted, each time delay feedback exclusive or oscillator is made of an XOR gate and three upper phase inverter groups, each time delay feedback is same or oscillator is made of a same or door and three lower phase inverter groups, wherein each reverser group includes different number of phase inverter；The sample circuit is made of, the output of all d type flip flops passes through XOR gate generating rate in the true random number of 100Mbit/s or more for sampling to the Random Oscillation signal that oscillating circuit generates several d type flip flops and an XOR gate.The configuration of the present invention is simple, entropy source randomness are good, can be used for secret communication.
Description
Technical field
The invention belongs to digital circuit technique field more particularly to a kind of true random number based on time delay feedback oscillator are raw
It grows up to be a useful person, can be used for secret communication.
Background technique
In cryptographic system, either ciphertext information, image or video, random number play the role of critically important.
There are mainly of two types for existing random number, true random number and pseudo random number.Pseudo random number is easy to go to realize in software, pacify
Full property depends on the complexity and key seed of given algorithm, although having good statistical property, it cannot be guaranteed that it has
Unpredictability；True random number relies on uncertain entropy source, such as the simulation phenomenon in electronic device, has unpredictable well
Property.Therefore, for the cryptographic system high for security requirement, true random number becomes better choice.
In existing True Random Number Generator, it is random needed for system to provide much to all rely on external noise source
Property, such as original meaning, the patent (patent publication No. of Zhang Haifeng, Zhe：CN201773390U) based on resistance noise processing it is true with
Machine number generator, the oscillation for driving the structural generation of voltage controlled oscillator to have larger phase noise by extracting noise signal are believed
Number, and random number is obtained using post-processing；Patent (the patent publication No. of Wu Xiaoyong, Wang Xinya：CN103049243A) truly random
Number production methods and device, by by the amplification process of the quantization error in analog-to-digital conversion and digital-to-analogue conversion process, then with introducing
Thermal noise summation amplification to generate random number.And noise source have unstability, attacker can by attack noise source come
Entire generator is destroyed, therefore this method is not fool proof.In addition to this also have much based on oscillator configurations it is true with
Machine number generator, such as Feng Rui, diversiform-leaved poplar river, the patent (patent publication No. how to defend the country：CN103150138A) a kind of based on number electricity
The real random number generator on road, by the frequency control of fundamental oscillation sample circuit in secondary oscillation sample circuit and main oscillations sample circuit
End connection processed, then sampled to obtain true random number in fundamental oscillation sample circuit output end with post processing circuitry；Bai Guoqiang, it opens
Patent (the patent publication No. of Xiao Feng, Chen Hongyi：CN101819515A) true random number based on circular type shaker occur circuit and
Real random number generator is constituted using two high-frequency ring oscillating circuits and a low frequency annular oscillation circuit with input terminal
Circuit occurs for true random number, then post-processes to it.
It is external noise source that noise source is used in the above method, and attacker can be by control external noise source come its progress
Attack, therefore the safety of the true random number of this method generation cannot be guaranteed；Secondly certain methods be based on it is traditional by
The oscillator of reverser composition generates random number, due to the phase randomness in the oscillator signal short time of this oscillator
It is minimum, so
The sufficiently long time is had to wait for when sampling to ensure to sample output and have sufficient randomness, therefore these methods produce
The rate of raw random number is very low.
Summary of the invention
It is an object of the invention to be directed to the deficiency of above-mentioned prior art, propose a kind of based on the true of time delay feedback oscillator
Random number generator improves the safety of secret communication to avoid the attack to external input port.
To achieve the above object, the present invention includes：
Oscillating circuit, for generating the Random Oscillation signal with random phase offset；
Sample circuit, the Random Oscillation signal for generating to oscillating circuit sample, continuous analog signal are converted
It is exported for discrete digital signal.
It is characterized in that：
The oscillating circuit, including：N number of identical time delay feedback exclusive or oscillator, M identical time delay feedbacks are same or shake
Device is swung, N, M are the integer greater than 1, and meet N+M>3；
Each time delay feedback exclusive or oscillator is made of an XOR gate XOR and three upper reverser group R, each anti-
It is made of to device group R different even number reversers, XOR gate XOR is set there are three input port and an output port；This is different
Or output port of three input ports of door XOR respectively with three upper reverser group R is correspondingly connected with；XOR gate XOR's is defeated
Exit port is connect with the input port of each upper reverser group R；
Each time delay feedback with or oscillator by one with or door XNOR and three lower reverser group B constitute；Under each
Reverser group B is made of different odd number reversers, this with or door XNOR there are three input port and an output port,
Output port of same or door XNOR three input ports respectively with three lower reverser group B is correspondingly connected with；The same or door XNOR
Output port connect with the input port of each lower reverser group B.
The invention has the advantages that as follows：
1. the true random number stability generated is strong, output speed is high.
The present invention feeds back same or oscillator composition oscillating circuit due to using time delay feedback exclusive or oscillator and prolonging, therefore can produce
Raw stable chaotic oscillation, the chaotic oscillation have high frequency of oscillation and very wide frequency spectrum, are shaken using the stable chaos
Swing the true random number that can produce stable high speed.
2. oscillating circuit of the invention is same due to the time delay feedback exclusive or oscillator and time delay feedback that contain different number
Or oscillator, increase the diversity and flexibility of design.
3. the present invention is since entire randomizer is only realized by reverser, XOR gate and same or door, so circuit is easy
In integrated, miniaturization, can be widely applied in secure private chip.
Detailed description of the invention
Fig. 1 is the principle of the present invention block diagram；
Fig. 2 is circuit structure diagram of the invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to embodiments, to the present invention
It is described in further detail.It should be appreciated that specific embodiment described herein is used only for explaining the present invention, it is not used to limit
The fixed present invention.
Referring to Fig.1, the present invention includes oscillating circuit, sample circuit.Wherein oscillating circuit is different by N number of identical time delay feedback
Or oscillator, M identical time delay feedbacks are same or oscillator is constituted, for generating Random Oscillation signal；Sample circuit is by N+M
D type flip flop is constituted, and the Random Oscillation signal for generating to oscillating circuit samples, and sub-circuit is sampled in the sample circuit
Output port of the exclusive or as the sample circuit is passed through in output, exports true random number sequence.
Referring to Fig. 2, oscillating circuit of the invention and sample circuit structure are described as follows：
The oscillating circuit, including：N number of identical time delay feedback exclusive or oscillator, M identical time delay feedbacks are same or shake
Device is swung, N, M are the integer greater than 1 and meet N+M>3；
Each time delay feedback exclusive or oscillator is made of an XOR gate XOR and three upper reverser group R；
Three upper reverser group R are expressed as reverser group R on first1, reverser group R on second2, it is reversed in third
Device group R3, the reverser number on these three in reverser group R is different, is respectively：First upper reverser group R1It is anti-by 2
It is composed in series to device, second upper reverser group R2It is composed in series by 6 reversers, the upper reverser group R of third3It is anti-by 18
It is composed in series to device.
There are three input port, i.e. first input port, second input port, thirds by each XOR gate XOR
Input port and an output port；
Output port of three input ports of XOR gate XOR respectively with three upper reverser group R is correspondingly connected with, i.e. exclusive or
The first input port of door XOR and first upper reverser group R1Output port connection；The second input port of XOR gate XOR
With second upper reverser group R2Output port connection；Third input port and the third upper reverser group R of XOR gate XOR3
Output port connection；The output port of XOR gate XOR is connect with the input port of each upper reverser group R.
Each time delay feedback with or oscillator by one with or door XNOR and three lower reverser group B constitute；
Three lower reverser group B are expressed as first lower reverser group B1, second lower reverser group B2, third
Lower reverser group B3, the reverser number under these three in reverser group B is different, is respectively：First lower reverser group B1By
1 reverser is composed in series, second lower reverser group B2It is composed in series by 7 reversers, the lower reverser group B of third3By 17
A reverser is composed in series.
For it is each with or door XNOR, there are three input port, i.e. first input port, second input port,
Third input port and an output port；
With or output port of three input ports respectively with three lower reverser group B of door XNOR be correspondingly connected with, i.e., the
One input port and first lower reverser group B1Output port connection；Second input port and second lower reverser group B2
Output port connection；Third input port and the lower reverser group B of third3Output port connection.This is same or door XNOR
Output port connection is connect with the input port of each lower reverser group B.
The sample circuit is by N+M trigger D1, D2, D3 .., DN+M and 1 XOR gate i.e. N+1 XOR gate
XORN+1Composition, top n d type flip flop is connected with N number of XOR gate XOR in oscillating circuit respectively, rear M d type flip flop respectively with vibration
It swings a same or door XNOR of the M in circuit to be connected, the output of N+M trigger D1, D2, D3 .., the DN+M are as N+1 exclusive or
Door XORN+1Input, the N+1 XOR gate XORN+1Output of the output as sample circuit, the N+M trigger D1, D2,
D3 .., DN+M and 1 XOR gate i.e. N+1 XOR gate XORN+1It is controlled by identical clock, the clock is by external clock
CLK is provided.
Effect of the invention can be further illustrated by following testing result：
1, detection method：
Under the frequency driving that external clock is 100MHZ, the true random sequence of 1000 groups of 1M is generated；
The SP800-22 random number examination criteria provided using American National Standard and technical research institute NIST is to above-mentioned
The randomness of the true random sequence of 1000 groups of 1M is detected, which includes 15 detection contents, and each single item detection produces
It include a P-value value and a percent of pass Propotion value in raw testing result.When P-value value is not less than 0.001
And percent of pass value is not less than 0.9806, indicates that this detection content passes through.
2, testing result：
The SP800-22 random number examination criteria provided with American National Standard and technical research institute NIST is to the present invention
The true random sequence of the 1000 groups of 1M generated is detected, as a result such as table 1：
1 test result of table
| Statistical Test | P-value | Propotion | Result |
| Frequence | 0.969688 | 0.9944 | Pass |
| BlockFrequence | 0.456986 | 0.9861 | Pass |
| CumulativeSums | 0.762645 | 0.9953 | Pass |
| Runs | 0.314654 | 0.9888 | Pass |
| LongestRun | 0.125744 | 0.9888 | Pass |
| Rank | 0.404423 | 0.9860 | Pass |
| FFT | 0.479815 | 0.9860 | Pass |
| OverlappingTemplate | 0.290965 | 0.9888 | Pass |
| Universal | 0.206718 | 0.9842 | Pass |
| LinearComplexity | 0.504632 | 0.9879 | Pass |
| ApproximateEntropy | 0.297427 | 0.9925 | Pass |
| Serial | 0.305762 | 0.9879 | Pass |
| NonOverlappingTemplate | 0.293816 | 0.9851 | Pass |
| RandomExcursions | 0.173693 | 0.9876 | Pass |
| RandomExcursionsVariant | 0.707318 | 0.9892 | Pass |
As seen from Table 1, each index of the present invention generates true random sequence has reached the requirement standard of random number, shows
The random number that the present invention generates has good randomness.
Above-described embodiment, which is only used to be embodied, illustrates implementation method of the invention, is not construed as limiting the invention,
Obviously on the basis of this of the invention can there are many deformation, it is this be all contained in based on structure change of the invention it is of the invention
Within protection scope.
Claims (10)
1. based on the True Random Number Generator of time delay feedback oscillator, including：
Oscillating circuit, for generating the Random Oscillation signal with random phase offset；
Sample circuit, the Random Oscillation signal for generating to oscillating circuit sample, by continuous analog signal be converted into from
Scattered digital signal is exported；It is characterized in that：
The sample circuit, by N+M trigger D1, D2, D3 .., DN+M and 1 XOR gate i.e. N+1 XOR gate XORN+1Group
At, top n d type flip flop is connected with N number of XOR gate XOR in oscillating circuit respectively, rear M d type flip flop respectively with oscillating circuit
In M with or door XNOR be connected, the output of N+M trigger D1, D2, D3 .., the DN+M are as N+1 XOR gate XORN+1
Input, the N+1 XOR gate XORN+1Output of the output as sample circuit；
The oscillating circuit, including：N number of identical time delay feedback exclusive or oscillator, M identical time delay feedbacks are same or vibrate
Device, N, M are the integer greater than 1, and meet N+M>3；
Each time delay feedback exclusive or oscillator is made of an XOR gate XOR and three upper reverser group R, each upper reverser
Group R is made of different even number reversers, and XOR gate XOR is set there are three input port and an output port；The XOR gate
Output port of three input ports of XOR respectively with three upper reverser group R is correspondingly connected with；The output end of XOR gate XOR
Mouth is connect with the input port of each upper reverser group R；
Each time delay feedback with or oscillator by one with or door XNOR and three lower reverser group B constitute；It is each lower reversed
Device group B is made of different odd number reversers, this with or door XNOR there are three input port and an output port, with or
Output port of three input ports of door XNOR respectively with three lower reverser group B is correspondingly connected with；This is same or door XNOR defeated
Exit port is connect with the input port of each lower reverser group B.
2. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：Time delay is anti-
Presenting the reverser number on 3 in exclusive or oscillator in reverser group R is respectively：First upper reverser group R1It is anti-by 2
It is composed in series to device, second upper reverser group R2It is composed in series by 6 reversers, the upper reverser group R of third3It is anti-by 18
It is composed in series to device.
3. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：Time delay is anti-
Feedback is together or the reverser number in 3 lower reverser group B in oscillator is respectively：First lower reverser group B1It is anti-by 1
It is composed in series to device, second lower reverser group B2It is composed in series by 7 reversers, the lower reverser group B of third3It is anti-by 17
It is composed in series to device.
4. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：XOR gate
The relationship that three input ports of XOR are correspondingly connected with the output port of three upper reverser group R respectively is：First input port
With first upper reverser group R1Output port connection, the second input port with second go up reverser group R2Output port
Connection, third input port and third upper reverser group R3Output port connection.
5. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：Same or door
Three input ports of XNOR are correspondingly connected with relationship with the output port of three lower reverser group B respectively：First input port
With first lower reverser group B1Output port connection, the second input port and second lower reverser group B2Output port
Connection, third input port and third lower reverser group B3Output port connection.
6. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：All
Reverser realizes that the logic unit is by reverse lookup tables LUT using the basic programmable logic cells of FPGA1And register
Composition realizes reverser pure digi-tal logic by searching for table, saves digital state by register.
7. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：All
XOR gate XOR realizes that the logic unit is by exclusive or look-up table LUT using the basic programmable logic cells of FPGA2And deposit
Device composition realizes exclusive or pure digi-tal logic by searching for table, saves digital state by register.
8. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：All
Same or door XNOR realizes that the logic unit is by same or look-up table LUT using the basic programmable logic cells of FPGA3With post
Storage composition realizes same or pure digi-tal logic by searching for table, saves digital state by register.
9. the True Random Number Generator according to claim 1 based on time delay feedback oscillator, it is characterised in that：It is described to adopt
Sample circuit is by N+M trigger D1, D2, D3 .., DN+M and 1 XOR gate i.e. N+1 XOR gate XORN+1Composition, top n D touching
Hair device is connected with N number of XOR gate XOR in oscillating circuit respectively, rear M d type flip flop respectively with the M in oscillating circuit it is a together or
Door XNOR is connected, which is used as N+1 XOR gate XORN+1Input, N+1
A XOR gate XORN+1Output of the output as sample circuit.
10. the True Random Number Generator according to claim 9 based on time delay feedback oscillator, it is characterised in that：N+M
Trigger D1, D2, D3 .., DN+M and 1 XOR gate i.e. N+1 XOR gate XORN+1It is controlled by identical clock, the clock
It is provided by outer clock circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610665531.1A CN106293616B (en) | 2016-08-12 | 2016-08-12 | True Random Number Generator based on time delay feedback oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610665531.1A CN106293616B (en) | 2016-08-12 | 2016-08-12 | True Random Number Generator based on time delay feedback oscillator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106293616A CN106293616A (en) | 2017-01-04 |
| CN106293616B true CN106293616B (en) | 2018-11-20 |
Family
ID=57670656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610665531.1A Active CN106293616B (en) | 2016-08-12 | 2016-08-12 | True Random Number Generator based on time delay feedback oscillator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106293616B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109830888A (en) * | 2019-01-24 | 2019-05-31 | 西南大学 | One kind generating physical random number device based on silicon substrate microcavity chaos |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107943451B (en) * | 2017-11-20 | 2020-04-07 | 西安电子科技大学 | True random number generator based on autonomous Boolean network structure |
| CN108509180B (en) * | 2018-04-13 | 2021-04-06 | 太原理工大学 | Low-power-consumption random number generation device based on two-input exclusive-OR gate |
| CN108717353B (en) * | 2018-05-24 | 2021-04-06 | 太原理工大学 | True random number generation method and device with detection and correction functions |
| CN109783061B (en) * | 2019-01-16 | 2023-04-25 | 宁波大学 | True random number generator sampled by oscillator |
| CN111932430B (en) * | 2020-01-15 | 2023-05-26 | 南京信息工程大学 | Image encryption method based on FPGA |
| CN111538475B (en) * | 2020-03-25 | 2023-06-23 | 上海交通大学 | System and method for constructing true random number generator based on FPGA |
| CN113433850B (en) * | 2021-06-04 | 2022-06-03 | 电子科技大学 | Method for repairing abnormal logic of FPGA (field programmable Gate array) |
| CN116382635B (en) * | 2023-06-05 | 2023-08-08 | 灿芯半导体(成都)有限公司 | All-digital true random number entropy source system |
| CN116860206B (en) * | 2023-07-24 | 2024-03-22 | 山西工程科技职业大学 | True random number generator based on autonomous metastable state circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751240A (en) * | 2008-12-04 | 2010-06-23 | 北京中电华大电子设计有限责任公司 | True random number generator circuit for comparing thermal noises of equal resistors |
| CN101819515A (en) * | 2010-02-08 | 2010-09-01 | 清华大学 | Ring-shaped oscillator based truly random number generation circuit and truly random number generator |
| CN102130667A (en) * | 2011-01-18 | 2011-07-20 | 浙江大学 | Digital true random oscillation signal generator |
| CN102375722A (en) * | 2010-08-09 | 2012-03-14 | 中国科学技术大学 | True random number generation method and generator |
| CN103049242A (en) * | 2012-12-04 | 2013-04-17 | 清华大学 | Digital true random number generator circuit |
| CN105426159A (en) * | 2015-12-22 | 2016-03-23 | 上海爱信诺航芯电子科技有限公司 | True random number generator based on digital circuit |
-
2016
- 2016-08-12 CN CN201610665531.1A patent/CN106293616B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751240A (en) * | 2008-12-04 | 2010-06-23 | 北京中电华大电子设计有限责任公司 | True random number generator circuit for comparing thermal noises of equal resistors |
| CN101819515A (en) * | 2010-02-08 | 2010-09-01 | 清华大学 | Ring-shaped oscillator based truly random number generation circuit and truly random number generator |
| CN102375722A (en) * | 2010-08-09 | 2012-03-14 | 中国科学技术大学 | True random number generation method and generator |
| CN102130667A (en) * | 2011-01-18 | 2011-07-20 | 浙江大学 | Digital true random oscillation signal generator |
| CN103049242A (en) * | 2012-12-04 | 2013-04-17 | 清华大学 | Digital true random number generator circuit |
| CN105426159A (en) * | 2015-12-22 | 2016-03-23 | 上海爱信诺航芯电子科技有限公司 | True random number generator based on digital circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109830888A (en) * | 2019-01-24 | 2019-05-31 | 西南大学 | One kind generating physical random number device based on silicon substrate microcavity chaos |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106293616A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106293616B (en) | True Random Number Generator based on time delay feedback oscillator | |
| CN107943451B (en) | True random number generator based on autonomous Boolean network structure | |
| US8744073B2 (en) | Digital random number generator based on digitally-controlled oscillators | |
| CN104572014B (en) | The True Random Number Generator of oscillator with reconditioning | |
| JP6718096B1 (en) | Low power consumption random number generator based on 2-input XOR gate | |
| JP2009545769A (en) | Random number generation using continuous-time chaos | |
| Demir et al. | Random number generators based on irregular sampling and Fibonacci–Galois ring oscillators | |
| Gupta et al. | FPGA implementation of chaos‐based high‐speed true random number generator | |
| KR20140110142A (en) | Random number generator | |
| Kuang et al. | Pseudo quantum random number generator with quantum permutation pad | |
| CN105138307A (en) | Phase noise based integratable true random number generation method and device | |
| CN103049242B (en) | digital true random number generator circuit | |
| Addabbo et al. | Lightweight true random bit generators in PLDs: Figures of merit and performance comparison | |
| CN101882062A (en) | True random bit stream generator | |
| Tao et al. | FPGA based true random number generators using non-linear feedback ring oscillators | |
| CN205015881U (en) | True random number that can integrate produces device based on phase noise | |
| CN106201436B (en) | True Random Number Generator based on double coupling Fibonacci oscillation rings | |
| CN106383691A (en) | Random number generation method and random number generator | |
| CN107479857A (en) | Random number produces and post processing circuitry | |
| Gupta et al. | Efficient design of chaos based 4 bit true random number generator on FPGA | |
| Jothi et al. | Parallel RC4 Key Searching System Based on FPGA | |
| CN110750233B (en) | Random number generator based on logic gate asymmetric autonomous Boolean network | |
| Zhang et al. | A self-timed ring based true random number generator on FPGA | |
| WO2017146650A1 (en) | True random number generator and system comprising the same | |
| CN106293615B (en) | True Random Number Generator based on fully connected network |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |