CN105844330A - Data processing method of neural network processor and neural network processor - Google Patents
Data processing method of neural network processor and neural network processor Download PDFInfo
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Abstract
The invention provides a data processing method of a neural network processor and a neural network processor. The method includes the following steps that: input data and corresponding weight absolute values are added together through an adder, wherein the input data are data of the output of a previous stage, and the input data and the weight absolute values are n-element vectors; and n-term data obtained after adding the input data and the corresponding weight absolute values together are subjected to n times of first nonlinear mapping; results obtained after the first nonlinear mapping are subjected to n times of accumulation operation through an accumulator, wherein the accumulation operation includes weight sign bit-controlled adding operation and subtraction operation; and a result obtained after the n times of accumulation operation is subjected to second nonlinear mapping, so that a processing result can be obtained, and data output is carried out, wherein the second nonlinear mapping is formulated according to the rules of neural network nonlinear mapping and the inverse mapping of the first nonlinear mapping. With the method adopted, quantization efficiency can be improved, and storage requirements and bandwidth requirements of data can be decreased.
Description
Technical field
The present embodiments relate to electronic chip technology field, particularly relate to a kind of neural network processor
Data processing method and neural network processor.
Background technology
Neutral net and degree of depth learning algorithm have been obtained for extremely successful application, and are in and develop rapidly
During, industry generally expects that new calculation contributes to realizing the most universal, complicated intelligence and answers
With.Neutral net and degree of depth learning algorithm achieve very prominent in recent years in image recognition application
Achievement, therefore neutral net and the optimization of degree of depth learning algorithm and high efficiency are realized beginning to focus on also by industry
Paying attention to, such as facebook, it is excellent that the company such as Qualcomm, baidu, google has all put into neutral net
Change the research of algorithm.Qualcomm company has issued integrated neural network processing module in chip of future generation
Plan, improve neural network algorithm treatment effeciency, the improvement of related algorithm, and chip realize effect
Rate is that it is paid close attention to and the key problem of research.
Fig. 1 is the calculating model of neural networks schematic diagram of a n level (layer), and Processing with Neural Network is therein
The calculating shape of one neuron is such as: y=f (x1*w1+x2*w2+ ...+xn*wn+b), calculating is that classification is carried out
, the output of previous stage is the input of rear stage.Fig. 2 is traditional computational methods flow chart, and prime exports
Inputting (x1, x2 ... xn) as data, x1, x2 ... xn are multiplied with corresponding weight parameter respectively,
Then completed x1*w1+x2*w2+ by accumulator ... the accumulation operations of+xn*wn+b, then reflect through non-linear
Penetrate y=f (result after Lei Jia) and obtain result of calculation, finally complete data output.
It can be seen that in above-mentioned data processing method, the computation complexity ratio of the multiplication owing to relating to
Higher, under certain calculation accuracy requires, storage demand and the bandwidth demand of corresponding data are the highest,
Computational efficiency is the highest.
Summary of the invention
The embodiment of the present invention provides data processing method and the Processing with Neural Network of a kind of neural network processor
Device, to solve the storage demand of data present in existing processing method and bandwidth demand is higher, calculate
Inefficient problem.
First aspect, the embodiment of the present invention provides the data processing method of a kind of neural network processor, should
Method includes: first passes through adder and will input data and the addition of corresponding weight absolute value, inputs data
For the data of previous stage output, input data and weight absolute value are n unit vector.The most successively will input
N item data after data and corresponding weight absolute value are added carries out n the first nonlinear mapping.Then
By accumulator, the result after the first nonlinear mapping is carried out n accumulation operations, and accumulation operations includes power
The add operation of weight sign bit control and subtraction.Finally the result after n accumulation operations is carried out
Two nonlinear mapping obtain result and carry out data output, and the second nonlinear mapping is according to neutral net
The rule of nonlinear mapping and the inverse mapping of the first nonlinear mapping are formulated.It is achieved thereby that complicated is taken advantage of
Method calculates and is changed into additional calculation, improves quantitative efficiency, and the capacity of storage and bandwidth can be compressed, because of
This storage demand reducing data and bandwidth demand, improve computational efficiency.And input data and do not limit
Quantify in 0/1 binary so that computational accuracy meets the demand of actual application network, can be suitable for except nerve net
The application target of wider scope beyond network calculating.
In a possible design, the first nonlinear mapping is the M power conversion of 2, and M is input number
According to corresponding weight absolute value be added after n item data in every.Use 2 M power conversion by
Simple in mapping relations, realization price of hardware is low.
In a possible design, when the first nonlinear mapping is the M power conversion of m, and m is not equal to
When 2, for making circuit realiration simple, the M power of m is converted the M power conversion being converted to 2, logical
Before crossing adder general's input data and the addition of corresponding weight absolute value, also include: input data are taken advantage of
With Proportional coefficient K1, and/or, weight absolute value is multiplied by Proportional coefficient K2, K1With K2Equal or different；
Or, after data and the addition of corresponding weight absolute value being inputted by adder, also include: to phase
Every in n item data after adding is multiplied by Proportional coefficient K3.Wherein, K1、K2、K3It is not equal to 0.
In a possible design, K1、K2、K3For 1+1/2NOr 1-1/2N。
In a possible design, when input data or weight absolute value are equal to 0, accumulation operations is for working as
Front cumulative item remains unchanged.Weight sign bit is for time negative, and accumulation operations is subtraction.Accumulator is in
Maintenance state, owing to, during actual neural computing, no matter counting input data or weight,
Have substantial amounts of 0, the most so can simplify process, reduce power consumption.
In a possible design, realize the first nonlinear mapping or second non-linear by analog circuit
Map or accumulation operations.Simulation non-linear conversion, the realization of addition all instantaneous can complete, disobeys
It is disinclined to the speed of digital dock.
Second aspect, the embodiment of the present invention provides a kind of neural network processor, including: add circuit,
Being added for inputting data and corresponding weight absolute value, input data are the data of previous stage output,
Input data and weight absolute value are n unit vector.First nonlinear mapping circuit, for inputting successively
N item data after data and corresponding weight absolute value are added carries out n the first nonlinear mapping.Cumulative
Circuit, for the result after the first nonlinear mapping is carried out n accumulation operations, accumulation operations includes power
The add operation of weight sign bit control and subtraction.Second nonlinear mapping circuit, for tiring out n time
Result after add operation carries out the second nonlinear mapping and obtains result and carry out data output, and second is non-
Rule and the inverse mapping of the first nonlinear mapping that Linear Mapping maps according to Neural Network Based Nonlinear are formulated.
In a possible design, the first nonlinear mapping circuit is the M power translation circuit of 2, M
For input data and corresponding weight absolute value be added after n item data in every.
In a possible design, also include: the first mlultiplying circuit, for inputting at add circuit
Before data and corresponding weight absolute value are added, input data are multiplied by Proportional coefficient K1；And/or, the
Square law circuit, for before add circuit will input data and corresponding weight absolute value is added, right
Weight absolute value is multiplied by Proportional coefficient K2, K1With K2Equal or different；Or, the 3rd mlultiplying circuit,
For after add circuit will input data and corresponding weight absolute value is added, to the n item after being added
Every in data is multiplied by Proportional coefficient K3；Wherein, K1、K2、K3It is not equal to 0.
In a possible design, K1、K2、K3For 1+1/2NOr 1-1/2N。
In a possible design, when input data or weight absolute value are equal to 0, accumulation operations is for working as
Front cumulative item remains unchanged；Weight sign bit is for time negative, and accumulation operations is subtraction.
At neutral net provided in each possible design of above-mentioned second aspect and above-mentioned second aspect
Reason device, its beneficial effect may refer to be carried in each possible design of above-mentioned first aspect and first aspect
The beneficial effect come, does not repeats them here.
The data processing method of the neural network processor that the embodiment of the present invention provides and Processing with Neural Network
Device, will input data by adder and corresponding weight absolute value will be added, and input data are that previous stage is defeated
The data gone out, the n item data after input data and corresponding weight absolute value being added the most successively is carried out
N the first nonlinear mapping, carries out n time by the result after the first nonlinear mapping by accumulator and adds up
Operation, accumulation operations includes add operation and the subtraction that weight sign bit controls, finally tired by n time
Result after add operation carries out the second nonlinear mapping and obtains result and carry out data output, and second is non-
Rule and the inverse mapping of the first nonlinear mapping that Linear Mapping maps according to Neural Network Based Nonlinear are formulated.
It is changed into additional calculation it is achieved thereby that calculated by complicated multiplication, improves quantitative efficiency, the appearance of storage
Amount and bandwidth can be compressed, and therefore reduce storage demand and the bandwidth demand of data, improve calculating effect
Rate.And input data and be not limited to 0/1 binary quantization so that computational accuracy meets actual application network
Demand, can be suitable for the application target of wider scope in addition to neural computing.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that under,
Accompanying drawing in the description of face is some embodiments of the embodiment of the present invention, comes for those of ordinary skill in the art
Say, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the calculating model of neural networks schematic diagram of a n level (layer)；
Fig. 2 is traditional computational methods flow chart；
Fig. 3 is the flow chart of the data processing method embodiment one of neural network processor of the present invention；
Fig. 4 is the computing block diagram of the data processing method embodiment two of neural network processor of the present invention；
Fig. 5 is the computing block diagram of the data processing method embodiment three of neural network processor of the present invention；
Fig. 6 be neural network processor of the present invention data processing method embodiment three in 2 M power become
Change schematic diagram；
Fig. 7 is the structural representation of neural network processor embodiment one of the present invention；
Fig. 8 is the structural representation of neural network processor embodiment two of the present invention；
Fig. 9 is the structural representation of neural network processor embodiment three of the present invention.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the embodiment of the present invention rather than whole embodiments.
Based on the embodiment in the embodiment of the present invention, those of ordinary skill in the art are not making creative work
The every other embodiment obtained under premise, broadly falls into the scope of embodiment of the present invention protection.
The embodiment of the present invention provides data processing method and the Processing with Neural Network of a kind of neural network processor
Device, can be applicable to the such as data such as view data, speech data, video data needs to carry out neutral net
The scene calculated, the data received carry out neural computing (single-stage neutral net as input data
Calculate or Multilevel ANN calculate), the following data processing method provided by the embodiment of the present invention,
Complicated multiplication calculates and is changed into additional calculation, improves quantitative efficiency, and capacity and the bandwidth of storage are permissible
Compression, therefore reduces storage demand and the bandwidth demand of data, improves computational efficiency.
The neural network processor that the embodiment of the present invention provides may have physical entity form.Such as, at cloud
End server application scenario, can be independent process chip, in terminal (such as mobile phone) application, and Ke Yishi
A module in terminal handler chip.The input of information needs from voice, image, natural language etc.
The various information wanting Intelligent treatment input, and through necessary pretreatment, (such as sampling, analog digital conversion, feature carries
Take) form the data of pending neural network computing.The output of information deliver to other subsequent treatment modules or
Software, such as figure or other be appreciated that available manifestation mode.Wherein, beyond the clouds under application form,
Before and after neural network processor, the processing unit of level such as can be undertaken by other server operation unit,
Under terminal applies environment, before and after neural network processor, level processing unit can be by its of terminal software and hardware
He completes part (such as including sensor, interface circuit etc.).
Fig. 3 is the flow chart of the data processing method embodiment one of neural network processor of the present invention, such as figure
Shown in 1, the method for the present embodiment may include that
S101, input data and corresponding weight absolute value being added by adder, input data are front
The data of one-level output, input data and weight absolute value are n unit vector.
For Multilevel ANN, the output of previous stage is as the input of rear stage.Weight therein includes
Weight absolute value and weight sign bit.
S102, successively will input data and corresponding weight absolute value be added after n item data carry out n time
First nonlinear mapping.
Wherein, the first nonlinear mapping can be any truth of a matter m M power conversion, it is also possible to be shape such as
Y=A*mB, the nonlinear transformation of y=B*B.Preferably, the first nonlinear mapping is the M power change of 2
Change, M be input data and corresponding weight absolute value be added after data in every.Use the M of 2
Power conversion is simple due to mapping relations, and realization price of hardware is low.
S103, the result after the first nonlinear mapping is carried out n accumulation operations by accumulator.
Accumulation operations includes add operation and the subtraction that weight sign bit controls, i.e. that is, weight
Sign bit is negative, then accumulator does subtraction, and weight sign bit is that just accumulator does additive operation.
S104, the result after n accumulation operations is carried out the second nonlinear mapping obtain result and go forward side by side
Row data export, rule that the second nonlinear mapping maps according to Neural Network Based Nonlinear and first non-linear
The inverse mapping mapped is formulated.
Wherein, when the first nonlinear mapping is the M power conversion of m, when m is not equal to 2, for making circuit
Realize simple, the M power of m is converted the M power conversion being converted to 2, especially by: in S101
Before inputting data and the addition of corresponding weight absolute value by adder, also include:
Input data are multiplied by Proportional coefficient K1, and/or, weight absolute value is multiplied by Proportional coefficient K2,
K1With K2Equal or different；Or, will input data and the addition of corresponding weight absolute value by adder
Afterwards, also include: to the n item data after being added every is multiplied by Proportional coefficient K3.Wherein, K1、
K2、K3It is not equal to 0, alternatively, K1、K2、K3Can be 1+1/2NOr 1-1/2N。
By aforesaid operations, can be by M time that M power shift conversion is 2 of m when circuit realiration
Power conversion realizes, because the mapping relations of the M power conversion of 2 are simple, realization price of hardware is low.
Further, there is the situation equal to 0 in input data or weight absolute value, and weight there is also as negative
The situation of number, therefore, when input data or weight absolute value are equal to 0, accumulation operations is current cumulative item
Remain unchanged.Accumulator is in maintenance state, due to during actual neural computing, no matter
Number input data or weight, exist substantial amounts of 0, the most so can simplify process, reduces power consumption.
Weight sign bit is for time negative, and accumulation operations is subtraction, i.e. accumulator does subtraction.Do and subtract
Method is exactly to negate original number to add 1.
It is alternatively possible to realize the first nonlinear mapping or the second nonlinear mapping or tired by analog circuit
Add operation.Simulation non-linear conversion, the realization of addition all can instantaneous complete, and disobeys and is disinclined to numeral
The speed of clock.
It should be noted that adder mentioned above, accumulator and hereafter carry in the embodiment of the present invention
To multiplier be discrete, the circuit of physics, not by universal cpu realize software module.
The data processing method of the neural network processor that the present embodiment provides, will input number by adder
Being added according to corresponding weight absolute value, input data are the data of previous stage output, the most successively by defeated
Enter the n item data after data and the addition of corresponding weight absolute value and carry out n the first nonlinear mapping, will
Result after first nonlinear mapping carries out n accumulation operations by accumulator, and accumulation operations includes weight
The add operation of sign bit control and subtraction, finally carry out second by the result after n accumulation operations
Nonlinear mapping obtains result and carries out data output, and the second nonlinear mapping is non-according to neutral net
The rule of Linear Mapping and the inverse mapping of the first nonlinear mapping are formulated.It is achieved thereby that by complicated multiplication
Calculating is changed into additional calculation, improves quantitative efficiency, and the capacity of storage and bandwidth can be compressed, therefore
Reduce storage demand and the bandwidth demand of data, improve computational efficiency.And input data and be not limited to
0/1 binary quantifies so that computational accuracy meets the demand of actual application network, can be suitable for except neutral net meter
The application target of wider scope beyond calculation.
Describe the embodiment of the present invention in detail provide below in conjunction with formulation process and a specific embodiment
The processing procedure of data processing method of neural network processor.
Specifically, complicated multiplication is calculated and is changed into additional calculation, in detail by the M power conversion using m
Formula proving process as follows:
As a example by background technology to be mentioned the calculating of shape such as y=f (x1*w1+x2*w2+ ...+xn*wn+b),
First assume that x > 0, s (w) are the sign bit of W.
Y=f (s (w1) eln(x1)+ln(|w1|)+s(w2)eln(x2)+ln(|w2|)+…s(wn)eln(xn)+ln(|wn|)+b)
Ln (y)=ln (f (s (w1) eln(x1)+ln(|w1|)+s(w2)eln(x2)+ln(|w2|)+…s(wn)eln(xn)+ln(|wn|)+b))
Assuming u=ln (y), v=ln (x), c=ln (| w |), this formula is expressed as again:
U=ln (f (s (w1) ev1+c1+s(w2)ev2+c2+…s(wn)evn+cn+b))
If exponential relationship is the index of 2, logarithmic relationship is the logarithm with 2 as the end, and computing formula is written as:
Y=f (s (w1) 2log 2 (x1)+log 2 (|w1|)+s(w2)2log 2 (x2)+log 2 (|w2|)+…+s(wn)2log 2 (xn)+log 2 (|wn|)…+b)
log2Y=log2f(s(w1)2log 2 (x1)+log 2 (|w1|)+s(w2)2log 2 (x2)+log 2 (|w2|)+…+s(wn)2log 2 (xn)+log 2 (|wn| )…+b)
Assume u=log2Y, v=log2X, c=log2| w |, this formula is expressed as again:
U=log2f(s(w1)2v1+c1+s(w2)2v2+c2+…s(wn)2vn+cn+b)
Make g (x)=2(x), ff (x)=log2F (x), then computing formula is abbreviated as:
U=ff (s (w1) g (v1+c1)+s (w2) g (v2+c2)+... s (wn) g (vn+cn)+b)
Wherein, corresponding first nonlinear mapping of g (x), corresponding second nonlinear mapping of ff (x).Fig. 4 is this
The computing block diagram of the data processing method embodiment two of bright neural network processor, as shown in Figure 4, prime is defeated
Going out as input data, input data and corresponding weight absolute value are n unit vector, first pass through adder
Input data and corresponding weight absolute value are added, n item data v1+c1 after being added, v2+c2,,
Vn+cn, n item data v1+c1 after will add up successively, v2+c2,, vn+cn carry out n the first non-thread
Property map (g (x)=2(x)), obtain the result 2 after the first nonlinear mappingv1+c1、2v2+c2、、、2vn+cn,
Then carry out n accumulation operations and obtain 2v1+c1+2v2+c2+…2vn+cn+ b, if input data or weight are 0,
The item that the most currently adds up remains unchanged.If weight sign bit is negative, then accumulator does subtraction.Finally
Result after n accumulation operations carries out the second nonlinear mapping (ff (x)) obtain result and go forward side by side line number
According to output.
If exponential relationship is the index with m as the end, logarithmic relationship is the logarithm with m as the end, computing formula
It is written as:
Y=f (s (w1) mlog m (x1)+log m (|w1|)+s(w2)mlog m (x2)+log m (|w2|)+…+s(wn)mlog m (xn)+log m (|wn|)
…+b)
logmY=logmf(s(w1)mlog m (x1)+log m (|w1|)+s(w2)mlog m (x2)+log m (|w2|)+…+s(wn)mlog m (xn)+l og m (|wn|)…+b)
Assume u=logmY, v=logmX, c=logm| w |, this formula is expressed as again:
U=logmf(s(w1)mv1+c1+s(w2)mv2+c2+…+s(wn)mvn+cn+b)
U=logmf(s(w1)2(v1+c1)*log 2 m+s(w2)2(v2+c2)*log 2 m+…+s(wn)2(vn+cn)*log 2 m+b)
Make g (x)=2(x), ff (x)=logmF (x), k=log2M, then computing formula is abbreviated as:
U=ff (s (w1) g (c1*k+v1*k)+s (w2) g (c2*k+v2*k)+... s (wn) g (cn*k+vn*k)+b)
Wherein corresponding first nonlinear mapping of g (x), corresponding second nonlinear mapping of ff (x).As it is shown in figure 5,
Fig. 5 is the computing block diagram of the data processing method embodiment three of neural network processor of the present invention.Above-mentioned calculating
K in formula is the proportionality coefficient taken advantage of, by inputting data and corresponding weight absolute value in adder
It is multiplied by proportionality coefficient k before or after addition, the M power of m can be converted the M power conversion being converted to 2,
Make mapping relations simple, also simple on circuit realiration, and then realization price of hardware is low.In conjunction with Fig. 5, this
The method implemented includes:
S201, from the data (i.e. prime output) of n-1 DBMS output unit output as the input of n level
Data.
Input data and the corresponding weight absolute value of this grade are done phase add operation by the adder of S202, n level.
S203, on the passage that input data and weight absolute value are added, or in input data and corresponding
Weight absolute value be added after result on, be multiplied by proportionality coefficient k, conventional proportionality coefficient k such as type is such as
1+1/2N, 1-1/2NProportionality coefficient.
S204, successively will input data and corresponding weight absolute value be added after n item data carry out n order
One nonlinear mapping.
Wherein, the first nonlinear mapping e.g. can simplify design 2 M power conversion.Fig. 6 is this
The M power conversion schematic diagram of 2 in the data processing method embodiment three of invention neural network processor, such as figure
Shown in 6, specifically include:
In data after S2041, addition, the floating-point part of data, through decoder circuit, be converted to anti-
Reflect the binary number of floating-point power actual size.
S2042, the fractional part of data, through the combinational circuit tabled look-up or simplify, complete the index of data
Transformed mappings.
Data after S2043, exponential transform, and the power of floating-point, combined the simplest by combinational circuit
Single 1, to n position multiplication, forms last result.
S205, accumulator carry out n accumulation operations to the cumulative item of output after the first nonlinear mapping.If
Input data or weight are 0, and the item that the most currently adds up remains unchanged.If weight sign bit is negative, then add up
Device does subtraction.
S206, the result after n accumulation operations is carried out the second nonlinear mapping.Usually, this is second non-
Rule and the inverse mapping of the first nonlinear mapping that Linear Mapping maps according to Neural Network Based Nonlinear are formulated.
One special case of this conversion is to include the cascades of 2 kinds of conversion, and it 1 is the non-linear change that neutral net is original
Change, such as Sigmoid, ReLU etc., its 2 be adjust the data regularity of distribution logarithmic transformation.
S207, result is carried out data output.
Such as, a corresponding shape is such as: the calculating of y=f (x1*w1+x2*w2+ ...+xn*wn+b), x, w,
The initial data precision of y needs the floating-point (32bit) of single precision, is at least also required to the fixed-point number of 16bit, right
The data bandwidth answered is by the proportional calculating of 16bit, simultaneously need to the multiplier of 16bit.
First can be to x, w, y carry out logarithmic transformation, A=logmB.Experiment shows, the number after conversion
According to, the quantization of 8 bits can meet the requirement of practicality, even can also accomplish 6 bits, 4 bits further.
Data after conversion are designated as P.Q, the part before wherein P is arithmetic point, and Q is arithmetic point portion below
Point, P has p position, and Q has q position, and p+q is total bit number of data.
The present embodiment represents correspondence with Pv.Qv, the x after conversion, w, y data.
Therefore, the additional calculation after logarithmic transformation is just changed into:
There is no the situation of carry: Px.Qx+Pw.Qw=(Px+Pw). (Qx+Qw) or
There is the situation of carry: Px.Qx+Pw.Qw=(Px+Pw+1). (Qx+Qw-1)
It is denoted as: Pt.Qt
Pt.Qt does a simple multiplication, and the coefficient taken advantage of is: Log2M, by this multiplication, permissible
The m that follow-up needs are donePt.Qt, be converted to 2Ps.QsDo.And Ps.Qs=Pt.Qt*Log2m。
As a rule, the logarithm or the index that take 2 can meet application requirement.In particular cases, if
The logarithmic relationship suitably adjusted can preferably meet the requirement of application, can fit by taking advantage of this coefficient
Work as regulation.By a sub-addition, satisfiable adjusting range be type such as: 1+1/2N, 1-1/2NAny
Coefficient.Assuming that Pt is 4bit, Qt is 4bit, follow-up calculating, and Pt is directly sent to 4 lines and turns the decoder of 16 lines,
And Qt directly send the look-up table of 4bit a to 4bit, or the simple combination electricity of reflection index mapping data rule
Road.
Fig. 7 is the structural representation of neural network processor embodiment one of the present invention, as it is shown in fig. 7, this
The neural network processor of embodiment may include that add circuit the 11, first nonlinear mapping circuit 12,
Summation circuit 13 and the second nonlinear mapping circuit 14.Wherein, add circuit 11 will be for inputting data
Being added with corresponding weight absolute value, input data are the data of previous stage output, input data and weight
Absolute value is n unit vector.First nonlinear mapping circuit 12 will be for inputting data and corresponding power successively
N item data after weight absolute value is added carries out n the first nonlinear mapping.Summation circuit 13 is for by the
Result after one nonlinear mapping carries out n accumulation operations, and accumulation operations includes what weight sign bit controlled
Add operation and subtraction.Second nonlinear mapping circuit 14 is for by the result after n accumulation operations
Carrying out the second nonlinear mapping obtain result and carry out data output, the second nonlinear mapping is according to god
Formulate through the rule of network nonlinear mapping and the inverse mapping of the first nonlinear mapping.
Wherein, the first nonlinear mapping circuit 12 can be the M power translation circuit of any truth of a matter m,
Can also is that shape such as y=A*mB, the non-linear transform circuit of y=B*B.Preferably, first non-linear reflects
Radio road 12 is the M power translation circuit of 2, and M is added for input data and corresponding weight absolute value
After n item data in every.
Further, when the first nonlinear mapping circuit 12 is the M power translation circuit of m, m
In 2 time, for making circuit realiration simple, the M power of m is converted the M power conversion being converted to 2,
Specifically, Fig. 8 is the structural representation of neural network processor embodiment two of the present invention, as shown in Figure 8,
On the basis of neural network processor shown in Fig. 7, further, also include: the first mlultiplying circuit 15,
For, before add circuit 11 will input data and corresponding weight absolute value is added, input data being taken advantage of
With Proportional coefficient K1；And/or, the second mlultiplying circuit 16, for add circuit 11 will input data and
Before corresponding weight absolute value is added, weight absolute value is multiplied by Proportional coefficient K2, K1With K2Equal
Or.
Fig. 9 is the structural representation of neural network processor embodiment three of the present invention, as it is shown in figure 9,
On the basis of neural network processor shown in Fig. 7, further, also include: the 3rd mlultiplying circuit 17,
For after add circuit 11 will input data and corresponding weight absolute value is added, to the n after being added
Every in item data is multiplied by Proportional coefficient K3。
Wherein, K1、K2、K3It is not equal to 0.Optionally, K1、K2、K3Can be 1+1/2NOr 1-1/2N。
Further, when input data or weight absolute value are equal to 0, accumulation operations is current cumulative Xiang Wei
Hold constant；Weight sign bit is for time negative, and accumulation operations is subtraction.Accumulator is in maintenance state,
Owing to, during actual neural computing, no matter counting input data or weight, existing substantial amounts of
0, the most so can simplify process, reduce power consumption.
The device of the present embodiment, may be used for performing the technical scheme of embodiment of the method shown in Fig. 3, in fact
Existing principle is similar to, and here is omitted.
The neural network processor that the present embodiment provides, will input data and corresponding power by add circuit
Weight absolute value is added, and input data are the data of previous stage output, and then the first nonlinear mapping circuit depends on
Secondary will input data and corresponding weight absolute value be added after n item data carry out n time first and non-linear reflect
Penetrating, the result after the first nonlinear mapping is carried out n accumulation operations by accumulator by summation circuit, tired
Add operation includes add operation and the subtraction that weight sign bit controls, the second last nonlinear mapping electricity
Result after n accumulation operations is carried out the second nonlinear mapping and obtains result and to carry out data defeated by road
Go out, rule that the second nonlinear mapping maps according to Neural Network Based Nonlinear and the first nonlinear mapping inverse
Map and formulate.It is changed into additional calculation it is achieved thereby that calculated by complicated multiplication, improves quantitative efficiency,
Capacity and the bandwidth of storage can be compressed, and therefore reduce storage demand and the bandwidth demand of data, improve
Computational efficiency.And input data and be not limited to 0/1 binary quantization so that computational accuracy meets reality should
By the demand of network, the application target of wider scope in addition to neural computing can be suitable for.
One of ordinary skill in the art will appreciate that: realize all or part of step of above-mentioned each method embodiment
Suddenly can be completed by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer can
Read in storage medium.This program upon execution, performs to include the step of above-mentioned each method embodiment；And
Aforesaid storage medium includes: ROM, RAM, magnetic disc or CD etc. are various can store program code
Medium.
It is last it is noted that various embodiments above is only in order to illustrate the technical scheme of the embodiment of the present invention,
It is not intended to limit；Although the embodiment of the present invention being described in detail with reference to foregoing embodiments,
It will be understood by those within the art that: it still can be to the technology described in foregoing embodiments
Scheme is modified, or the most some or all of technical characteristic is carried out equivalent；And these are repaiied
Change or replace, not making the essence of appropriate technical solution depart from the embodiment of the present invention each embodiment technical side
The scope of case.
Claims (11)
1. the data processing method of a neural network processor, it is characterised in that including:
To input data by adder and corresponding weight absolute value is added, described input data are previous
The data of level output, described input data and described weight absolute value are n unit vector；
N item data after described input data and corresponding weight absolute value being added successively carries out n order
One nonlinear mapping；
Result after first nonlinear mapping is carried out n accumulation operations, described cumulative behaviour by accumulator
Make to include add operation and the subtraction that weight sign bit controls；
Result after n accumulation operations is carried out the second nonlinear mapping obtain result and carry out data
Output, rule that described second nonlinear mapping maps according to Neural Network Based Nonlinear and described first non-thread
Property map inverse mapping formulate.
Method the most according to claim 1, it is characterised in that described first nonlinear mapping is 2
The conversion of M power, M is in the n item data after described input data and corresponding weight absolute value are added
Every.
Method the most according to claim 1 and 2, it is characterised in that described by adder by defeated
Before entering data and the addition of corresponding weight absolute value, also include:
Described input data are multiplied by Proportional coefficient K1, and/or, described weight absolute value is multiplied by ratio system
Number K2, K1With K2Equal or different；Or,
Described by adder will input data and corresponding weight absolute value be added after, also include:
To the n item data after being added every is multiplied by Proportional coefficient K3；
Wherein, K1、K2、K3It is not equal to 0.
Method the most according to claim 3, it is characterised in that K1、K2、K3For 1+1/2NOr
1-1/2N。
5. according to the method described in any one of claim 1-4, it is characterised in that
When described input data or described weight absolute value are equal to 0, described accumulation operations is current cumulative item
Remain unchanged；
Described weight sign bit is for time negative, and described accumulation operations is subtraction.
6. according to the method described in any one of claim 1-5, it is characterised in that real by analog circuit
Show described first nonlinear mapping or described second nonlinear mapping or described accumulation operations.
7. a neural network processor, it is characterised in that including:
Add circuit, is added for inputting data and corresponding weight absolute value, and described input data are
The data of previous stage output, described input data and described weight absolute value are n unit vector；
First nonlinear mapping circuit, for successively by described input data and corresponding weight absolute value phase
N item data after adding carries out n the first nonlinear mapping；
Summation circuit, for the result after the first nonlinear mapping being carried out n accumulation operations, described tired
Add operation includes add operation and the subtraction that weight sign bit controls.
Second nonlinear mapping circuit, non-linear reflects for the result after n accumulation operations carries out second
Penetrating and obtain result and carry out data output, described second nonlinear mapping is according to Neural Network Based Nonlinear
The rule mapped and the inverse mapping of described first nonlinear mapping are formulated.
Neural network processor the most according to claim 7, it is characterised in that described first non-thread
Property mapping circuit is the M power translation circuit of 2, and M is described input data and corresponding weight absolute value
Every in n item data after addition.
Neural network processor the most according to claim 7, it is characterised in that also include:
First mlultiplying circuit, for inputting data and corresponding weight absolute value phase at described add circuit
Before adding, described input data are multiplied by Proportional coefficient K1；And/or,
Second mlultiplying circuit, for inputting data and corresponding weight absolute value phase at described add circuit
Before adding, described weight absolute value is multiplied by Proportional coefficient K2, K1With K2Equal or different；
Or,
3rd mlultiplying circuit, for inputting data and corresponding weight absolute value phase at described add circuit
After adding, to the n item data after being added every is multiplied by Proportional coefficient K3；
Wherein, K1、K2、K3It is not equal to 0.
Neural network processor the most according to claim 9, it is characterised in that K1、K2、K3
For 1+1/2NOr 1-1/2N。
11. according to the neural network processor described in any one of claim 7-10, it is characterised in that institute
When stating input data or described weight absolute value equal to 0, described accumulation operations is that current cumulative item maintains not
Become；
Described weight sign bit is for time negative, and described accumulation operations is subtraction.
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