CN105843749B - A kind of NAND Flash fault-tolerance approach based on FPGA - Google Patents
A kind of NAND Flash fault-tolerance approach based on FPGA Download PDFInfo
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- CN105843749B CN105843749B CN201610173425.1A CN201610173425A CN105843749B CN 105843749 B CN105843749 B CN 105843749B CN 201610173425 A CN201610173425 A CN 201610173425A CN 105843749 B CN105843749 B CN 105843749B
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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Abstract
The NAND Flash fault-tolerance approach based on FPGA that the invention discloses a kind of, including the detection of Flash bad block, bad block management and On-line Timing Plan Selection.The state of flag bit is write by Flash and whether read-write content is identical detects bad block.Good, the defect block addresses that detect are managed, and establish address mapping table using bad block management algorithm.FPGA carries out Flash by way of On-line Timing Plan Selection to write, read and erase operation, substantially increases the Accuracy and high efficiency of data access.This method can directly improve Flash space utilization rate, its overall performance and processing speed is made to obtain important guarantee, have reference significance to the application development of large capacity NAND Flash of new generation.
Description
Technical field
The present invention relates to Flash fault-toleranr technique more particularly to a kind of NAND Flash fault-tolerance approaches based on FPGA.
Background technique
It with information technology continues to develop, digital product has become the vital a part of life.People not
During disconnected pursuit high-quality life, the capacity and process performance of the digital products such as smart phone, digital camera, player are urgently
It needs to be promoted.At the same time, storage industry is faced with by great demand bring opportunity to develop.Civilian consumer electronics market now
In, flash memory (Flash) plays dominant role in non-volatile memory medium.NOR can be divided by the difference on logical architecture
Two kinds of Flash and NAND Flash.NOR Flash occupies main status in early stage market, after technological innovation, NAND Flash
The cost for emphasizing to reduce every bit, can pass through interface as disk and easily upgrade, and have speed high, and high reliablity is low in energy consumption,
The advantages that small in size, fever is less, antidetonation is strong, gradually replaces NOR Flash, has become the mainstream of memory.
Since the technique of NAND Flash cannot be guaranteed the Memory Array of the NAND retention property in its life cycle
It is reliable, therefore appear on the scene and use process in can generate and be unable to the invalid block of erasure error, i.e. bad block.It is existing bad when appearance
Block cannot be used for storing data, be identified by producer, and certain positions of bad block caused by the day after tomorrow increases due to access times are not
It can be flipped, system is made to become unstable, cause data in Flash not read and write normally, or even cause
The problems such as Flash scraps.Therefore, bad block management is always the key problem in technology and difficult point in NAND Flash management.By to bad
The testing and management of block not only can find at the first time bad block, but also can according to need and skip or replace bad block, and handle
The bad block of replacement is stored in reserved area, can be ensured data safety, be avoided the unnecessary trouble such as loss of data.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to provide a kind of fault-tolerant side of NAND Flash based on FPGA
Method.
The purpose of the present invention is what is be achieved through the following technical solutions: a kind of fault-tolerant side of NAND Flash based on FPGA
Method, including the detection of Flash bad block, bad block management and On-line Timing Plan Selection.The state of flag bit is write by Flash and whether reads and writes content
It is identical to detect bad block.Good, the defect block addresses that detect are managed, and establish address of cache using bad block management algorithm
Table.FPGA carries out Flash by way of On-line Timing Plan Selection to write, read and erase operation, substantially increases data access
Accuracy and high efficiency.
Further, the bad block detection process of the Flash is as follows:
(1) write operation is carried out by page address to all pieces of Flash chip by FPGA, once writes one page.One write cycle time
After, by checking write state flag bit to determine whether being write as function, if continuous 3 times are not write as function, judge that current block is
Bad block；
(2) if being written successfully, data will be write and stored to RAM.It reads in current block content and RAM and writes data progress
Comparison, it is not identical to read and write content for continuous 2 times, then judges current block for bad block；
(2) if being written successfully, the data of writing read in current block content and RAM are compared, and are read and are write for continuous 2 times
It is not identical to enter content, then judges current block for bad block；
Further, the bad block management process is as follows:
(1) erasing operation is carried out to first good block that every piece of Flash is detected, all byte contents are after erasing
0XFF.Then it is marked in all byte write-in 0X0A of its first page, shows that the block for storage address mapping table, is denoted as
Block1, block address are denoted as address1；
(2) register for defining one 16, is denoted as block_addr, for storing the state of detection block.Block1's
Second page starts, and the storage address mapping table by the way of one block of each bit label, good block is denoted as 1, and bad block is denoted as 0；
(3) from the BOB(beginning of block) detection after Block1, if preferably block,
Block_addr [0]=1,
Conversely,
Block_addr [0]=0.
Meanwhile block_addr moves to left one, and definition register bit_counter, record moves to left digit；
(4) during by checking that write state flag bit detects bad block, if current page meets write-in fail condition, judge
Current block is bad block, and skips the detection of continued page, directly starts next piece of detection；
(5) as bit_counter=31, block_addr is written to first word of the second page of Block1,
And Block1 column address adds 1, bit_counter to reset.Meanwhile definition register block_counter, record reset secondary
Number；
(6) a total of N number of piece of Flash is set, maximum block address is denoted as addr_max, if meeting
Block_counter >=(addr_max-address1)/16,
Then illustrate that detection is completed, address mapping table has been stored in Block1.
Further, for the Flash after establishing address mapping table, On-line Timing Plan Selection process is as follows:
(1) it reads: executing read operation from first BOB(beginning of block) of Flash, if the first page for reading block is all 0X0A,
Judge current block for address mapping table memory block.The address mapping table of second page is read, and is stored to RAM, meanwhile, after block address
Move to next piece.Address mapping table is judged by turn, if 1, is read current block content if 0 and is then skipped current block.Each position
After judgement and block operation, address moves back a unit, until executing to block address addr_max；
(2) it wipes: executing read operation from first BOB(beginning of block) of Flash, if the first page for reading block is all 0X0A,
Then judge current block for address mapping table memory block.Erasing operation is executed from next BOB(beginning of block), until executing to block address addr_
max；
(3) dynamic updates: when executing write operation after erasing again, executing reading from first BOB(beginning of block) of Flash first
Operation, if the first page for reading block is all 0X0A, judges current block for address mapping table memory block.Read the ground of second page
Location mapping table, and store to RAM, meanwhile, block address is moved back to next piece.Address mapping table is judged by turn, if 0, is skipped and is worked as
Preceding piece, if 1, data is written in current block, is performed simultaneously detection operation, if current block is detected as bad block, updates address and reflect
Current record position is updated to 0, and skips current block by firing table.After each position judgement and block operation, address moves back one
Unit, until executing to block address addr_max.
The invention has the advantages that: the NAND Flash fault-tolerance approach based on FPGA can efficiently solve bad
Block testing and management problem prolongs its service life to improve Flash storage performance, ensures the data safety of user.The party
Method includes the detection of Flash bad block, bad block management and On-line Timing Plan Selection.The state of flag bit is write by Flash and whether reads and writes content
It is identical to detect bad block.Good, the defect block addresses that detect are managed, and establish address of cache using bad block management algorithm
Table.FPGA carries out Flash by way of On-line Timing Plan Selection to write, read and erase operation, mentions in view of the deficiencies of the prior art
Go out practicable processing method, substantially increases the Accuracy and high efficiency of data access.In short, passing through NAND Flash
Fault-tolerance approach can carry out dynamic management to the bad block encountered in use process, dynamically update bad block information table, and directly raising block is empty
Between utilization efficiency, so that Flash overall performance and processing speed is obtained important guarantee, to large capacity NAND Flash's of new generation
Application development has reference significance.
Detailed description of the invention
Fig. 1 is the bad block overhaul flow chart of Flash；
Fig. 2 is Flash bad block management flow chart；
Fig. 3 is that address mapping table dynamic updates flow chart.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.
As shown in Figure 1, the bad block detection process of Flash is as follows:
(1) write operation is carried out by page address to all pieces of Flash chip by FPGA, once writes one page.One write cycle time
After, by checking write state flag bit to determine whether being write as function, if continuous 3 times are not write as function, judge that current block is
Bad block；
(2) if being written successfully, data will be write and stored to RAM.It reads in current block content and RAM and writes data progress
Comparison, it is not identical to read and write content for continuous 2 times, then judges current block for bad block；
As shown in Fig. 2, bad block management process is as follows:
(1) erasing operation is carried out to first good block that every piece of Flash is detected, all byte contents are after erasing
0XFF.Then it is marked in all byte write-in 0X0A of its first page, shows that the block for storage address mapping table, is denoted as
Block1, block address are denoted as address1；
(2) register for defining one 16, is denoted as block_addr, for storing the state of detection block.Block1's
Second page starts, and the storage address mapping table by the way of one block of each bit label, good block is denoted as 1, and bad block is denoted as 0；
(3) from the BOB(beginning of block) detection after Block1, if preferably block,
Block_addr [0]=1,
Conversely,
Block_addr [0]=0.
Meanwhile block_addr moves to left one, and definition register bit_counter, record moves to left digit；
(4) during by checking that write state flag bit detects bad block, if current page meets write-in fail condition, judge
Current block is bad block, and skips the detection of continued page, directly starts next piece of detection；
(5) as bit_counter=31, block_addr is written to first word of the second page of Block1,
And Block1 column address adds 1, bit_counter to reset.Meanwhile definition register block_counter, record reset secondary
Number；
(6) a total of N number of piece of Flash is set, maximum block address is denoted as addr_max, if meeting
Block_counter >=(addr_max-address1)/16,
Then illustrate that detection is completed, address mapping table has been stored in Block1.
As shown in figure 3, Flash, after establishing address mapping table, On-line Timing Plan Selection process is as follows:
(1) it reads: executing read operation from first BOB(beginning of block) of Flash, if the first page for reading block is all 0X0A,
Judge current block for address mapping table memory block.The address mapping table of second page is read, and is stored to RAM, meanwhile, after block address
Move to next piece.Address mapping table is judged by turn, if 1, is read current block content if 0 and is then skipped current block.Each position
After judgement and block operation, address moves back a unit, until executing to block address addr_max；
(2) it wipes: executing read operation from first BOB(beginning of block) of Flash, if the first page for reading block is all 0X0A,
Judge current block for address mapping table memory block.Erasing operation is executed from next BOB(beginning of block), until executing to block address addr_
max；
(3) dynamic updates: when executing write operation after erasing again, executing reading from first BOB(beginning of block) of Flash first
Operation, if the first page for reading block is all 0X0A, judges current block for address mapping table memory block.Read the ground of second page
Location mapping table, and store to RAM, meanwhile, block address is moved back to next piece.Address mapping table is judged by turn, if 0, is skipped and is worked as
Preceding piece, if 1, data is written in current block, is performed simultaneously detection operation, if current block is detected as bad block, updates address and reflect
Current record position is updated to 0, and skips current block by firing table.After each position judgement and block operation, address moves back one
Unit, until executing to block address addr_max.
Claims (3)
1. a kind of NAND Flash fault-tolerance approach based on FPGA, which is characterized in that including the detection of Flash bad block, bad block management
And On-line Timing Plan Selection；The state of flag bit is write by Flash and whether read-write content is identical detects bad block；It is calculated using bad block management
Method is managed to good, the defect block addresses that detect, and establishes address mapping table；FPGA is by way of On-line Timing Plan Selection pair
Flash carries out writing, reading and erasing operation；
The bad block detection process of Flash is as follows:
(1) write operation is carried out by page address to all pieces of Flash chip by FPGA, once writes one page；One write cycle time terminates
Afterwards, by checking that Flash writes the state of flag bit to determine whether being write as function, if continuous 3 times are not write as function, judge current block
For bad block；
(2) if being written successfully, data will be write and stored to RAM；The data of writing read in current block content and RAM carry out pair
Than it is not identical to read and write content for continuous 2 times, then judges current block for bad block.
2. a kind of NAND Flash fault-tolerance approach based on FPGA according to claim 1, which is characterized in that the bad block
Management process is as follows:
(1) erasing operation is carried out to first good block that Flash is detected, all byte contents are 0XFF after erasing；Then
It is marked in this first good all byte write-in 0X0A of block first page, shows that this first good block is mapped for storage address
Table is denoted as Block1, this first good block block address is denoted as address1；
(2) register for defining one 16, is denoted as block_addr, for storing the state of detection block；From the of Block1
Page two start, and the storage address mapping table by the way of one block of each bit label, good block is denoted as 1, and bad block is denoted as 0；
(3) from the BOB(beginning of block) detection after Block1, if preferably block,
Block_addr [0]=1,
Conversely,
block_addr[0]=0；
Meanwhile block_addr moves to left one, and definition register bit_counter, record moves to left digit；
(4) during by checking that write state flag bit detects bad block, if current page meets write-in fail condition, judgement is worked as
Preceding piece is bad block, and skips the detection of continued page, directly starts next piece of detection；
(5) as bit_counter=31, the content in block_addr is written to the first word of the second page of Block1
In, and Block1 column address adds 1, bit_counter to reset；Meanwhile definition register block_counter, record are reset
Number；
(6) a total of N number of piece of Flash is set, maximum block address is denoted as addr_max, if meeting
Block_counter >=(addr_max-address1)/16,
Then illustrate that detection is completed, address mapping table has been stored in Block1.
3. a kind of NAND Flash fault-tolerance approach based on FPGA according to claim 1, which is characterized in that described
For Flash after establishing address mapping table, On-line Timing Plan Selection process is as follows:
(1) it reads: executing read operation from first BOB(beginning of block) of Flash and sentence if the first page for reading block is all 0X0A
Disconnected current block is address mapping table memory block；The address mapping table of second page is read, and is stored to RAM, meanwhile, block address moves back
To next piece；Address mapping table is judged by turn, if 1, is read current block content if 0 and is then skipped current block；Sentence each position
After the operation of disconnected and block, address moves back a unit, until executing to block address addr_max；
(2) it wipes: executing read operation from first BOB(beginning of block) of Flash and sentence if the first page for reading block is all 0X0A
Disconnected current block is address mapping table memory block；Erasing operation is executed from next BOB(beginning of block), until executing to block address addr_max；
(3) dynamic updates: when executing write operation after erasing again, executing from first BOB(beginning of block) of Flash read behaviour first
Make, if the first page for reading block is all 0X0A, judges current block for address mapping table memory block；Read the address of second page
Mapping table, and store to RAM, meanwhile, block address is moved back to next piece；Address mapping table is judged by turn, if 0, is skipped current
Block is written data in current block, is performed simultaneously detection operation, if current block is detected as bad block, updates address of cache if 1
Current record position is updated to 0, and skips current block by table；After each position judgement and block operation, address moves back a list
Position, until executing to block address addr_max.
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|---|---|---|---|---|
| CN106527997B (en) * | 2016-11-25 | 2019-07-16 | 西安电子科技大学 | Method and device based on the NAND Flash bad block recycling for expanding sequence |
| CN106648463B (en) * | 2016-12-21 | 2020-06-16 | 广州立功科技股份有限公司 | Nand Flash block management method and system |
| CN106844079A (en) * | 2016-12-28 | 2017-06-13 | 中国北方车辆研究所 | The FLASH bad block managements system and management method of a kind of armored vehicle |
| CN106909519A (en) * | 2017-02-24 | 2017-06-30 | 济南浪潮高新科技投资发展有限公司 | A kind of Nand Flash memory mapped systems based on FPGA |
| CN106920576A (en) * | 2017-03-22 | 2017-07-04 | 惠州佰维存储科技有限公司 | A kind of method and system of inspection Nand Flash mass |
| CN108710580A (en) * | 2018-04-27 | 2018-10-26 | 江苏华存电子科技有限公司 | A kind of bad block management method promoting storage device active volume |
| CN109358814A (en) * | 2018-10-17 | 2019-02-19 | 天津易众腾动力技术有限公司 | A kind of method of EEPROM storage |
| CN109545266A (en) * | 2018-11-13 | 2019-03-29 | 深圳忆联信息系统有限公司 | A kind of solid state hard disk finds weak piece of method and its system |
| CN109783411B (en) * | 2018-12-20 | 2022-05-17 | 成都旋极历通信息技术有限公司 | FLASH array control method based on FPGA and controller |
| CN109634534B (en) * | 2019-01-02 | 2022-04-01 | 威胜集团有限公司 | Method for quickly judging capacity of memory chip |
| CN112764670A (en) * | 2019-11-04 | 2021-05-07 | 深圳宏芯宇电子股份有限公司 | Flash memory device and flash memory management method |
| CN112331252A (en) * | 2020-12-14 | 2021-02-05 | 深圳市芯天下技术有限公司 | Method and device for automatically marking bad blocks of Nand flash memory, storage medium and terminal |
| CN114546292B (en) * | 2022-02-28 | 2023-12-15 | 深圳市风云实业有限公司 | Method and system for managing nand flash bad blocks |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104360958A (en) * | 2014-12-09 | 2015-02-18 | 哈尔滨工业大学 | Bad block management system and bad block management method based on block reservation area replacement |
| CN104765695A (en) * | 2015-04-03 | 2015-07-08 | 上海交通大学 | NAND FLASH bad block management system and method |
| CN105005453A (en) * | 2015-07-17 | 2015-10-28 | 上海卫星工程研究所 | Bad block management system for satellite-based NAND FLASH solid memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8819328B2 (en) * | 2010-12-30 | 2014-08-26 | Sandisk Technologies Inc. | Controller and method for performing background operations |
-
2016
- 2016-03-24 CN CN201610173425.1A patent/CN105843749B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104360958A (en) * | 2014-12-09 | 2015-02-18 | 哈尔滨工业大学 | Bad block management system and bad block management method based on block reservation area replacement |
| CN104765695A (en) * | 2015-04-03 | 2015-07-08 | 上海交通大学 | NAND FLASH bad block management system and method |
| CN105005453A (en) * | 2015-07-17 | 2015-10-28 | 上海卫星工程研究所 | Bad block management system for satellite-based NAND FLASH solid memory |
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