CN105826421A - Indium bump device structure and preparation method for same - Google Patents
Indium bump device structure and preparation method for same Download PDFInfo
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- CN105826421A CN105826421A CN201610316689.8A CN201610316689A CN105826421A CN 105826421 A CN105826421 A CN 105826421A CN 201610316689 A CN201610316689 A CN 201610316689A CN 105826421 A CN105826421 A CN 105826421A
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- 229910052738 indium Inorganic materials 0.000 title claims abstract description 95
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 title claims abstract description 94
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 27
- 239000008188 pellet Substances 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 8
- 229910052906 cristobalite Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052682 stishovite Inorganic materials 0.000 claims description 8
- 229910052905 tridymite Inorganic materials 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000035882 stress Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 4
- 230000008646 thermal stress Effects 0.000 abstract description 4
- 230000035939 shock Effects 0.000 abstract description 3
- 238000009736 wetting Methods 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract 1
- 238000003466 welding Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000002207 thermal evaporation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 150000002471 indium Chemical class 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/09—Devices sensitive to infrared, visible or ultraviolet radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention relates to an indium bump device structure and a preparation method for the same and belongs to the technical field of preparation of indium bump devices. The device structure comprises a semiconductor substrate, a welding disk, a first passivation layer, a second passivation layer, a UBM metal layer and an indium bump, wherein the UBM metal layer comprises an adhesion layer, a blocking layer, a buffer layer and a wetting layer; and in the device structure, a part of the first passivation layer is covered by the adhesion layer, and a part of the adhesion layer is covered by the second passivation layer. High structural intensity is provided by the stacking structure, so that the structure composed of the indium bump and the UBM is prevented from being separated along an interface of the adhesion layer and the first passivation layer under effects of thermal stress when the device surfers from thermal shocks. In addition, internal stress changes between the substrate and the UBM during backflow are mitigated by setting of the buffer layer, so that the indium bump is prevented from being separated from the wetting layer under too large internal stress changes. Hence, the device structure provided by the invention has higher stability and a longer service life.
Description
Technical field
The invention belongs to indium bump device preparing technical field, be specifically related to a kind of indium bump device architecture and preparation method thereof.
Background technology
At present, infrared focal plane detector has been widely used in the aspects such as military affairs, industry, environment, medical science, and along with the progress of science and technology, the demand of large area array detector is continuously increased by people.But, also constantly increasing along with the design of the increase of pixel number, focal plane and reading circuit and the difficulty of interconnection.Tradition spun gold Wire Bonding Technology exposes obvious shortcoming, such as: the shortcomings such as interconnection resistance is high, circuit is long, package dimension is big and interconnection density is low.Flip-chip interconnection techniques can not only overcome above-mentioned shortcoming very well, and it is with low cost, is therefore widely used.
In Infrared Detectors flip-chip interconnection techniques, bottoming metal (UBM) plays adhesion, stops diffusion, infiltration and work function matching effect.Additionally, ductility is good under indium metal low temperature, there is under room temperature good flexibility, it is easy to realize bonding, there is good mechanically and electrically property of interconnections, be particularly well-suited to Infrared Detectors low-temperature working requirement.Therefore, for the flip-chip interconnection of Infrared Detectors, there is the indium bump structure of bottoming metal UBM it is critical that.
Shown in Fig. 1 is the cross-sectional structure figure of the indium bump device of prior art.This structure 100 includes Semiconductor substrate 101, pad 102, passivation layer 103, bottoming metal UBM104, indium pellet 105.Passivation layer 103 covers substrate 101 and a part of pad 102, and UBM104 is between pad 102 and indium pellet 105.
A total of three layers of UBM104, is adhesion layer 104a respectively, barrier layer 104b, soakage layer 104c.Adhesion layer 104a covers on the pad 102 exposed and portion of the passivating layer 103, and barrier layer 104b covers on adhesion layer 104a, and soakage layer 104c covers on the 104b of barrier layer, and the sectional dimension size of adhesion layer 104a, barrier layer 104b and soakage layer 104c is identical；Indium pellet 105 covers on soakage layer 104c.Wherein, adhesion layer 104a can strengthen the adhesion between pad 102 and barrier layer 104b, and the effect of barrier layer 104b is to stop indium pellet 105 and the diffusion reaction of lower metal, and soakage layer 104c can strengthen the adhesion of indium pellet 105 and UBM104.
General indium pellet 105, before being formed, needs to carry out the process of backflow contracting ball, is exactly i.e. that the indium post before thermal reflow is allowed to melt, and utilizes the surface tension of indium and the immersional wetting of UBM to make indium post become indium pellet, and then improves the height of indium bump.During backflow, melted indium meeting and the reaction of the soakage layer 104c bottom it generate layer of metal compound, the formation of metal compound layer can change the internal stress between UBM104 and substrate 101, when this internal stress changes greatly, may result in indium pellet 105 and comes off from soakage layer 104c.
In addition, in structure 100, owing to the periphery of UBM104 is distributed on passivation layer 103, the difference of the thermal coefficient of expansion between the structure 107 that the structure 106 and UBM104 being made up of substrate 101 and passivation layer 103 and indium bump 105 form, when indium bump device is when backflow is by high temperature (180 DEG C) thermal shock, producing thermal stress between adhesion layer 104a and passivation layer 103, the structure 107 ultimately resulting in UBM104 and indium bump 105 composition comes off along adhesion layer 104a and the interface of passivation layer 103.
The above-mentioned performance either way influencing whether device and stability, shorten the life-span of device.The most how overcoming the deficiencies in the prior art is the problem that current indium bump device preparing technical field needs solution badly.
Summary of the invention
The invention aims to solve the deficiencies in the prior art, it is provided that a kind of indium bump device architecture and preparation method thereof, to improve the situation that indium bump comes off, improve stability and the life-span of indium bump device.
For achieving the above object, the technical solution used in the present invention is as follows:
A kind of indium bump device architecture, it is characterised in that include Semiconductor substrate, pad, the first passivation layer, the second passivation layer, UBM metal level and indium bump；
UBM metal level includes adhesion layer, barrier layer, cushion and the soakage layer set gradually from top to bottom；
Pad is placed in the surface of Semiconductor substrate, and the first passivation layer is overlying on Semiconductor substrate and bond pad surface, and the first passivation layer is provided with the first opening with pad overlapping, bond pad surface is exposed by the first opening part；
Adhesion layer is overlying in the bond pad surface that the first opening part exposes, and the peripheral part of adhesion layer is positioned in the first passivation layer surface so that adhesion layer and the first passivation layer partly overlap；
Second passivation layer is overlying on the first passivation layer surface and adhesion layer surface, and the second passivation layer is provided with the second opening with adhesion layer overlapping, is exposed by the second opening by adhesion layer；
The cross-sectional width of the second opening is more than the cross-sectional width of the first opening；
Barrier layer is located on the adhesion layer surface that the second opening part exposes, and cushion is overlying on barrier layer surface, and soakage layer is overlying on buffer-layer surface, and indium bump is overlying on soakage layer surface；
Further, barrier layer, cushion and soakage layer and the second passivation layer do not contact；
The cross-sectional width of barrier layer, cushion and soakage layer is the most identical；The cross-sectional width of adhesion layer is more than the cross-sectional width on barrier layer.
It is further preferred that the material of described Semiconductor substrate is Si.
It is further preferred that the material of the first described passivation layer is SiO2Or Si3N4, the material of the second passivation layer is SiO2Or Si3N4, and the first passivation layer and the second passivation layer material identical.
It is further preferred that the material of described pad is metal Al or Cu.
It is further preferred that the material of described adhesion layer is metal Ti, Ni, Cr or Ta.
It is further preferred that the material on described barrier layer is Pt metal, Pd, Ni.
It is further preferred that described cushion is identical with the material of soakage layer, it is metal Au.
It is further preferred that the material of described indium bump is indium metal；Indium bump is spherical or column.
The preparation method of above-mentioned indium bump device architecture, comprises the steps:
Step (1), takes a Semiconductor substrate with pad, is covered on substrate and pad by the first passivation layer, then obtains the first opening by photoetching and etching, to expose part pad；
Step (2), covers adhesion layer in the bond pad surface that the first opening part exposes, and part is covered on the first passivation layer；
Step (3), is overlying on the second passivation layer the first passivation layer surface and adhesion layer surface, then obtains the second opening by photoetching and etching, to expose part adhesion layer；
Step (4), deposits barrier layer on the adhesion layer surface that the second opening part exposes, covers cushion the most over the barrier layer, cover soakage layer the most on the buffer layer；
Step (5), deposits indium metal on soakage layer and forms indium post, be then refluxed for making indium post become indium pellet.
Compared with prior art, it has the beneficial effect that the present invention
In the indium bump device architecture that the present invention provides, adhesion layer covers part the first passivation layer, second passivation layer covers again part adhesion layer, this stacked structure provides higher structural strength, so when device is by thermal shock, it is possible to prevent the situation that the structure of the indium bump caused due to thermal stress and UBM composition comes off along adhesion layer and the first passivation layer interface.
In addition, in the indium bump device architecture that the present invention provides, UBM structure has one layer of cushion metal Au, it serves the effect of buffering, relax the change of internal stress when backflow between substrate and UBM the most exactly, and then prevented owing to internal stress changes the situation that indium bump that is excessive and that cause comes off from soakage layer.
Therefore, traditional device architecture compared by the indium bump device architecture that the present invention provides, and has higher stability, and the service life of device, compared with traditional devices, improves 15%.
Accompanying drawing explanation
Shown in Fig. 1 is the cross-sectional structure figure of the indium bump device of prior art.
Shown in Fig. 2 is the cross-sectional structure figure of the indium bump device of the present invention.
Shown in Fig. 3 A-3I is the flow chart of the indium bump device architecture formation of the present invention.
Wherein, 200, indium bump device architecture；201, Semiconductor substrate；202, pad；203, the first passivation layer；203a, the first opening；204, the second passivation layer；204a, the second opening；205, UBM metal level；205a, adhesion layer；205b, barrier layer；205c, cushion；205d, soakage layer；206, indium bump；207, the first lithographic mask layer；208, the first cross section opening；209, the second lithographic mask layer；210, the second cross section opening；211, the 3rd lithographic mask layer；212, the 3rd cross section opening；213, indium post；214, there is the indium pellet of UBM layer.
Detailed description of the invention
Below in conjunction with embodiment, the present invention is described in further detail.
It will be understood to those of skill in the art that the following example is merely to illustrate the present invention, and should not be taken as limiting the scope of the invention.Unreceipted concrete technology or condition person in embodiment, according to the technology described by the document in this area or condition or carried out according to product description.Agents useful for same or instrument unreceipted production firm person, be the conventional products that can be obtained by purchase.
It should be appreciated by those skilled in the art that so marking after being drawn on the both sides of the first opening 203a and the second opening 204a, the width of extraction is also cross-sectional width again owing to layer structure of the present invention is overlapping.
Shown in Fig. 2 is the cross-sectional structure figure of the indium bump device of the present invention.This indium bump device architecture 200 comprises Semiconductor substrate 201, pad the 202, first passivation layer the 203, second passivation layer 204, UBM metal level 205, indium bump 206.UBM metal level 205 includes setting gradually adhesion layer 205a, barrier layer 205b, cushion 205c and soakage layer 205d from top to bottom.
Pad 202 is placed in the surface of Semiconductor substrate 201, and the first passivation layer 203 is overlying on Semiconductor substrate 201 and pad 202 surface, and the first passivation layer 203 is provided with the first opening 203a with pad 202 overlapping, is exposed by the first opening 203a on pad 202 surface；
Adhesion layer 205a is overlying on pad 202 surface exposed at the first opening 203a, and the peripheral part of adhesion layer 205a is positioned on the first passivation layer 203 surface so that adhesion layer 205a and the first passivation layer 203 partly overlap；
Second passivation layer 204 is overlying on the first passivation layer 203 surface and adhesion layer 205a surface, and the second passivation layer 204 is provided with the second opening 204a with adhesion layer 205 overlapping, is exposed by the second opening 204a by adhesion layer 205a；
The cross-sectional width of the second opening 204a cross-sectional width more than the first opening 205a；
Barrier layer 205b is located on the adhesion layer 205a surface exposed at the second opening 204a, and cushion 205c is overlying on 205b surface, barrier layer, and 205d soakage layer is overlying on cushion 205c surface, and indium bump 206 is overlying on soakage layer surface；Indium bump 206 in Fig. 2 is spherical, i.e. indium pellet.
Further, barrier layer 205b, cushion 205c and soakage layer 205d and the second passivation layer 204 do not contact；
Barrier layer 205b, cushion 205c are the most identical with the cross-sectional width of soakage layer 205d；The cross-sectional width of the adhesion layer 205a cross-sectional width more than barrier layer 205b.
I.e. first passivation layer 203 covers on substrate 201 and part pad 202；Adhesion layer 205a covers on the pad 202 exposed and part the first passivation layer 203, and its cross-sectional width is d1；Second passivation layer 204 covers the first passivation layer 203 and part adhesion layer 205a；Barrier layer 205b, cushion 205c and soakage layer 205d cover in succession on the part adhesion layer 205a exposed, and barrier layer 205b, cushion 205c are all d mutually with the cross-sectional width of soakage layer 205d2, and d2Less than d1；Indium bump 206 covers on soakage layer 205d.
The material of described Semiconductor substrate is Si.
The material of the first described passivation layer 203 is SiO2Or Si3N4, the material of the second passivation layer 204 is SiO2Or Si3N4, and the first passivation layer 203 is identical with the second passivation layer 204 material.
The material of described pad 202 is metal Al or Cu.
The material of described adhesion layer 205a is metal Ti, Ni, Cr or Ta.
The material of described barrier layer 205b is Pt metal, Pd, Ni.
Described cushion 205c is identical with the material of soakage layer 205d, is metal Au.
The material of described indium bump 206 is indium metal；Indium bump 206 can also be column.
Fig. 3 A provides a Semiconductor substrate 201 with pad 202.First passivation layer 203 covers in Semiconductor substrate 201 and part pad 202.First passivation layer 203 is SiO2Or Si3N4, pad 202 is metal Al or Cu.The structure of the first passivation layer 203 can be realized by a series of processes such as plasma reinforced chemical vapour deposition PECVD, photoetching and etchings.
In Fig. 3 B, the first lithographic mask layer 207 has size is d1The first cross section opening 208, adhesion layer 205a deposits in the first cross section opening 208, covers pad 202 and part first passivation layer 203 of exposure.First lithographic mask layer 207 can be realized by a series of processes such as coating photoresist, photoetching and developments.Adhesion layer 205a is metal Ti, Ta, Cr, and the deposition of adhesion layer 205a can be realized by means such as sputtering, thermal evaporations, and the first lithographic mask layer 207 can utilize acetone to get rid of, and finally giving cross sectional dimensions is d1Adhesion layer 205a, adhesion layer 205a cover pad 202 and part first passivation layer 203 of exposure, as shown in Figure 3 C.
In fig. 3d, the second passivation layer 204 covers the first passivation layer 203 and part adhesion layer 205a.Second passivation layer 204 is SiO2、Si3N4, the structure of the second passivation layer 204 can be realized by a series of processes such as plasma reinforced chemical vapour deposition PECVD, photoetching and etchings.
In Fig. 3 E, the second lithographic mask layer 209 has size is d2The second cross section opening 210, barrier layer 205b, cushion 205c and soakage layer 205d be sequentially deposited in the second cross section opening 210, is i.e. sequentially deposited on the adhesion layer 205a that exposes.Barrier layer 205b is Pt, Pd, Ni, and cushion 205c and soakage layer 205d is all metal Au.Barrier layer 205b, the deposition of cushion 205c and soakage layer 205d can be realized by means such as sputtering, thermal evaporations.Second lithographic mask layer 209 can be realized by a series of processes such as coating photoresist, photoetching and developments.Second lithographic mask layer 209 can utilize acetone to get rid of, and obtaining cross sectional dimensions is d2Barrier layer 205b, cushion 205c and soakage layer 205d, as illustrated in Figure 3 F, especially, d2Cross sectional dimensions d less than adhesion layer 205a1。
Having the 3rd lithographic mask layer 211 of the 3rd cross section opening 212 in Fig. 3 G, indium metal deposits in the 3rd cross section opening 212.3rd lithographic mask layer 211 can be by coating photoresist, a series of process such as photoetching and development realizes, and the deposition of indium metal can be realized by means such as sputtering, thermal evaporations, and the 3rd lithographic mask layer 211 utilizes acetone to get rid of subsequently, finally give indium post 213, as shown in figure 3h.
Indium bump 206 in Fig. 3 I can be obtained by backflow indium post 213, and in reflux course, melted indium post 213 utilizes surface tension to form indium bump 206(the present embodiment and defines indium pellet).In addition, melted indium post 213 meeting and the Au reaction of the soakage layer 205d bottom it generate Au-In metallic compound, the generation of Au-In metallic compound can change the internal stress between UBM metal level 205 and Semiconductor substrate 201, but UBM metal level 205 in the present invention has the cushion 205c of layer of metal Au, the existence of cushion 205c significantly reduces the change of the internal stress between UBM metal level 205 and Semiconductor substrate 201, and then prevents indium bump 206 from coming off from the surface of soakage layer 205d.
In addition, the structure being made up of the first passivation layer 203, adhesion layer 205a and the second passivation layer 204 in the present invention has higher structural strength, so when device is by high temperature thermal shocking, it is possible to prevent the situation causing the structure 214 being made up of UBM metal level 205 and indium bump 206 to come off due to thermal stress along adhesion layer 205a and the interface of the first passivation layer 203.
Therefore, traditional device architecture compared by the device architecture of the indium bump that the present invention provides, and has higher stability, the service life of device is greatly improved.
The ultimate principle of the present invention, principal character and advantages of the present invention have more than been shown and described.Skilled person will appreciate that of the industry; the present invention is not restricted to the described embodiments; the principle that the present invention is simply described described in above-described embodiment and description; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements both fall within scope of the claimed invention.Claimed scope is defined by appending claims and equivalent thereof.
Claims (9)
1. an indium bump device architecture, it is characterised in that include Semiconductor substrate, pad, the first passivation layer, the second passivation layer, UBM metal level and indium bump；
UBM metal level includes adhesion layer, barrier layer, cushion and the soakage layer set gradually from top to bottom；
Pad is placed in the surface of Semiconductor substrate, and the first passivation layer is overlying on Semiconductor substrate and bond pad surface, and the first passivation layer is provided with the first opening with pad overlapping, bond pad surface is exposed by the first opening part；
Adhesion layer is overlying in the bond pad surface that the first opening part exposes, and the peripheral part of adhesion layer is positioned in the first passivation layer surface so that adhesion layer and the first passivation layer partly overlap；
Second passivation layer is overlying on the first passivation layer surface and adhesion layer surface, and the second passivation layer is provided with the second opening with adhesion layer overlapping, is exposed by the second opening by adhesion layer；
The cross-sectional width of the second opening is more than the cross-sectional width of the first opening；
Barrier layer is located on the adhesion layer surface that the second opening part exposes, and cushion is overlying on barrier layer surface, and soakage layer is overlying on buffer-layer surface, and indium bump is overlying on soakage layer surface；
Further, barrier layer, cushion and soakage layer and the second passivation layer do not contact；
The cross-sectional width of barrier layer, cushion and soakage layer is the most identical；The cross-sectional width of adhesion layer is more than the cross-sectional width on barrier layer.
Indium bump device architecture the most according to claim 1, it is characterised in that the material of described Semiconductor substrate is Si.
Indium bump device architecture the most according to claim 1, it is characterised in that the material of the first described passivation layer is SiO2Or Si3N4, the material of the second passivation layer is SiO2Or Si3N4, and the first passivation layer and the second passivation layer material identical.
Indium bump device architecture the most according to claim 1, it is characterised in that the material of described pad is metal Al or Cu.
Indium bump device architecture the most according to claim 1, it is characterised in that the material of described adhesion layer is metal Ti, Ni, Cr or Ta.
Indium bump device architecture the most according to claim 1, it is characterised in that the material on described barrier layer is Pt metal, Pd, Ni.
Indium bump device architecture the most according to claim 1, it is characterised in that described cushion is identical with the material of soakage layer, is metal Au.
Indium bump device architecture the most according to claim 1, it is characterised in that the material of described indium bump is indium metal；Indium bump is spherical or column.
9. the preparation method of the indium bump device architecture described in claim 1-8, it is characterised in that comprise the steps:
Step (1), takes a Semiconductor substrate with pad, is covered on substrate and pad by the first passivation layer, then obtains the first opening by photoetching and etching, to expose part pad；
Step (2), covers adhesion layer in the bond pad surface that the first opening part exposes, and part is covered on the first passivation layer；
Step (3), is overlying on the second passivation layer the first passivation layer surface and adhesion layer surface, then obtains the second opening by photoetching and etching, to expose part adhesion layer；
Step (4), deposits barrier layer on the adhesion layer surface that the second opening part exposes, covers cushion the most over the barrier layer, cover soakage layer the most on the buffer layer；
Step (5), deposits indium metal on soakage layer and forms indium post, be then refluxed for making indium post become indium pellet.
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| CN108987523A (en) * | 2017-06-05 | 2018-12-11 | 北京弘芯科技有限公司 | Infrared focal plane detector and preparation method thereof |
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| CN113314556A (en) * | 2021-05-28 | 2021-08-27 | 北京智创芯源科技有限公司 | Focal plane detector and indium ball array preparation method thereof |
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| CN106653945A (en) * | 2016-12-12 | 2017-05-10 | 中国电子科技集团公司第十研究所 | Method for obtaining indium balls of readout circuit |
| CN108231728A (en) * | 2016-12-12 | 2018-06-29 | 英飞凌科技奥地利有限公司 | Semiconductor devices, electronic building brick and method |
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| CN109727950B (en) * | 2018-12-26 | 2020-12-04 | 中国电子科技集团公司第四十四研究所 | Hybrid focal plane flip-chip integration bump structure and manufacturing method thereof |
| US20220359444A1 (en) * | 2021-05-07 | 2022-11-10 | Microsoft Technology Licensing, Llc | Electroplated indium bump stacks for cryogenic electronics |
| US11862593B2 (en) * | 2021-05-07 | 2024-01-02 | Microsoft Technology Licensing, Llc | Electroplated indium bump stacks for cryogenic electronics |
| CN113314556A (en) * | 2021-05-28 | 2021-08-27 | 北京智创芯源科技有限公司 | Focal plane detector and indium ball array preparation method thereof |
| CN113314556B (en) * | 2021-05-28 | 2022-02-15 | 北京智创芯源科技有限公司 | Focal plane detector and indium ball array preparation method thereof |
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