CN105720563B - A kind of more principle relay protection chips and its method based on FPGA - Google Patents
A kind of more principle relay protection chips and its method based on FPGA Download PDFInfo
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Abstract
The present invention relates to a kind of more principle relay protection chips and its method based on FPGA, the chip includes data acquisition module, FPGA module, MCU module and communications peripheral interface；The data acquisition module, FPGA module, MCU module and communications peripheral interface are sequentially connected.The method includes the voltage of input, current-mode analog quantity are converted to voltage signal；Voltage signal is input to multiple selector and AD unit；Digital signal after AD cell translation is sent in FFT unit and carries out operation；It sends the signal obtained after FFT unit operation in measuring unit and hardware protection algorithm unit；Data buffer zone is sent by the operation result of FFT unit, measuring unit and hardware protection algorithm unit；The relay action signal of data buffer zone is sent to dispatch control unit in output control and MCU module；MCU module interacts related control data and dispatch control unit.
Description
Technical field
The present invention relates to a kind of relay protection chip, in particular to a kind of more principle relay protection chips based on FPGA
And its method.
Background technique
Protective relaying device, which refers to, can reflect in electric system that electrical component breaks down or irregular operating state, and move
Make in circuit breaker trip or issues a kind of automatic device of signal.Protective relaying device is widely used in existing electric system,
And it is played an important role in New Generation of Intelligent substation.In traditional relay protection system design, DSP+ is mostly used
The framework of MCU module realizes there is certain flexibility and operability, but with the continuous development of smart grid, a new generation
Intelligent substation requires to realize miniaturization, the integrated, modularization, wisdom of substation, dynamic in protection to protective relaying device
Making speed sum aggregate, above more stringent requirements are proposed at change, and the framework of DSP+MCU module is in terms of integrated, modularization and reliability
All have much room for improvement.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of more principle relay protection chips based on FPGA and its side
Method is being based on field programmable gate array (Field-Programmable Gate Array, FPGA) and microprocessor
On the basis of the hardware structure of (Micro Control Unit, MCU module), system using data acquisition, Digital Signal Processing, firmly
Part protection algorism, FPGA and MCU module process scheduling and the modules such as FPGA and peripheral communication are analyzed and are designed, and
Hardware compilation and experimental verification have been carried out on QuartusII.The present invention improves the protection act speed of relay protection system, pressure
Contracted the volume of device, and architecturally has reconfigurability.
The purpose of the present invention is adopt the following technical solutions realization:
A kind of more principle relay protection chips based on FPGA, it is improved in that the chip includes data acquisition
Module, FPGA module, MCU module and communications peripheral interface；
The data acquisition module, FPGA module, MCU module and communications peripheral interface are sequentially connected；
The data acquisition module includes analog input unit, dispatch circuit, multiple selector and AD unit；
The FPGA module includes FFT unit, hardware protection unit, measuring unit, output control unit, data buffer zone
Area and multi-path choice control unit；
The MCU module includes scheduling controller and communication unit；
The communications peripheral interface includes EEPROM interface, LCD Interface, keyboard interface and RS485 interface.
The present invention is based on a kind of more principle relay protecting methods based on FPGA that another object proposes, improvements exist
In, the method includes
(1) voltage of input, current-mode analog quantity are converted into voltage signal；
(2) voltage signal is input to multiple selector and AD unit；
(3) digital signal after AD cell translation is sent in FFT unit and carries out operation；
(4) it sends the signal obtained after FFT unit operation in measuring unit and hardware protection algorithm unit；
(5) data buffer zone is sent by the operation result of FFT unit, measuring unit and hardware protection algorithm unit；
(6) relay action signal of data buffer zone is sent to dispatch control unit in output control and MCU module；
(7) MCU module interacts related control data and dispatch control unit, passes through EEPROM, liquid crystal display, keyboard
The communication with peripheral hardware is completed with RS485.
Preferably, the step (1) includes by mutual inductor, filter circuit and voltage conversion circuit, signal conditioning circuit
16 road voltages of input, current-mode analog quantity are converted to the voltage signal lower than 2.5V.
Preferably, the step (2) includes that the voltage signal is input to multiple selector and AD unit, is completed to input
16 channel analogy amounts every channel 32 real-time samplings of every cycle, and export corresponding 14 AD cell datas.
Preferably, the step (3) includes the Fast Fourier Transform (FFT) that FFT unit realizes AD unit sampling data, frequency
Measurement, virtual value calculates and power calculation, wherein and FFT unit calculates the fundamental wave of the every cycle in every channel and the amplitude of 15 subharmonic,
Fundamental wave provides real-time data input for hardware protection algorithm unit, and harmonic wave is used for power quality analysis.
Further, the extraction of square root operation in the virtual value calculating uses look-up table, realizes the efficient of hardware resource
It utilizes, every cycle 20ms 32 points of progress FFT unit calculating each to every channel, totally 16 channel, i.e., every cycle completes 512 points of FFT
Unit, clock frequency use 12MHz.
Preferably, the step (4) includes by the signal obtained after FFT unit operation while being sent to measuring unit and hard
In part protection algorism unit, wherein measuring unit is used to measure the real-time amplitude in its each channel, and hardware protection algorithm unit is used for
Realization presses through stream, inverse-time overcurrent and differential protection, common three-stage overcurrent protection, low-frequency load reduction protection and zero sequence overcurrent again
With the algorithm of zero sequence overvoltage protection.
Preferably, the hardware protection algorithm unit throws the defencive function mould for moving back control word selection starting by defencive function
Block is compared according to the calculated result of FFT unit and with the definite value in Electrically Erasable Programmable Read-Only Memory, passes through each protection
The corresponding protection act of logic function progress of module, output protection action value, alarm signal and SOE event, and fixed value modification,
The transmission that protection throwing moves back work and SOE event is controlled by MCU module.
Preferably, the step (5) includes by the operation result of FFT unit, measuring unit and hardware protection algorithm unit
Real-time transmission is to data buffer zone, arrangement and output of the data buffer zone for realizing event queue SOE, while and MCU module
Middle dispatch control unit carries out data interaction.
Preferably, the step (6) includes that the relay action signal of data buffer zone is sent to output control, through exporting
Control is transmitted to relay output end mouth；While the data of data buffer zone are by the control of dispatch control unit in MCU module, it is complete
At the data communication of MCU module and FPGA.
Further, the communication of the FPGA and MCU module uses customized simultaneously and concurrently bus protocol, in the agreement
On the basis of realize process effective scheduling, the process of scheduling comprising protection algorism throwing move back control, switching value, electricity, effectively
Value, performance number, frequency values, definite value, breaker control, higher hamonic wave value and SOE event.
Preferably, the step (7) includes that MCU module interacts related control data and dispatch control unit, is led to
The communication of EEPROM, liquid crystal display, keyboard and RS485 completion and peripheral hardware are crossed, the EEPROM reads control word for MCU module,
Liquid crystal is for showing, keyboard is for inputting, and RS485 is for communication with the outside.
Compared with the prior art, the invention has the benefit that
(1) present invention uses FPGA+MCU module architectures, executes program using the hardware concurrent of FPGA and improves hardware protection
The processing speed of logic guarantees the safety and reliability of system.
(2) design of the invention has reconfigurability, and relay protection algorithm is independent, in many occasions of relay protection,
It only needs it can be made to be applied to route protection, bus protection and tranformer protection etc. by changing hardware protection algorithm unit
Field.
(3) design of the invention has reconfigurability, can be under the premise of not promoting CPU frequency, high-speed response protection
It is required that.
(4) design of the invention has compressed the volume of device, be conducive to the site of smart grid secondary device with it is small-sized
Change, provides " core " for smart grid and support.
Detailed description of the invention
Fig. 1 is a kind of more principle relay protection chip concept figures based on FPGA provided by the invention.
Fig. 2 is hardware protection algorithm logic block diagram provided by the invention.
Specific embodiment
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing.
As shown in Figure 1, a kind of more principle relay protection chips based on FPGA of the present invention comprising data acquisition module,
FPGA module, MCU module and communications peripheral interface；
Data acquisition module, FPGA module, MCU module and communications peripheral interface are sequentially connected；
Data acquisition module includes analog input unit, dispatch circuit, multiple selector and AD unit；
FPGA module include FFT unit, hardware protection unit, measuring unit, output control unit, data buffering it is trivial and
Multi-path choice control unit；
MCU module includes scheduling controller and communication unit；
Communications peripheral interface includes EEPROM interface, LCD Interface, keyboard interface and RS485 interface.
A kind of more principle relay protecting methods based on FPGA of the present invention, integrate metering, protection, communication function, adopt
With FPGA+MCU module hardware framework, the control of FPGA data acquisition, Digital Signal Processing, hardware protection algorithm and FPGA with
The function of MCU module communication control, MCU module complete the function of interacting with peripheral communication and MCU module with FPGA data.Specifically
Method is as follows:
1, the voltage of input, current-mode analog quantity are converted into voltage signal；
Wherein, voltage conversion, real-time sampling, storage and the analog-to-digital conversion of input analog quantity are realized in data acquisition.Firstly, logical
Mutual inductor, filter circuit and voltage conversion circuit are crossed, signal conditioning circuit is converted to 16 road voltages of input, current-mode analog quantity
Voltage signal lower than 2.5V.
2, voltage signal is input to multiple selector and AD unit；
The voltage signal is input to multiple selector and AD unit, completes every channel to 16 channel analogy amounts of input
32 real-time samplings of every cycle, and export corresponding 14 AD cell datas.
3, the digital signal after AD cell translation is sent in FFT unit and carries out operation；
Fast Fourier Transform (FFT) (the Fast Fourier of Digital Signal Processing realization AD unit sampling data
Transformation, FFT unit), frequency measurement, virtual value calculate and power calculation function.FFT unit calculates every channel
The amplitude of the fundamental wave of every cycle and 15 subharmonic, fundamental wave provide real-time data input, harmonic wave for hardware protection algorithm unit
For power quality analysis.FFT unit uses the radix-4 butterfly algorithm of altera corp's IP kernel, has both met wanting for speed and resource
It asks, and convenient for being debugged to the layout of FPGA, wiring and hardware.Virtual value calculate in extraction of square root operation using look-up table realization,
Guaranteeing that precision is high, efficient utilization fireballing while that realize hardware resource.32 points each to every channel of every cycle (20ms)
FFT unit calculating is carried out, totally 16 channel, i.e., every cycle completes 512 points of FFT unit, and clock frequency uses 12MHz.
4, it by the signal obtained after FFT unit operation while being sent in measuring unit and hardware protection algorithm unit,
Middle measuring unit is used to measure the real-time amplitude in its each channel, and hardware protection algorithm unit for realizing pressing through stream, inverse time lag again
The algorithm of overcurrent and differential protection etc.；
Hardware protection algorithm mainly includes multiple pressure overcurrent protection, inverse-time overcurrent protection, differential protection and three sections common
Formula overcurrent protection, low-frequency load reduction protection (with low-voltage dead lock and slippage blocking function), zero sequence overcurrent and zero sequence overvoltage protection etc..
Hardware protection algorithm unit, which moves back control word selection by defencive function throwing, needs defencive function module to be started, mono- further according to FFT
Member calculated result and with definite value (time definite value, current ration, the voltage in Electrically Erasable Programmable Read-Only Memory (EEPROM)
Definite value etc.) it is compared, corresponding protection act is carried out by the logic function of each protective module, while output protection acts
Value, alarm signal and SOE event etc., and the transmission that fixed value modification, protection throwing move back work and SOE event is controlled by MCU module.
Wherein, overcurrent protection is pressed to calculate positive sequence voltage, negative sequence voltage, zero according to the three-phase phase voltage and phase current of input again
Sequence voltage and forward-order current then realize negative sequence voltage latch-up protection by the way that time delay condition is compared and met with setting valve；Instead
Time limit overcurrent protection carries out curve fitting calculating to 0.02 power function of general inverse time lag using Taylor series expansion method；It is differential
The biased differential protection and difference stream fast tripping protection of both ends formula are realized in protection, and biased differential protection is by calculating six Xiang Xiang electricity of first and last end
Stream makees difference and realization of making comparisons with difference current minimum movements definite value and the minimum restraint current；Three-stage overcurrent protection scheduling algorithm is logical
It is compared after the amplitude inputted in real time with the setting valve of time and amplitude, and exports fault value and relay trip signal.
Hardware protection algorithm logic block diagram is as shown in Figure 2.Wherein I in biased differential protectionAT、IBT、ICTFor test line or
The head end electric current of device, IAN、IBN、ICNFor tail current, S is ratio brake coefficient, IOPFor difference current minimum movements definite value,
IresFor the minimum restraint current；I in inverse-time overcurrent protectionAset、IBset、ICsetRespectively three-phase phase current over-current adjusting value, Ip
For current reference value, tpFor time constant；U in overcurrent protection is pressed againA、UB、UC、UORespectively A, B, C three-phase phase voltage and zero sequence
Voltage, IZsetFor positive sequence current setting, VZsetFor positive sequence voltage setting valve, VFsetFor negative sequence voltage setting valve, VOsetFor zero sequence
Voltage setting valve.
5, by the operation result real-time transmission of FFT unit, measuring unit and hardware protection algorithm unit to data buffer zone,
Data buffer zone for realizing event queue SOE arrangement and output, while in MCU module dispatch control unit carry out data
Interaction；
Some processes are controlled by PORT COM in each task process, such as reading of the MCU module to frequency values；It is some into
Journey wants spontaneous wake-up, occurs if any SOE event, and system must notify immediately MCU module to read after FIFO is written, and read simultaneously
The time that SOE event occurs in real-time timepiece chip is taken to lose SOE thing if this process is too long (being more than 10ms)
The precision of part record；Such as watt metering module is recorded certain value (such as 10 degree) and MCU module will be notified to read electricity
Angle value is simultaneously written in E2PROM.
6, the relay action signal of data buffer zone is sent to output control, is transmitted to relay output through output control
Port；The data of data buffer zone are completed the number of MCU module and FPGA by the control of dispatch control unit in MCU module simultaneously
According to communication；
FPGA and MCU module process scheduling are completed measured data, fixed value information, SOE event information and relay control and are believed
The scheduling of breath and the system-level scheduling of task process.In order to guarantee the transmission speed of system data and the reliability of protection act,
The communication of FPGA and MCU module uses customized simultaneously and concurrently bus protocol, and the effective of process is realized on the protocol basis
Scheduling, the process of scheduling include protection algorism throwing move back control, switching value, electricity, virtual value, performance number, frequency values, definite value,
Breaker control, higher hamonic wave value and SOE event etc..
During the realization of communication task process scheduling, order that host state machine variable is sent according to peripheral control unit
Number, the enable signal of the corresponding process of set, until process end signal is raised into idle state.All task process are each other
Independent, parallel, they only pass through the respective enable signal launching process of real-time detection, after the completion of once-through operation, remove automatically certainly
Oneself enable signal restarts new process in order to next host state machine.Other than host state machine, other all state machines
Any process cannot all be started, all processes oneself spontaneous can not start, only SOE event buffering FIFO and internal data school
Testing error module etc. can force peripheral control unit to say the word word in the shortest time to start corresponding task by irq signal
Process.
Wherein, FPGA is defined as follows with MCU module internal bus protocol:
(1) bus definition
In order to guarantee the reliability of system data transmission speed and protection act, the communication of FPGA and MCU module is using same
Walk parallel bus protocol.Its mutual signal of communication is 11, is described in detail below:
DATA [7:0]: 8 BDB Bi-directional Data Bus；
TCLK: parallel transmission clock signal is controlled by MCU module and is generated, high level corresponding data validity period；
ACK: data direction id signal is controlled by MCU module and is generated, and high level indicates that FPGA hair MCU module is received, low electricity
It is flat to indicate that MCU module hair FPGA is received；
FLAG: data transfer request signal is controlled by FPGA and is generated, and low level indicates that MCU module must send correspondence and look into
Order is ask to read SOE event or electric degree value.
(2) command number
It is since transmission data type and content are more, it is separately shown according to command number.Opening for process is transmitted each time
Dynamic and end is all controlled by MCU module, and MCU module is notified according to the first character section (namely command number) for being sent to FPGA
Next data content that FPGA is transmitted, while determining the total amount of byte for needing to transmit.
7, MCU module interacts related control data and dispatch control unit, passes through EEPROM, liquid crystal display, keyboard
The communication with peripheral hardware is completed with RS485, the EEPROM reads control word for MCU module, and for showing, keyboard is used for liquid crystal
Input, RS485 is for communication with the outside.
MCU module and peripheral communication provide the RS485 interface of standard, complete the communication with host computer, realize remote signalling, distant
It surveys, the function of remote control and the transmission of SOE event.Meanwhile MCU module and EEPROM carry out data interaction by I2C bus, it is fixed to realize
The reading data and modification of value, time etc.；MCU module and display screen and keyboard are defined by customized communication port completes number
According to control and display.
Embodiment
The present invention develops software by QuartursII and carries out system design and synthesis, using ALTERA company Cyclone
The EP1C12Q240C8 of series carries out simulation hardware.The FPGA realize multiple selector control, the control of AD unit, FFT unit, firmly
Functions, the resources of chip occupancy situations such as part protection algorism, frequency calculating, the communication of power calculation and FPGA and MCU module are shown in Table
1.
System design has reconfigurability, it is only necessary to change relevant hardware protection algorithm and interface, can be realized
Suitable for the System on Chip/SoC of different relay protection fields, while the system shortens the operation hardware protection time, has compressed relay protection
The design of device volume, relay protection system chip also provides for the miniaturization of New Generation of Intelligent substation and intelligentized application
More wide space.
Finally it should be noted that: the above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, institute
The those of ordinary skill in category field can still modify to a specific embodiment of the invention referring to above-described embodiment or
Equivalent replacement, these are applying for this pending hair without departing from any modification of spirit and scope of the invention or equivalent replacement
Within bright claims.
Claims (9)
1. a kind of more principle relay protection chips based on FPGA, which is characterized in that the chip include data acquisition module,
FPGA module, MCU module and communications peripheral interface；
The data acquisition module, FPGA module, MCU module and communications peripheral interface are sequentially connected；
The data acquisition module includes analog input unit, signal conditioning circuit, multiple selector and AD unit；
The FPGA module includes FFT unit, hardware protection algorithm unit, measuring unit, output control unit, data buffer zone
With multi-path choice control unit；
The MCU module includes dispatch control unit and communication unit；
The communications peripheral interface includes EEPROM interface, LCD Interface, keyboard interface and RS485 interface；Based on FPGA's
More principle relay protecting methods include:
The voltage of input, current-mode analog quantity are converted to voltage signal by step (1)；
Voltage signal is input to multiple selector and AD unit by step (2)；
Digital signal after AD cell translation is sent in FFT unit by step (3) carries out operation；
Step (4) sends the signal obtained after FFT unit operation in measuring unit and hardware protection algorithm unit；
The operation result of FFT unit, measuring unit and hardware protection algorithm unit is sent data buffer zone by step (5)；
Step (6) data buffering is trivial to be sent to output control unit for relay action signal；Scheduling controlling list in MCU module
Member control data buffer zone；
Step (7) MCU module interacts related control data and dispatch control unit, by communications peripheral interface complete with
The communication of peripheral hardware；
The step (4) includes by the signal obtained after FFT unit operation while being sent to measuring unit and hardware protection algorithm
In unit, wherein measuring unit is used to measure the real-time amplitude in its each channel, and hardware protection algorithm unit for realizing pressing through again
Stream, inverse-time overcurrent and differential protection, three-stage overcurrent protection, low-frequency load reduction protection and zero sequence overcurrent and zero sequence overvoltage protection
Algorithm；
The step (1) includes passing through mutual inductor, filter circuit and voltage conversion circuit, signal condition electricity in data acquisition module
16 road voltages of input, current-mode analog quantity are converted to the voltage signal lower than 2.5V by road.
2. a kind of more principle relay protection chips based on FPGA as described in claim 1, which is characterized in that the step
(2) include that the voltage signal is input to multiple selector and AD unit, complete every channel to 16 channel analogy amounts of input
32 real-time samplings of every cycle, and export corresponding 14 AD cell datas.
3. a kind of more principle relay protection chips based on FPGA as described in claim 1, which is characterized in that the step
(3) include FFT unit realize AD unit sampling data Fast Fourier Transform (FFT), frequency measurement, virtual value calculate and power meter
It calculates, wherein FFT unit calculates the fundamental wave of the every cycle in every channel and the amplitude of 15 subharmonic, and fundamental wave is hardware protection algorithm unit
Real-time data input is provided, harmonic wave is used for power quality analysis.
4. a kind of more principle relay protection chips based on FPGA as claimed in claim 3, which is characterized in that the virtual value
Extraction of square root operation in calculating uses look-up table, realizes the efficient utilization of hardware resource, every cycle 20ms each to every channel 32
Point carries out FFT unit calculating, totally 16 channels, i.e., every cycle completes 512 points of FFT unit, and clock frequency uses 12MHz.
5. a kind of more principle relay protection chips based on FPGA as described in claim 1, which is characterized in that the hardware package
Shield algorithm unit by defencive function throw move back control selections starting defencive function module, according to the calculated result of FFT unit with
It is compared, is carried out by the logic function of each defencive function module corresponding with the definite value in Electrically Erasable Programmable Read-Only Memory
Protection act, output protection action value, alarm signal and SOE event, and fixed value modification, defencive function throwing move back work and SOE
The transmission of event is controlled by MCU module.
6. a kind of more principle relay protection chips based on FPGA as described in claim 1, which is characterized in that the step
It (5) include by the operation result real-time transmission of FFT unit, measuring unit and hardware protection algorithm unit to data buffer zone, number
According to buffer area for realizing the arrangement and output of event queue SOE, while data friendship is carried out with dispatch control unit in MCU module
Mutually.
7. a kind of more principle relay protection chips based on FPGA as described in claim 1, which is characterized in that the step
(6) include that relay action signal is sent to output control unit by data buffer zone, be transmitted to relay through output control unit
Device output port；Simultaneously data buffer zone data by dispatch control unit in MCU module control, complete MCU module with
The data communication of FPGA.
8. a kind of more principle relay protection chips based on FPGA as claimed in claim 7, which is characterized in that the FPGA with
The communication of MCU module realizes effective scheduling of process using simultaneously and concurrently bus protocol on the protocol basis, scheduling into
Journey comprising protection algorism throwing move back control, switching value, electricity, virtual value, performance number, frequency values, definite value, breaker control,
Higher hamonic wave value and SOE event.
9. a kind of more principle relay protection chips based on FPGA as described in claim 1, which is characterized in that the step
(7) include that MCU module interacts related control data and dispatch control unit, by EEPROM, liquid crystal display, keyboard and
RS485 completes the communication with peripheral hardware, and the EEPROM reads control word for MCU module, and liquid crystal is for showing, keyboard is for defeated
Enter, RS485 is for communication with the outside.
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| KR20060134399A (en) * | 2005-06-22 | 2006-12-28 | 민영인버터(주) | Voltage source supplier with surge filtering function |
| CN101021721A (en) * | 2007-01-26 | 2007-08-22 | 西安交通大学 | Three-bus structure-based intelligent monitoring unit special integrated circuit |
| CN101162479A (en) * | 2007-11-06 | 2008-04-16 | 西安交通大学 | Design method of electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20060134399A (en) * | 2005-06-22 | 2006-12-28 | 민영인버터(주) | Voltage source supplier with surge filtering function |
| CN101021721A (en) * | 2007-01-26 | 2007-08-22 | 西安交通大学 | Three-bus structure-based intelligent monitoring unit special integrated circuit |
| CN101162479A (en) * | 2007-11-06 | 2008-04-16 | 西安交通大学 | Design method of electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology |
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