CN205407785U - A multiloop analog quantity synchronous sampling circuit for metering device - Google Patents
A multiloop analog quantity synchronous sampling circuit for metering device Download PDFInfo
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- CN205407785U CN205407785U CN201620161299.3U CN201620161299U CN205407785U CN 205407785 U CN205407785 U CN 205407785U CN 201620161299 U CN201620161299 U CN 201620161299U CN 205407785 U CN205407785 U CN 205407785U
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Abstract
The utility model provides a multiloop analog quantity synchronous sampling circuit for metering device, including AD conversion chip, controller and FPGA, the CONV signal end of AD conversion chip, CS signal end, BUSY signal end link to each other with FPGA's IO port, DATA signal end links to each other with the DATA signal end of controller, and CLK signal end links to each other with the CLK signal end of controller, FPGA's IO pin, the INT signal end of controller links to each other with FPGA's IO pin. The utility model discloses owing to adopted the controller that has the DMA passageway to increased FPGA and carry out the control of data sampling and transmission between controller and AD conversion chip, therefore do not needed the core operating program of controller and other hardware resource to participate in in data sampling and transmission course, reduced the resource cost of controller, makeed the controller operation more reliable and more stable, the sampling rate is higher, and the real -time is better.
Description
Technical field
This utility model is specifically related to a kind of multiloop analog quantity synchronized sampling circuit for measuring instrument.
Background technology
Along with the raising of the development of national economy technology and people's living standard, measuring instrument has become as energy supplying system, such as power system, water system, heating system, air supply system etc., important metering outfit.The quality of measuring instrument performance, directly influences the order of accuarcy of metering.
Along with the development of smart electronics, intelligent and electronization has had become as the developing direction of measuring instrument.Intelligent electronic-type measuring instrument, because of advantages such as its measuring accuracy height, accurate measurements, has progressively replaced existing mechanical type measuring instrument.
Metering object is sampled by Intelligent electronic-type measuring instrument by sample circuit, incoming for sampled data control module is measured after then passing through AD conversion.But, existing multiloop analog quantity synchronized sampling circuit, by controller, all of AD conversion chip carried out simultaneously controlling of sampling, after AD conversion chip completes analog digital conversion, controller needs one by one AD conversion chip to be successively read sampled data, operates each time and all needs to take certain controller resource.AD conversion chip is more many, needed for the controller resource that takies more many, make controller cannot timely respond to the application request of other resources.Particularly run the controller of operating system, because of task priority and round-robin, cause that response time delay is more serious, it is difficult to meet the requirement of multiloop synchronized sampling real-time.
Utility model content
The purpose of this utility model is in that providing a kind of takies the multiloop analog quantity synchronized sampling circuit for measuring instrument that controller resource is less, data sampling disposal ability high, real-time is good.
This multiloop analog quantity synchronized sampling circuit for measuring instrument that this utility model provides, including N sheet AD conversion chip and controller, N is positive integer, also includes FPGA；The CONV signal end of described AD conversion chip, CS signal end, BUSY signal end are connected with the I/O port of described FPGA；DATA signal end is connected with the DATA signal end of described controller, and CLK signal end is connected with the I/O pin of the CLK signal end of controller, FPGA；The INT signal end of controller is connected with the I/O pin of described FPGA.
Described controller is the controller with DMA channel.
Described controller model is TMS320C67.
This multiloop analog quantity synchronized sampling circuit for measuring instrument that this utility model provides, owing to have employed the controller with DMA channel, and the interrupt signal adding the extra control chip FPGA selection and controller being AD converted chip between controller and AD conversion chip sends, therefore this utility model is in data sampling and transmitting procedure, controller is not involved in the controlling of sampling of AD conversion chip, is only involved in data receiver；In data transmission procedure, DMA channel is automatically performed and data is carried to memory field, it is not necessary to the core of controller runs program and other hardware resources participate in, greatly reduce the resource overhead of controller, controller being run more reliable and more stable, and sampling rate is higher, real-time is better.
Accompanying drawing explanation
Fig. 1 is functional block diagram of the present utility model.
Detailed description of the invention
It is illustrated in figure 1 functional block diagram of the present utility model: this multiloop analog quantity synchronized sampling circuit for measuring instrument that this utility model provides, including controller, FPGA and some AD conversion chip；The CONV signal end of wherein said AD conversion chip, CS signal end, BUSY signal end stop with the I/O of described FPGA and are connected；DATA signal end is connected with the DATA signal end of described controller, and CLK signal end is connected with the CLK signal end of controller and the I/O port of FPGA；The INT signal end of controller is connected with the I/O port of described FPGA；Controller is the controller with DMA channel, concrete, it is possible to adopting model is the controller of TMS320C67.
Claims (3)
1., for a multiloop analog quantity synchronized sampling circuit for measuring instrument, including N sheet AD conversion chip and controller, N is positive integer, it is characterised in that also include FPGA；The CONV signal end of described AD conversion chip, CS signal end, BUSY signal end are connected with the I/O port of described FPGA；DATA signal end is connected with the DATA signal end of described controller, and CLK signal end is connected with the I/O pin of the CLK signal end of controller, FPGA；The INT signal end of controller is connected with the I/O pin of described FPGA.
2. the multiloop analog quantity synchronized sampling circuit for measuring instrument according to claim 1, it is characterised in that described controller is the controller with DMA channel.
3. the multiloop analog quantity synchronized sampling circuit for measuring instrument according to claim 1 and 2, it is characterised in that described controller model is TMS320C67.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620161299.3U CN205407785U (en) | 2016-03-03 | 2016-03-03 | A multiloop analog quantity synchronous sampling circuit for metering device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620161299.3U CN205407785U (en) | 2016-03-03 | 2016-03-03 | A multiloop analog quantity synchronous sampling circuit for metering device |
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| Publication Number | Publication Date |
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| CN205407785U true CN205407785U (en) | 2016-07-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201620161299.3U Active CN205407785U (en) | 2016-03-03 | 2016-03-03 | A multiloop analog quantity synchronous sampling circuit for metering device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3543860A1 (en) * | 2018-03-23 | 2019-09-25 | Hamilton Sundstrand Corporation | System to acquire analog to digital (adc) data using high end timer (n2het) and high end timer transfer unit (htu) |
-
2016
- 2016-03-03 CN CN201620161299.3U patent/CN205407785U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3543860A1 (en) * | 2018-03-23 | 2019-09-25 | Hamilton Sundstrand Corporation | System to acquire analog to digital (adc) data using high end timer (n2het) and high end timer transfer unit (htu) |
| US10628077B2 (en) | 2018-03-23 | 2020-04-21 | Hamilton Sundstrand Corporation | System to acquire analog to digital (ADC) data using high end timer (N2HET) and high end timer transfer unit (HTU) |
| EP4123464A1 (en) * | 2018-03-23 | 2023-01-25 | Hamilton Sundstrand Corporation | System to acquire analog to digital (adc) data using high end timer (n2het) and high end timer transfer unit (htu) |
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| C14 | Grant of patent or utility model | ||
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Address after: 410205 No. 468 west slope, Changsha hi tech Industrial Development Zone, Changsha, Hunan, Yuelu District, Tongzi Patentee after: WILLFAR INFORMATION TECHNOLOGY Co.,Ltd. Address before: 410205 No. 468 west slope, Changsha hi tech Industrial Development Zone, Changsha, Hunan, Yuelu District, Tongzi Patentee before: HUNAN WEISHENG INFORMATION TECHNOLOGY CO.,LTD. Address after: 410205 No. 468 west slope, Changsha hi tech Industrial Development Zone, Changsha, Hunan, Yuelu District, Tongzi Patentee after: HUNAN WEISHENG INFORMATION TECHNOLOGY CO.,LTD. Address before: 410205 No. 468 west slope, Changsha hi tech Industrial Development Zone, Changsha, Hunan, Yuelu District, Tongzi Patentee before: CHANGSHA WASION INFORMATION TECHNOLOGY Co.,Ltd. |