CN105668502B - The level Hermetic Package structure and its manufacture method of a kind of attached cavity device - Google Patents
The level Hermetic Package structure and its manufacture method of a kind of attached cavity device Download PDFInfo
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- CN105668502B CN105668502B CN201610174128.9A CN201610174128A CN105668502B CN 105668502 B CN105668502 B CN 105668502B CN 201610174128 A CN201610174128 A CN 201610174128A CN 105668502 B CN105668502 B CN 105668502B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The invention discloses a kind of level Hermetic Package structure of attached cavity device and its manufacture method, the level Hermetic Package structure includes：First semiconductor wafer and the second semiconductor wafer, each semiconductor wafer include first surface, the second surface relative with the first surface；Binder bonded layer, it is used to the first surface of the first surface of the first semiconductor wafer and the second semiconductor wafer being bonded together；Multiple cavities, it surround sealing by binder bonded layer respectively between the first semiconductor wafer and the first surface of the second semiconductor wafer；Multiple grooves on the outside of cavity, groove at least run through the first semiconductor wafer and binder bonded layer from the second surface of the first semiconductor wafer, and multiple grooves are respectively around cavity；Plastic packaging material encapsulated member, its second surface filled groove and cover the first semiconductor wafer.Compared with prior art, the present invention can realize good air-tightness, so as to obtain the device of high reliability.
Description
【Technical field】
The present invention relates to technical field of semiconductor encapsulation, the level Hermetic Package structure of more particularly to a kind of attached cavity device and its
Manufacture method.
【Background technology】
Many micro-electromechanical system (MEMS) (Micro-Electro Mechanical System) devices have movable member,
This just needs to provide cavity (Cavity) environment, is essentially all to pass through wafer bonding in wafer-level packaging
(bonding) realize.In various bonding patterns, binder is bonded because the low characteristic of its technological temperature is able to extensive use,
But its bonding material of itself is macromolecule organic, and often air-tightness, waterproof and dampproof etc. are limited in one's ability, can not finally obtain height
The device of reliability.
Therefore, it is necessary to a kind of improved plan is proposed to overcome above mentioned problem.
【The content of the invention】
An object of the present invention is the level Hermetic Package structure and its manufacture method for providing a kind of attached cavity device, and it can
To realize good air-tightness, so as to obtain the device of high reliability.
In order to solve the above problems, according to an aspect of the present invention, the present invention provides a kind of the airtight of attached cavity device
Encapsulating structure, it includes：First semiconductor wafer, it includes first surface, the second surface relative with the first surface：Second
Semiconductor wafer, it includes first surface, the second surface relative with the first surface；Binder bonded layer, it is located at first
Between the first surface of semiconductor wafer and the second semiconductor wafer, the binder bonded layer is used for the first semiconductor wafer
First surface and the first surface of the second semiconductor wafer be bonded together；Multiple cavities, it is located at the first semiconductor wafer
And second semiconductor wafer first surface between, and respectively by the binder bonded layer around sealing；It is multiple positioned at described
Groove on the outside of cavity, the groove are at least justified from the second surface of first semiconductor wafer through first semiconductor
Piece and binder bonded layer, the multiple groove is respectively around the cavity；Plastic packaging material encapsulated member, it is filled the groove and covered
The second surface of the semiconductor wafer of lid first.
Further, the level Hermetic Package structure also includes redistribution layer, and the redistribution layer is by the first semiconductor wafer
And/or the second circuit signal on semiconductor wafer leads to the output port on the plastic packaging material encapsulated member surface.
Further, the groove sequentially passes through first semiconductor wafer and binder bonded layer to described the second half
The first surface of conductor disk；Or the groove sequentially passes through first semiconductor wafer and adhesive bonds layer, and prolong
In life to second semiconductor wafer.
Further, the side wall of the groove is inclined design or vertical design；The groove can be cut by blade,
At least one of laser cutting, dry etching and wet etching technique is formed.
Further, at least one MEMS circuit modules are located at the first surface of semiconductor wafer.
Further, the binder bonded layer include epoxy resin, silicon nitride, silica, silicon oxynitride, soldering-resistance layer,
At least one of polyimides, benzocyclobutene (BCB), Parylene, poly- naphthalene, fluorocarbon and acrylate.
According to another aspect of the present invention, the present invention provides a kind of manufacturer of the level Hermetic Package structure of attached cavity device
Method, it includes：First semiconductor wafer and the second semiconductor wafer are provided, wherein, each semiconductor wafer includes the first table
Face and the second surface relative with the first surface；Align the first semiconductor wafer and the second semiconductor wafer, passes through binder
The first surface of the first surface of first semiconductor wafer and the second semiconductor wafer is bonded by bonded layer, wherein, the first half
Multiple cavities are formed between the first surface of conductor disk and the second semiconductor wafer, the cavity is respectively by described adhesive key
Layer is closed around sealing；Multiple grooves, institute are opened up from the second surface of first semiconductor wafer and on the outside of the cavity
State groove and at least run through first semiconductor wafer and binder bonded layer, the multiple groove is respectively around the cavity；
Plastic packaging is carried out to the second surface of first semiconductor wafer, to form plastic packaging material encapsulated member, the plastic packaging material encapsulated member is filled out
Fill the groove and cover the second surface of first semiconductor wafer.
Further, the preparation method also includes：Redistribution layer is formed, the redistribution layer is by the first semiconductor wafer
And/or the second circuit signal on semiconductor wafer leads to the output port on the plastic packaging material encapsulated member surface.
Further, the second surface from first semiconductor wafer and opened up on the outside of the cavity multiple
Trench step is to be opened up from the second surface of first semiconductor wafer and sequentially pass through first semiconductor wafer and bonding
Agent bonded layer to the surface of second semiconductor wafer groove；Or the second surface from first semiconductor wafer
And it is to open up from the second surface of first semiconductor wafer and pass through successively to open up multiple trench steps on the outside of the cavity
Wear first semiconductor wafer and binder bonded layer, and the groove extended in second semiconductor wafer.
Further, the side wall of the groove is inclined design or vertical design；The groove can be cut by blade,
At least one of laser cutting, dry etching and wet etching technique is formed.
Further, at least one MEMS circuit modules are located at the first surface of semiconductor wafer.
Compared with prior art, the present invention uses generally applicable binder bonding techniques and wafer-level packaging technique, leads to
The mode that the binder bonded layer cut-out between wafer is refilled plastic packaging material and encapsulated is crossed, utilizes the excellent properties of plastic packaging material
Good air-tightness is realized, so as to obtain the device of high reliability.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these accompanying drawings other
Accompanying drawing.Wherein：
Fig. 1 is the schematic flow sheet of the manufacture method of the level Hermetic Package structure in the present invention in one embodiment；
Fig. 2 is the overall knot of the first semiconductor wafer that the present invention provides in one embodiment and the second semiconductor wafer
Structure schematic diagram；
Fig. 3 for the present invention in one embodiment, after aliging and being bonded the first semiconductor wafer and the second semiconductor wafer
Level Hermetic Package structure overall structure diagram；
Fig. 4 is the partial longitudinal section figure of level Hermetic Package structure in one embodiment shown in Fig. 3；
Fig. 5 for the present invention in one embodiment, from after the second surface of first semiconductor wafer opens up groove
The overall structure diagram of level Hermetic Package structure；
Fig. 6 a and Fig. 6 b are partial longitudinal section figure of the level Hermetic Package structure in two different embodiments shown in Fig. 5；
Fig. 7 for the present invention in one embodiment, from after the second surface 212 of the first semiconductor wafer 210 carries out plastic packaging
Level Hermetic Package structure overall structure diagram；
Fig. 8 a and Fig. 8 b are partial longitudinal section figure of the level Hermetic Package structure in two different embodiments shown in Fig. 7；
Fig. 9 for the present invention in one embodiment, illustrate by the overall structure of the level Hermetic Package structure formed after redistribution layer
Figure；
Figure 10 is the partial longitudinal section figure of level Hermetic Package structure in one embodiment shown in Fig. 9；
Figure 11 is the schematic diagram after carrying out scribing cutting with cutting blade to the level Hermetic Package structure shown in Fig. 9.
【Embodiment】
The detailed description of the present invention is mainly by program, step, logical block, process or other symbolistic descriptions come directly
Or the running of simulation technical solution of the present invention indirectly.For the thorough explanation present invention, set forth very in following description
More specific details.And in these specific details, it is of the invention then can still may realize.Technical staff in art makes
With these descriptions herein and state that the others skilled in the art into art effectively introduce their work essence.Change sentence
Talk about, for the purpose of the present invention of avoiding confusion, because well known methods and procedures has been readily appreciated that, therefore they are not detailed
Thin description.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the present invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.It is common in art
Technical staff is it is well known that the expression such as be connected, connect or connect in the present invention is directly or indirectly electrically connected with.
Refer to shown in Fig. 1, its for the level Hermetic Package structure in the present invention manufacture method 100 in one embodiment
Schematic flow sheet.The manufacture method 100 comprises the following steps.
Step 110, as shown in Figure 2, there is provided the first semiconductor wafer 210 and the second semiconductor wafer 220.Each semiconductor
Disk includes first surface 212,222, the second surface 214,224 relative with the first surface 212,222, at least one MEMS
Circuit module is located at the first surface 212,222 of semiconductor wafer 210,220, and the first surface of at least one semiconductor wafer is set
It is equipped with groove.In the embodiment shown in Figure 2, with reference to shown in Fig. 4, the first surface 212 of the first semiconductor wafer 210 and
Multiple grooves 2301 are provided with the first surface 222 of two semiconductor wafers 220.Wherein, Fig. 2 is the present invention in an implementation
The first semiconductor wafer 210 and the overall structure diagram of the second semiconductor wafer 220 provided in example.
Step 120, as shown in Figure 3 and Figure 4, align the first semiconductor wafer 210 and the second semiconductor wafer 220, passes through
Binder bonded layer 240 is by the first surface of the semiconductor wafer 220 of first surface 212 and second of the first semiconductor wafer 210
222 bondings, to form the bonding wafers for including the first semiconductor wafer 210 and the second semiconductor wafer 220.Align and be bonded
Afterwards, formed between the first surface 222 of the semiconductor wafer 220 of first surface 212 and second of the first semiconductor wafer 210 more
Individual cavity 230, and the cavity 230 is sealed respectively by the binder bonded layer 240.In one embodiment, the cavity
230 be vacuum；Or gaseous material is filled with the cavity 230, the pressure in the cavity 230 is 1bar to 10bar.
Wherein, Fig. 3 for the present invention in one embodiment, align and be bonded the first semiconductor wafer 210 and the second half and lead
The overall structure diagram of level Hermetic Package structure after body disk 220；Fig. 4 is the level Hermetic Package structure shown in Fig. 3 in a reality
Apply the partial longitudinal section figure in example.In the embodiment shown in fig. 4, it is simply exemplary to show a cavity 230, other chambers
Body does not show that.
Step 130, as shown in Fig. 5, Fig. 6 a and Fig. 6 b, second surface 212 and position from first semiconductor wafer 210
Multiple grooves 250 are opened up in the outside of cavity 230, the groove 250 at least through first semiconductor wafer 210 and sticks
Mixture bonded layer 240, the multiple groove 250 is respectively around the cavity 230.The groove 250 can be cut by blade,
At least one of laser cutting, dry etching and wet etching technique is formed.
Refer to shown in Fig. 5, its for the present invention in one embodiment, from the second of first semiconductor wafer 210
Surface 214 opens up the overall structure diagram of the level Hermetic Package structure after groove 250, in the embodiment shown in fig. 5, alignment key
After conjunction, the cavity 230 between the first surface of the first semiconductor wafer 210 and the second semiconductor wafer 220 is in rectangular
Formula is arranged, the second surface 214 using groove cutting blade 300 from first semiconductor wafer 210, in adjacent rows cavity
Between, between adjacent two row cavity, and outermost row cavity on the outside of, and outermost row cavity on the outside of carry out groove cutting so that
Each cavity is surround by four its immediate grooves 250.
It refer to shown in Fig. 6 a and Fig. 6 b, it is portion of the level Hermetic Package structure in two different embodiments shown in Fig. 5
Divide profilograph.In the embodiment shown in Fig. 6 a, groove 250a sequentially passes through first semiconductor wafer 210 and binder
Bonded layer 240 to second semiconductor wafer 220 first surface 222.In the embodiment shown in Fig. 6 b, groove 250b according to
It is secondary to run through first semiconductor wafer 210 and binder bonded layer 240, and extend in second semiconductor wafer 220.
In the embodiment shown in Fig. 6 a and Fig. 6 b, groove 250a and 250b side wall is tilt (slope) design, in other embodiment
In, groove 250a and 250b side wall can also be that vertical (straight wall) designs.
Step 140, as shown in Fig. 7, Fig. 8 a and Fig. 8 b, the second surface 212 of first semiconductor wafer 210 is carried out
Plastic packaging, to form plastic packaging material encapsulated member 260, the plastic packaging material encapsulated member 260 fills the groove 250 and covers described the first half
The second surface 214 of conductor disk 210.So, binder bonded layer 240 is typically entrapped within the plastic packaging material encapsulated member 260, is not revealed
Outside for the plastic packaging material encapsulated member 260, so that cavity 230 realizes more preferable air-tightness, so as to obtain the device of high reliability
Part.
Wherein, Fig. 7 for the present invention in one embodiment, moulded from the second surface 212 of the first semiconductor wafer 210
The overall structure diagram for the level Hermetic Package structure being honored as a queen.It refer to shown in Fig. 8 a and Fig. 8 b, it is the level Hermetic Package shown in Fig. 7
Partial longitudinal section figure of the structure in two different embodiments.In the embodiment shown in Fig. 8 a, the plastic packaging material encapsulated member
260a fills the groove 250a and covers the second surface 214 of first semiconductor wafer 210；In the implementation shown in Fig. 8 b
In example, the plastic packaging material encapsulated member 260b fills the groove 250b and covers the second table of first semiconductor wafer 210
Face 214.Wherein, the concrete structure about groove 250a and 250b refers to the foregoing description to groove 250a, 250b.
Due in foregoing statement it is stated that, on the first surface 212,222 of the semiconductor wafer 210,220 in the present invention
At least one MEMS circuit module, therefore, encapsulate electrical connection formation comprise at least the first semiconductor wafer 210 and/or
The design that circuit signal on second semiconductor wafer 220 is led to outside plastic packaging, specifically refers to following step 150.
Step 150, as shown in Figure 9 and Figure 10, forms redistribution layer RDL (not shown), and the redistribution layer is by the first half
Circuit signal on the semiconductor wafer 220 of conductor disk 210 and/or second leads to the output end on the surface of plastic packaging material encapsulated member 260
Mouth 270, the output port 270 can be soldered ball or the weld pad without pin.Wherein, Fig. 9 for the present invention in one embodiment,
The overall structure diagram of the level Hermetic Package structure formed after redistribution layer；Figure 10 is the level Hermetic Package structure shown in Fig. 9 one
Partial longitudinal section figure in individual embodiment, in the embodiment shown in fig. 10, the output port 270 are soldered ball.
Scribing cutting then is carried out to level Hermetic Package structure made from manufacture method as shown in Figure 1, to obtain single core
Piece, it is specific shown in Figure 11, after it is carries out scribing cutting to the level Hermetic Package structure shown in Fig. 9 with cutting blade 330
Schematic diagram.
In one embodiment, the binder bonded layer 240 can include epoxy resin, silicon nitride, silica, nitrogen oxygen
In SiClx, soldering-resistance layer, polyimides, benzocyclobutene (BCB), Parylene, poly- naphthalene, fluorocarbon and acrylate
It is at least one；The material of the semiconductor wafer 210,220 can include Glass, Si, Ge, GaAs, InP, GaN, Al2O3,
At least one of Cu, Al, KOVAR；
According to another aspect of the present invention, the present invention provides a kind of level Hermetic Package structure.
It refer to shown in Fig. 9 and Figure 10, the level Hermetic Package structure in the present invention includes the first semiconductor wafer 210, with the
The second semiconductor wafer 220, multiple cavities 230, binder bonded layer 240, the multiple grooves of the bonding of semiconductor disk 210
250a and plastic packaging material encapsulated member 260.
First semiconductor wafer 210 includes first surface 212, the second surface relative with the first surface 212
214；Second semiconductor wafer 220 includes first surface 222, the second surface 224 relative with the first surface 222；Institute
State the first surface 222 that cavity 230 is formed at the semiconductor wafer 220 of first surface 212 and second of the first semiconductor wafer 210
Between；The binder bonded layer 240 is sandwiched in the semiconductor wafer 220 of first surface 212 and second of the first semiconductor wafer 210
First surface 222 between, the binder bonded layer 240 seals the cavity 230 respectively；At least one MEMS circuit modules
Positioned at the first surface 212,222 of semiconductor wafer 210,220.
In the embodiment shown in fig. 10, on first surface 212 of the cavity 230 by the first semiconductor wafer 210
Corresponding groove 2301, which fastens, on the first surface 222 of the semiconductor wafer 220 of groove 2301 and second forms；In the another of the present invention
In one embodiment, the cavity 230 can be by (part of part first surface 212 of first semiconductor wafer 210
Groove 2301 is not formed on one surface 212) fastened with the groove 2301 of the first surface 222 of second semiconductor wafer 220
Formed；In further embodiment in the present invention, the cavity 230 can be by the first of first semiconductor wafer 210
The part first surface 222 of the groove 2301 on surface 212 and second semiconductor wafer 220 is (on the part first surface 222
Groove 2301 is not formed fastens formation.
Multiple groove 250a are located at the outside of the cavity 230, and the groove 250a is from first semiconductor wafer
210 second surface 214 is at least bonded to 240 through first semiconductor wafer 210 and binder, the multiple groove
250a is respectively around the cavity 230.In the embodiment shown in fig. 10, the groove 250a sequentially passes through described the first half and led
Body disk 210 and binder bonded layer 240 to second semiconductor wafer 220 first surface 222；In the reality shown in Fig. 8 b
Apply in example, groove 250b sequentially passes through first semiconductor wafer 210 and binder bonded layer 240, and extends to described
In two semiconductor wafers 220.
The plastic packaging material encapsulated member 260 fills the groove 250a and covers the second of first semiconductor wafer 210
Surface 214.So, binder bonded layer 240 is typically entrapped within the plastic packaging material encapsulated member 260, is not exposed to the plastic packaging material bag
Seal outside body 260, so that cavity 230 realizes more preferable air-tightness, so as to obtain the device of high reliability.
In the embodiment shown in Fig. 9 and Figure 10, the level Hermetic Package structure in the present invention also includes redistribution layer RDL (not
Show), the redistribution layer leads to the circuit signal on the first semiconductor wafer 210 and/or the second semiconductor wafer 220
The output port 270 on the surface of plastic packaging material encapsulated member 260, the output port 270 can be soldered ball or the weld pad without pin, scheme
In embodiment shown in 10, the output port 270 is soldered ball.
Described above has fully disclosed the embodiment of the present invention.It is pointed out that it is familiar with the field
Scope of the technical staff to any change that the embodiment of the present invention is done all without departing from claims of the present invention.
Correspondingly, the scope of claim of the invention is also not limited only to previous embodiment.
Claims (4)
1. a kind of manufacture method of the level Hermetic Package structure of attached cavity device, it is characterised in that it includes：
First semiconductor wafer and the second semiconductor wafer are provided, wherein, each semiconductor wafer include first surface and with
The relative second surface of the first surface；
Align the first semiconductor wafer and the second semiconductor wafer, by binder bonded layer by the first of the first semiconductor wafer
The first surface of surface and the second semiconductor wafer is bonded, wherein, the of the first semiconductor wafer and the second semiconductor wafer
Multiple cavities are formed between one surface, the cavity is respectively by the binder bonded layer around sealing；
Multiple grooves are opened up from the second surface of first semiconductor wafer and on the outside of the cavity, the groove runs through
First semiconductor wafer and binder bonded layer, and extend in second semiconductor wafer, the multiple groove point
Cavity described in other continued circling, cut, be cut by laser by blade from the second surface of first semiconductor wafer, dry method is carved
At least one of erosion and wet etching technique form the groove；
Plastic packaging is carried out to the second surface of first semiconductor wafer, to form plastic packaging material encapsulated member, the plastic packaging material encapsulating
Body fills the groove and covers the second surface of first semiconductor wafer.
2. manufacture method according to claim 1, it is characterised in that it also includes：
Redistribution layer is formed, the redistribution layer is by the circuit signal on the first semiconductor wafer and/or the second semiconductor wafer
Lead to the output port on the plastic packaging material encapsulated member surface.
3. manufacture method according to claim 1, it is characterised in that
The side wall of the groove is inclined design or vertical design；
The groove can be cut by blade, is cut by laser, at least one of dry etching and wet etching technique are formed.
4. manufacture method according to claim 1, it is characterised in that
At least one MEMS circuit modules are located at the first surface of semiconductor wafer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610174128.9A CN105668502B (en) | 2016-03-24 | 2016-03-24 | The level Hermetic Package structure and its manufacture method of a kind of attached cavity device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610174128.9A CN105668502B (en) | 2016-03-24 | 2016-03-24 | The level Hermetic Package structure and its manufacture method of a kind of attached cavity device |
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| CN105668502B true CN105668502B (en) | 2017-12-15 |
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| CN110562911A (en) * | 2019-09-18 | 2019-12-13 | 北京理工大学 | Micro-nano structure forming and manufacturing method using supporting layer |
| CN113816331A (en) * | 2021-10-09 | 2021-12-21 | 美新半导体（无锡）有限公司 | Airtight packaging structure of device with cavity |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3496347B2 (en) * | 1995-07-13 | 2004-02-09 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| WO2000028589A1 (en) * | 1998-11-06 | 2000-05-18 | Festec Co., Ltd. | A plastic package having an air cavity and manufacturing method thereof |
| TW560018B (en) * | 2001-10-30 | 2003-11-01 | Asia Pacific Microsystems Inc | A wafer level packaged structure and method for manufacturing the same |
| JP2008130701A (en) * | 2006-11-20 | 2008-06-05 | Matsushita Electric Ind Co Ltd | Wiring substrate, semiconductor device using the substrate, and method of manufacturing the semiconductor device |
| US8900931B2 (en) * | 2007-12-26 | 2014-12-02 | Skyworks Solutions, Inc. | In-situ cavity integrated circuit package |
| TWI455266B (en) * | 2010-12-17 | 2014-10-01 | 矽品精密工業股份有限公司 | Package structure having micro-electro-mechanical elements and manufacturing method thereof |
| US9403674B2 (en) * | 2014-08-12 | 2016-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for packaging a microelectromechanical system (MEMS) wafer and application-specific integrated circuit (ASIC) dies using through mold vias (TMVs) |
| CN204424241U (en) * | 2015-02-10 | 2015-06-24 | 华天科技（昆山）电子有限公司 | The chip package structure of belt edge stress transfer and wafer level chip encapsulating structure |
| CN105174195A (en) * | 2015-10-12 | 2015-12-23 | 美新半导体（无锡）有限公司 | WLP (wafer-level packaging) structure and method for cavity MEMS (micro-electromechanical system) device |
| CN205398103U (en) * | 2016-03-24 | 2016-07-27 | 美新半导体（无锡）有限公司 | Take airtight packaging structure of cavity device |
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