CN105490883A - 1553B bus monitoring circuit based on Ethernet interface - Google Patents
1553B bus monitoring circuit based on Ethernet interface Download PDFInfo
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- CN105490883A CN105490883A CN201510924316.4A CN201510924316A CN105490883A CN 105490883 A CN105490883 A CN 105490883A CN 201510924316 A CN201510924316 A CN 201510924316A CN 105490883 A CN105490883 A CN 105490883A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
Abstract
The invention relates to a 1553B bus monitoring circuit based on an Ethernet interface. The 1553B bus monitoring circuit comprises the Ethernet interface, a 1553B bus interface module, an external memory controller (EBC) module, a clock and reset module, a JTAG module and a power supply module, wherein the JTAG interface module is used for providing a JTAG function for regulating and controlling on-chip debugging of the 1553B bus interface module and the Ethernet interface; the power supply module is used for supplying work voltages to the 1553B bus interface module and the Ethernet interface; and the EBC module controls data transceiving between the 1553B bus interface module and an 1553B bus and communication between the Ethernet interface and a host. The 1553B bus monitoring circuit based on the Ethernet interface supports a BC/RT/MT function and completes system monitoring.
Description
Technical field
The invention belongs to technical field of circuit design, particularly relate to the 1553B bus monitoring circuit based on Ethernet interface.
Background technology
The design of SoC from whole system performance requirement, will combine microprocessor, bus protocol, chip structure, each layered electronic circuit module of peripheral components closely, and by system-level Hardware/Software Collaborative Design, realizes system-level function on a single chip.
Based on the 1553B bus monitoring circuit of Ethernet interface, from the angle of 1553B bus system application, it has low energy consumption, small size, systemic-function is enriched, the feature such as high-performance and low cost, the 1553B bus monitoring system of Ethernet interface and control method mainly adopt the HKS289BRM chip design from grinding, from hardware aspect, decrease the pressure of distributing, make the area of module, weight, power consumption reduces greatly, abundanter from the internal resource of SoC software aspect, the function realized is abundanter, especially a big chunk software function of bearing of sheet inner treater, decrease host process pressure, on the whole, the circuit of SoC design is adopted more to meet the demand of system, performance is significantly improved.
Summary of the invention
The invention provides the 1553B bus monitoring circuit based on Ethernet interface, in order to realize the BC/RT/MT function in 1553B bus, for bus system provides application solution.
Technical solution of the present invention:
Based on the 1553B bus monitoring circuit of Ethernet interface, its special character is,
Ethernet interface, 1553B bus interface module, external storage controller (EBC) module, clock and reseting module, JTAG module and power module;
1553B bus interface module comprises MT memory, BCRT memory, MT protocol processor, 1553BCRT protocol processor, 1553B two-way transceiver, network clocking controller, a passage transformer and two passage transformers;
One passage transformer is connected with 1553B bus by transformer coupled mode with one end of two passage transformers, one passage transformer is connected with one end of 1553B two-way transceiver with the other end of two passage transformers, the other end of 1553B two-way transceiver is connected with MT protocol processor and 1553BCRT protocol processor, the 1553B data buffer storage of 1553BCRT protocol processor is in BCRT memory, the 1553B data buffer storage of MT protocol processor is in MT memory, network clocking controller is connected with 553BCRT protocol processor, for 1553B bus provides synchronised clock;
Ethernet interface comprises Ethernet transformer, ethernet PHY and Ethernet protocol processing unit;
One end of Ethernet transformer is connected with main frame by netting twine, the other end of Ethernet transformer is connected with ethernet PHY, ethernet PHY is connected with Ethernet protocol processing unit, and Ethernet protocol processing unit sends to main frame by ethernet PHY and Ethernet transformer after being used for reading 1553B data from MT memory and BCRT memory; The 1553B data conversion storage sent by main frame is in BCRT memory; Clock and reseting module provide unified clock and reset signal to 1553B bus interface module and Ethernet interface;
Described jtag interface module is used for providing JTAG function, debugs for regulating and controlling in 1553B bus interface module processed and Ethernet interface sheet;
Described power module is used for providing operating voltage to 1553B bus interface module and Ethernet interface;
Data transmit-receive between external storage controller (EBC) module controls 1553B bus interface module and 1553B bus and the communication of Ethernet interface and main frame.
The transformation ratio of above-mentioned passage one transformer and passage two transformer can regulate.
The transmission rate of MT reconnaissance protocol processor, 1553BCRT protocol processor is 1MHz or 2MHz.
The advantageous effect that the present invention has:
The invention provides the 1553B bus monitoring circuit based on Ethernet interface, have employed Ethernet interface and meet host interface demand, 1553B bus interface realizes having the BC/RT/MT specified in 1553B, support the mechanism that BC/MT, RT/MT work simultaneously simultaneously, the external storage controller storage resources abundant for chip provides, whole design provide and monitor 1553B bus system, evaluation and test, analyze etc. function, meet the function to 1553B bus system fast detecting.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of the 1553B bus monitoring system of Ethernet interface of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is stated clearly and completely.Obviously; the embodiment stated is only the present invention's part embodiment, instead of whole embodiments, based on the embodiment in the present invention; the every other embodiment that those skilled in the art are not making creative work prerequisite and obtain, all belongs to protection scope of the present invention.
As shown in Figure 1, based on the 1553B bus monitoring circuit of Ethernet interface, comprise Ethernet interface, 1553B bus interface module, external storage controller (EBC) module, clock and reseting module, JTAG module and power module;
1553B bus interface module comprises MT memory, BCRT memory, MT protocol processor, 1553BCRT protocol processor, 1553B two-way transceiver, network clocking controller, a passage transformer and two passage transformers;
One passage transformer is connected with 1553B bus by transformer coupled mode with one end of two passage transformers, one passage transformer is connected with one end of 1553B two-way transceiver with the other end of two passage transformers, the other end of 1553B two-way transceiver is connected with MT protocol processor and 1553BCRT protocol processor, the 1553B data buffer storage of 1553BCRT protocol processor is in BCRT memory, the 1553B data buffer storage of MT protocol processor is in MT memory, network clocking controller is connected with 553BCRT protocol processor, for 1553B bus provides synchronised clock; Ethernet interface comprises Ethernet transformer, ethernet PHY and Ethernet protocol processing unit; One end of Ethernet transformer is connected with main frame by netting twine, the other end of Ethernet transformer is connected with ethernet PHY, ethernet PHY is connected with Ethernet protocol processing unit, and Ethernet protocol processing unit sends to main frame by ethernet PHY and Ethernet transformer after being used for reading 1553B data from MT memory and BCRT memory; The 1553B data conversion storage sent by main frame is in BCRT memory; Clock and reseting module provide unified clock and reset signal to 1553B bus interface module and Ethernet interface; Jtag interface module is used for providing JTAG function, debugs for regulating and controlling in 1553B bus interface module processed and Ethernet interface sheet; Power module is used for providing operating voltage to 1553B bus interface module and Ethernet interface; Data transmit-receive between external storage controller (EBC) module controls 1553B bus interface module and 1553B bus and the communication of Ethernet interface and main frame.
Passage one transformer 1 passage two transformer 2 transformation ratio can regulate.The transmission rate of MT protocol processor, 1553BCRT protocol processor is 1MHz or 2MHz.
Embodiment:
The invention provides the 1553B bus monitoring circuit based on Ethernet interface, comprise Ethernet interface, 1553B bus interface, external storage controller (EBC), clock and reset, JTAG module and power supply;
Wherein, Ethernet interface, the controlling functions such as the initialization of 1553B bus interface, startup, stopping, bus data, bus transmission, bus data monitoring are comprised, main frame is completed by Ethernet interface and records all message sources in bus and analyze, message monitoring, bus load calculate, the monitoring etc. of mistake, and main frame feeds back to user by visual interface, realizes the functions such as the evaluation and test to 1553B bus system, analysis.
Send and control, send the transmission scheduling feature that control logic mainly completes ethernet frame.Comprise frame length detect, by ethernet frame stored in transmission buffering area, clock zone conversion and control, report transmission state, sends the functions such as data dispatch.
Send the control logic DPRAM that uses size to be 16KB, be used for depositing the ethernet frame of PLB interface write.Send DPRAM and be divided into 8 fritters (every block 2KB), each fritter only allows to deposit an ethernet frame.
Receive and control, receive reception and scheduling feature that control module mainly completes ethernet frame.Comprise receive from MAC core data, by process after Frame stored in reception DPRAM in, when being cached excessive, the frame abandoned counted and be reported to protocol stack process, clock zone conversion and control, the calculating of data division School Affairs and erroneous frame such as to abandon at the function.
Receive control module and use the DPRAM that size is 16KB, be used for depositing the ethernet frame received.Receive DPRAM and be divided into 8 fritters (every block 2KB), each fritter only allows to deposit an ethernet frame, and if do not remove corresponding state, each buffer memory can repeatedly read, and these 8 spatial caches adopt the storage mode of poll.
EBC external storage controller, be specially: the test of external memory storage connects by outside the test that different memory realizes external interface, reserved 4 sheets choosing of external interface, sheet selects 0 can only connect flash storage, and bit wide is 16, other memory devices such as SRAM can not be connect, sheet selects 1 to meet 8 Flash, sheet selects 2 to select 3 to select the SRAM connecing 32 to realize complete system by wire jumper or switch with sheet, EBC_READY (external bus operation gets out signal) the signal outside of memory interface is drawn high, the read-write of external memory portion is complexing pin, realized the independent utility of read-write operation by design inverter in design.
Clock and reset circuit design, be specially: PPC_PERI_RST warm reset acquiescence outside is drawn high, and SYS_POR_ON_RST system power-on reset, realizes electrification reset by MAX706 chip, PCI_RST_OUT_N signal is that pci interface resets, and is connected to SYS_POR_ON_RST and is realized by MAX706.REF_PPC_CLK inputs the reference clock as chip of 48MHZ, and Ethernet interface provides 25MHZ clock.
Jtag interface module, is specially: design according to described mode below.
JTAG_TDO (10K pull-up), JTAG_TDI (10K pull-up), JTAG_TMS (10K pull-up), JTAG_TCK (10K pull-up), JTAG_TRST_N (10K is drop-down), DBG_HALT_N (1K pull-up);
Described power module, be specially: required voltage is by the core voltage of 1.2V, the I/O port voltage of 3.3V, the ether medium physical layer emitter/receiver of Ethernet interface aspect application DP83848YB, this chip is needing the core voltage providing 1.8V, and the core voltage of ethernet PHY chip and interface voltage adopt magnetic bead to isolate, and power supply type selecting aspect power supply exports the electric current meeting 3A.
The invention provides the 1553B bus monitoring circuit based on Ethernet interface, have employed Ethernet interface and main-machine communication, 1553B bus interface realizes having the BC/RT/MT specified in GJB289A-97, support the mechanism that BC/MT, RT/MT work simultaneously simultaneously, software provides visual interface, resolves the data message of bus intuitively.
Be specially: pass through bus transceiver, transformer and 1553B connector etc. realize 1553B bus interface function, bus transceiver can receive the BUS signal from bus, through isolation, HKS289BRM chip RX signal is converted to after noise reduction, also the TX signal of HKS289BRM can be converted to BUS signal and be sent to transformer, the BUS signal of bus transceiver is sent in bus after meeting the requirements of Vpp through the propelling movement of transformer, the test of system works signalization Gonogo and subsystem failure signal Ssysf gives enable by arranging outside manual control, simultaneously provide 25 or the selectable RTC clock of 50MHz to system,
The invention provides the 1553B bus monitoring circuit based on Ethernet interface, 1553B bus interface is by bus transceiver and transformer, achieve effective Fault Isolation and the reliable transmission circuit of bus, solve the demand of the node under Domestic Transformers coupled modes, support 1M or 2Mbps transmission rate, provide bus system fast monitored analytical applications solution, meet miniaturized, intelligent, unitized 1553B node circuit.
Finally it should be noted that above embodiment only in order to technical scheme of the present invention to be described, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that; It still can be modified to the technical scheme that foregoing embodiments is recorded, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (3)
1., based on the 1553B bus monitoring circuit of Ethernet interface, it is characterized in that,
Ethernet interface, 1553B bus interface module, external storage controller (EBC) module, clock and reseting module, JTAG module and power module;
1553B bus interface module comprises MT memory, BCRT memory, MT protocol processor, 1553BCRT protocol processor, 1553B two-way transceiver, network clocking controller, a passage transformer and two passage transformers;
One passage transformer is connected with 1553B bus by transformer coupled mode with one end of two passage transformers, one passage transformer is connected with one end of 1553B two-way transceiver with the other end of two passage transformers, the other end of 1553B two-way transceiver is connected with MT protocol processor and 1553BCRT protocol processor, the 1553B data buffer storage of 1553BCRT protocol processor is in BCRT memory, the 1553B data buffer storage of MT protocol processor is in MT memory, network clocking controller is connected with 553BCRT protocol processor, for 1553B bus provides synchronised clock;
Ethernet interface comprises Ethernet transformer, ethernet PHY and Ethernet protocol processing unit;
One end of Ethernet transformer is connected with main frame by netting twine, the other end of Ethernet transformer is connected with ethernet PHY, ethernet PHY is connected with Ethernet protocol processing unit, and Ethernet protocol processing unit sends to main frame by ethernet PHY and Ethernet transformer after being used for reading 1553B data from MT memory and BCRT memory; The 1553B data conversion storage sent by main frame is in BCRT memory; Clock and reseting module provide unified clock and reset signal to 1553B bus interface module and Ethernet interface;
Described jtag interface module is used for providing JTAG function, debugs for regulating and controlling in 1553B bus interface module processed and Ethernet interface sheet;
Described power module is used for providing operating voltage to 1553B bus interface module and Ethernet interface;
Data transmit-receive between external storage controller (EBC) module controls 1553B bus interface module and 1553B bus and the communication of Ethernet interface and main frame.
2. the 1553B bus monitoring circuit based on Ethernet interface according to claim 1, is characterized in that: the transformation ratio of described passage one transformer and passage two transformer can regulate.
3. the 1553B bus monitoring circuit based on Ethernet interface according to claim 1 and 2, is characterized in that: the transmission rate of described MT protocol processor, 1553BCRT protocol processor is 1MHz or 2MHz.
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| CN201510924316.4A CN105490883A (en) | 2015-12-11 | 2015-12-11 | 1553B bus monitoring circuit based on Ethernet interface |
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| CN201510924316.4A CN105490883A (en) | 2015-12-11 | 2015-12-11 | 1553B bus monitoring circuit based on Ethernet interface |
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Cited By (4)
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| CN108123846A (en) * | 2017-12-06 | 2018-06-05 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of Ethernet data shaping feature test platform |
| CN111130966A (en) * | 2019-12-24 | 2020-05-08 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
| CN111800234A (en) * | 2020-06-30 | 2020-10-20 | 西安微电子技术研究所 | Conversion circuit of dual-redundancy Ethernet and intelligent 1553B bus |
| CN114124609A (en) * | 2021-09-30 | 2022-03-01 | 山东盖特航空科技有限公司 | Communication device and communication method based on 1553B bus |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108123846A (en) * | 2017-12-06 | 2018-06-05 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of Ethernet data shaping feature test platform |
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| CN111130966A (en) * | 2019-12-24 | 2020-05-08 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
| CN111130966B (en) * | 2019-12-24 | 2021-10-15 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
| CN111800234A (en) * | 2020-06-30 | 2020-10-20 | 西安微电子技术研究所 | Conversion circuit of dual-redundancy Ethernet and intelligent 1553B bus |
| CN111800234B (en) * | 2020-06-30 | 2023-03-14 | 西安微电子技术研究所 | Conversion circuit of dual-redundancy Ethernet and intelligent 1553B bus |
| CN114124609A (en) * | 2021-09-30 | 2022-03-01 | 山东盖特航空科技有限公司 | Communication device and communication method based on 1553B bus |
| CN114124609B (en) * | 2021-09-30 | 2023-03-14 | 山东盖特航空科技有限公司 | Communication device and communication method based on 1553B bus |
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