CN105515673B - A kind of optical-fibre channel node card - Google Patents
A kind of optical-fibre channel node card Download PDFInfo
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- CN105515673B CN105515673B CN201510849823.6A CN201510849823A CN105515673B CN 105515673 B CN105515673 B CN 105515673B CN 201510849823 A CN201510849823 A CN 201510849823A CN 105515673 B CN105515673 B CN 105515673B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/27—Arrangements for networking
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Abstract
The invention discloses a kind of optical-fibre channel node cards, are related to technical field of information transmission.The optical-fibre channel node card includes FPGA, for completing FC MAC, FC frames transmitting-receiving control, FC-AE-ASM protocol processes and host interface work；FPGA CFG Flash, the file for storing the field programmable gate array；Communication configuration flash memory, for storing communication configuration file；JTAG mouthfuls, it is located at edges of boards, FPGA Image is debugged and updated for FPGA；Clock oscillator；Reset chip, monitoring system power on situation, provide systematic reset signal；CONN interfaces provide all input/output signals；Control module, including FC protocol handling parts and PCIe host interface；Wherein, FPGA CFG Flash, communication configuration flash memory, JTAG mouthfuls, clock oscillator and CONN interfaces are connect with FPGA.Beneficial effects of the present invention：The optical-fibre channel node card of the present invention has the characteristics that small, low-power consumption, and hardware configuration is few, reduces total power consumption, so that optical-fibre channel node card performance is more stablized, and lighter in weight, is suitble to airborne requirement.
Description
Technical field
The present invention relates to technical field of information transmission, and in particular to a kind of optical-fibre channel node card.
Background technology
Optical-fibre channel (FC) network is applied to a variety of aircraft avionics systems as data communication main bus, in stable condition, full
The advanced synthesis architecture requirement of sufficient avionics system, it has also become the first choice of the present and following military aviation electronic system bus
Scheme.Optical-fibre channel node card plays core management role in entire FC networks, is provided for module/subsystem as interface equipment
Communication interface is responsible for the data of application being submitted on network, or collects data from network and submit to application, is also equipped with simultaneously
The network management function synchronous with clock.
Currently, China's optical-fibre channel node card designing technique is weaker, domestic performance stabilization not yet, low-power consumption, again
Measure light, small optical-fibre channel node card.
Invention content
The object of the present invention is to provide a kind of optical-fibre channel node cards, with solution or at least in the presence of mitigation background technology
At least one at the problem of.
The technical solution adopted in the present invention is：A kind of optical-fibre channel node card is provided, is connected by PCIe interface and host
It connects, runs on Vxworks operating systems, and host is connected to by its port FC by FC networks, including, field programmable gate array
FPGA, for completing FC MAC, FC frames transmitting-receiving control, FC-AE-ASM protocol processes and host interface work；Field programmable gate
Array configuration flash memory FPGA CFG Flash, the file for storing field programmable gate array；Communication configuration flash memory, for depositing
Store up communication configuration file；JTAG mouthfuls, it is located at edges of boards, the debugging for field programmable gate array and update field-programmable gate array
The file of row；Clock oscillator OSC；Reset chip RST, monitoring system power on situation, provide systematic reset signal；CONN connects
Mouthful, all input/output signals are provided；Wherein, field programmable gate array configuration flash memory FPGA CFG Flash, communication
Configuration flash memory, JTAG mouthfuls, clock oscillator OSC and CONN interface connect with on-site programmable gate array FPGA；The control
Module includes FC protocol handling parts and PCIe host interface two parts.
Preferably, the field programmable gate array selects the serial low-power consumption small packages of Xilinx 7, is ensureing treatability
In the case of energy, realize that module minimizes design.
Preferably, the model XC7A100T of the on-site programmable gate array FPGA.
Preferably, the field programmable gate array is configured to, and programmable logic resource reaches 100K, configurable to patrol
It collects block and reaches 15K；Block RAM are up to 4Mb or more；Embed 2 Clock Managing Units；8 road high-speed transceivers are supported
Highest receives and dispatches speed 5Gbps or more；PCIe modules are internally integrated, can support x4；Multiple IO Bank provide most 300 use
Family IO；Memory interface rate is up to 1066Mb/s.
Preferably, it includes ginseng inside the PCIe of 212.5MHz system clocks and 100MHz that the clock oscillator OSC, which is generated,
Examine clock.
Preferably, JTAG is reserved respectively in the device side of printing board PCB and reverse side debug port.
Preferably, the external power supply input in the CONN interfaces is voltage DC 5V, and input ripple is no more than 250mVp-
P, 4.75~5.25V of voltage range will carry out power conversion on 5V voltages.
Preferably, the FC protocol handling parts include FC-0 layers, FC-1 layers, FC-2 layer protocols and FC-AE-ASM layers of association
View processing.
Preferably, the PCIe host interface mainly realizes PCIe interface protocol processes and DMA control functions.
Preferably, the control module of the FC node cards is designed using multichannel concurrent reading and writing, is driven by interrupt event, real
Existing low CPU usage；Each channels share buffering area, it is less to Installed System Memory demand by efficient queue management mechanism, ensure
Data transfer sequence realizes high-speed data transmitting-receiving.
Beneficial effects of the present invention：FPGA selected by the optical-fibre channel node card of the present invention is before ensureing processing system energy
It puts, has the characteristics that small, low-power consumption, hardware configuration is few, reduces total power consumption, makes optical-fibre channel node card performance more
Stablize, and lighter in weight, is suitble to airborne requirement.
Control module is designed using multichannel concurrent reading and writing, is driven by interrupt event, is realized low CPU usage；Each channel
Shared buffer, it is less to Installed System Memory demand by efficient queue management mechanism, it ensure that data transfer sequence, realize
High-speed data transmitting-receiving.
Description of the drawings
Fig. 1 is the schematic diagram of the optical-fibre channel node card of the present invention.
Specific implementation mode
To keep the purpose, technical scheme and advantage that the present invention is implemented clearer, below in conjunction in the embodiment of the present invention
Attached drawing, technical solution in the embodiment of the present invention is further described in more detail.In the accompanying drawings, identical from beginning to end or class
As label indicate same or similar element or element with the same or similar functions.Described embodiment is the present invention
A part of the embodiment, instead of all the embodiments.The embodiments described below with reference to the accompanying drawings are exemplary, it is intended to use
It is of the invention in explaining, and be not considered as limiting the invention.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without creative efforts, shall fall within the protection scope of the present invention.Under
Face is described in detail the embodiment of the present invention in conjunction with attached drawing.
In the description of the present invention, it is to be understood that, term "center", " longitudinal direction ", " transverse direction ", "front", "rear",
The orientation or positional relationship of the instructions such as "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside" is based on attached drawing institute
The orientation or positional relationship shown, is merely for convenience of description of the present invention and simplification of the description, and does not indicate or imply the indicated dress
It sets or element must have a particular orientation, with specific azimuth configuration and operation, therefore should not be understood as protecting the present invention
The limitation of range.
As shown in Figure 1, a kind of optical-fibre channel node card, is connect by PCIe interface with host, Vxworks operations are run on
System, and host is connected to by its port FC by FC networks, including, on-site programmable gate array FPGA, for complete FC MAC,
FC frames transmitting-receiving control, FC-AE-ASM protocol processes and host interface work.
On-site programmable gate array internal include configurable logic blocks CLB (Configurable Logic Block),
Output input module IOB (Input Output Block) and three parts of interconnector (Interconnect).The base of FPGA
This feature mainly has：
1) use FPGA design ASIC circuit, user that need not throw piece production, the chip that can be shared.
2) FPGA can do the middle coupons of other full customs or semi-custom ASIC circuit.
3) there are abundant trigger and I/O pins inside FPGA.
4) FPGA is that the design cycle is most short, development cost are minimum in ASIC circuit, one of the device of least risk.
5) FPGA uses high speed CHMOS techniques, low in energy consumption, can be compatible with CMOS, Transistor-Transistor Logic level.
It can be said that fpga chip is one of the optimal selection that small lot system improves level of integrated system, reliability
Field programmable gate array configures flash memory FPGA CFG Flash, for storing FPGA Image files；Communication is matched
Flash is set, for storing communication configuration file；JTAG mouthfuls, it is located at edges of boards, FPGA Image is debugged and updated for FPGA；When
Clock oscillator OSC；Reset chip RST, monitoring system power on situation, provide systematic reset signal；CONN interfaces provide all defeated
Enter output signal；Wherein, field programmable gate array configuration flash memory FPGA CFG Flash, communication configuration Flash, JTAG
Mouth, clock oscillator OSC and CONN interface are connect with on-site programmable gate array FPGA；The control module includes FC agreements
Process part and PCIe host interface two parts.
In the present embodiment, FPGA selects the serial low-power consumption small packages of Xilinx 7, in the case where ensureing process performance,
Realize that module minimizes design.It the advantage is that, small volume is low in energy consumption, and performance is more stablized.
In the present embodiment, the model XC7A100T of on-site programmable gate array FPGA.
The fundamental performance parameter index of fpga chip：Programmable logic resource reaches 100K, and configurable logic block reaches
15K；Block RAM are up to 4Mb or more；Embed 2 Clock Managing Units；8 road high-speed transceivers support highest transmitting-receiving
Speed 5Gbps or more；PCIe modules are internally integrated, can support x4；Multiple IO Bank provide most 300 user IO；It deposits
Storage interface rate is up to 1066Mb/s.
In the present embodiment, it includes inside the PCIe of 212.5MHz system clocks and 100MHz that clock oscillator OSC, which is generated,
Reference clock.
JTAG mouthfuls, it is located at edges of boards, FPGA Image is debugged and updated for FPGA；In order to conveniently make in application process
With, printing board PCB device side and reverse side respectively reserve JTAG debug port.
In the present embodiment, the external power supply input in CONN interfaces is voltage DC 5V, and input ripple is no more than
250mVp-p, 4.75~5.25V of voltage range will carry out power conversion on 5V voltages.DC/DC power modules select Linear
Company's micropackaging structure power module.High-speed transceiver SERDES modules, which have power quality, compares strict requirements, for this
The power supply of module, using the TPS series LDO power supplys of TI companies high reliability.
CONN interfaces are unique connectors on printing board PCB, provide all input/output signals, including board supplies
Electricity, PCIe x4, FC power ports and SPI interface, wherein SPI interface update communication configuration file for peripheral hardware.
In the present embodiment, FC protocol handling parts include FC-0 layers, FC-1 layers, FC-2 layer protocols and FC-AE-ASM layers
Protocol processes.It is main to complete word synchronization, port state machine, CRC check, flow control, the parsing of FC frames, ASM data fractionation/recombination
Etc. functions.
PCIe host interface mainly realizes PCIe interface protocol processes and DMA control functions.
FC node card control modules are mainly driver, api interface program and relevant device/communication management module.It adopts
It is designed with multichannel concurrent reading and writing, is driven by interrupt event, realize low CPU usage, each channels share buffering area, by efficient
Queue management mechanism, both less Installed System Memory demand, in turn ensured data transfer sequence, realize high-speed data transmitting-receiving.
After host driver completes initialization, FC node cards are started to work, and are receiving direction, node card is first FC electricity
Interface, feeding are integrated in FPGA inner high speed transceivers, complete bit synchronous, serial/parallel conversion and 8b/10b decodings, then export
16 parallel datas.After word synchronization module in FPGA reception logics synchronizes 16 bit parallel datas received completion word,
It exports in 32 data to port state machine.According to FC standard agreements, after port state machine enters state of activation, could carry out
The transmitting-receiving of FC frames, after link activation, the FC frames received are sent to reception buffering area by FC node cards, through channel recognition and are had
After imitating load recombination, under the action of dma controller, it is transmitted in the reception buffering area in host through PCIe buses, waiting is answered
Use Program extraction.
In sending direction, host application program is by the transmission buffering area in data elder generation write driver to be sent, FC nodes
Card hardware is read data to be sent in the transmission buffering area of FC node cards under the action of dma controller, through PCIe buses, then
FC frames are split into according to channel information, are finally forwarded to the ports FC.
It is last it is to be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations.To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：It is still
Can be with technical scheme described in the above embodiments is modified, or which part technical characteristic is equally replaced
It changes；And these modifications or replacements, the essence for various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution
God and range.
Claims (6)
1. a kind of optical-fibre channel node card is connect with host by PCIe interface, runs on Vxworks operating systems, and pass through
Host is connected to FC networks by its port FC, it is characterised in that：Including
Field programmable gate array, for completing FC MAC, FC frames transmitting-receiving control, FC-AE-ASM protocol processes and host interface
Work, the field programmable gate array select 7 series of Xilinx, model XC7A100T, the field programmable gate array
Be configured to, programmable logic resource reaches 100K, and configurable logic block reaches 15K；Block RAM are up to 4Mb
More than；Embed 2 Clock Managing Units；8 road high-speed transceivers support highest to receive and dispatch speed 5Gbps or more；It is internally integrated PCIe
Module can support x4；Multiple IO Bank provide most 300 user IO；Memory interface rate is up to 1066Mb/s；
Field programmable gate array configures flash memory, the file for storing the field programmable gate array；
Communication configuration flash memory, for storing communication configuration file；
JTAG mouthfuls, it is located at edges of boards, for the debugging of field programmable gate array and the file of update field programmable gate array；
Clock oscillator；
Reset chip, monitoring system power on situation, provide systematic reset signal；
CONN interfaces provide all input/output signals；
Control module, including FC protocol handling parts and PCIe host interface two parts, the control module of FC node cards is using more
Channel concurrent reading and writing design, is driven, each channels share buffering area by interrupt event；
Wherein, the field programmable gate array configuration flash memory, communication configuration flash memory, JTAG mouthfuls, clock oscillator and CONN connect
Mouth is connect with field programmable gate array.
2. optical-fibre channel node card as described in claim 1, it is characterised in that：The clock oscillator generates
The PCIe internal reference clocks of 212.5MHz system clocks and 100MHz.
3. optical-fibre channel node card as described in claim 1, it is characterised in that：In the device side of printing board PCB and anti-
JTAG is reserved respectively and debugs port in face.
4. optical-fibre channel node card as described in claim 1, it is characterised in that：External power supply input in the CONN interfaces
For voltage DC 5V, input ripple is no more than 250mVp-p, 4.75~5.25V of voltage range, power supply change is carried out on 5V voltages
It changes.
5. optical-fibre channel node card as described in claim 1, it is characterised in that：The FC protocol handling parts include FC-0
Layer, FC-1 layers, FC-2 layer protocols and the processing of FC-AE-ASM layer protocols.
6. optical-fibre channel node card as described in claim 1, it is characterised in that：The PCIe host interface mainly realizes PCIe
Interface protocol processing and DMA control functions.
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| CN201510849823.6A CN105515673B (en) | 2015-11-27 | 2015-11-27 | A kind of optical-fibre channel node card |
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| CN201510849823.6A CN105515673B (en) | 2015-11-27 | 2015-11-27 | A kind of optical-fibre channel node card |
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| CN105515673B true CN105515673B (en) | 2018-11-13 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108614800A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AE-ASM protocol processing chip circuit structures |
| CN109684101B (en) * | 2018-12-12 | 2023-07-07 | 中国航空工业集团公司西安航空计算技术研究所 | FC_AE_ASM protocol processing engine circuit |
| CN111581152A (en) * | 2020-05-08 | 2020-08-25 | 安创生态科技(深圳)有限公司 | Reconfigurable hardware acceleration SOC chip system |
| CN112214451B (en) * | 2020-10-21 | 2021-08-10 | 成都成电光信科技股份有限公司 | High-speed monitoring recording equipment and method based on system on chip |
| CN113341814B (en) * | 2021-06-11 | 2022-08-23 | 哈尔滨工业大学 | Unmanned aerial vehicle flight control computer evaluation system |
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| CN102185833A (en) * | 2011-03-30 | 2011-09-14 | 无锡众志和达存储技术有限公司 | Fiber channel (FC) input/output (I/O) parallel processing method based on field programmable gate array (FPGA) |
| CN103107923A (en) * | 2013-02-27 | 2013-05-15 | 成都成电光信科技有限责任公司 | Fiber channel (FC) network data monitoring system and method based on system on chip (SOC) technology |
| CN203537390U (en) * | 2013-09-12 | 2014-04-09 | 成都成电光信科技有限责任公司 | Test system based on optical fiber channel |
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- 2015-11-27 CN CN201510849823.6A patent/CN105515673B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185833A (en) * | 2011-03-30 | 2011-09-14 | 无锡众志和达存储技术有限公司 | Fiber channel (FC) input/output (I/O) parallel processing method based on field programmable gate array (FPGA) |
| CN103107923A (en) * | 2013-02-27 | 2013-05-15 | 成都成电光信科技有限责任公司 | Fiber channel (FC) network data monitoring system and method based on system on chip (SOC) technology |
| CN203537390U (en) * | 2013-09-12 | 2014-04-09 | 成都成电光信科技有限责任公司 | Test system based on optical fiber channel |
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