CN105471855A - Low power elliptical curve encryption engine for electronic label rapid identity discrimination - Google Patents
Low power elliptical curve encryption engine for electronic label rapid identity discrimination Download PDFInfo
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- CN105471855A CN105471855A CN201510798808.3A CN201510798808A CN105471855A CN 105471855 A CN105471855 A CN 105471855A CN 201510798808 A CN201510798808 A CN 201510798808A CN 105471855 A CN105471855 A CN 105471855A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/0442—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply asymmetric encryption, i.e. different keys for encryption and decryption
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K17/00—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
- G06K17/0022—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations arrangements or provisious for transferring data to distant stations, e.g. from a sensing device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/0008—General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/08—Network architectures or network communication protocols for network security for authentication of entities
- H04L63/083—Network architectures or network communication protocols for network security for authentication of entities using passwords
Abstract
The invention belongs to the radio frequency identification technology field and particularly relates to a low power elliptical curve encryption engine for rapid electronic label identity discrimination. The ECC encryption engine comprises an arithmetic operation module, a register set module and a logic control module, wherein the arithmetic operation module comprises three sub modules of a finite field adder, a finite field multiplier and a finite field square arithmetic unit. Batch labels can be rapidly identified by employing the low power technology in combination with algorithm simplification, elliptical curve system configuration optimization and module realization; elliptical curve engine design can not only guarantee communication safety of labels and reader-writers, and design requirements in speed, area and power consumption can be further satisfied. The ECC encryption engine is suitable for realization schemes based on the Lopez-Daha elliptical curve system and the Montgomery step algorithm, effective support is provided for rapid false-proof verification on high additional value articles, and thereby article flow safety is enhanced.
Description
Technical field
The invention belongs to technical field of RFID, be specifically related to a kind of radio-frequency (RF) identification (RFID) tag encryption module, particularly relate to low-power consumption elliptic curve cryptography (ECC) engine that one can complete the discriminating of radio-frequency (RF) identification (RFID) tag identity fast.
Background technology
Passive type super high frequency radio frequency recognition technology obtains very much progress in recent years.The large equipment of many building blocks, high energy consumption replace by the small size microprocessor chip of super low-power consumption.The RFID processor system of these low costs is widely used in logistics, retail, engineering manufacture and electronic charging.In predictable future, these systems will have more wide application prospect.
It should be noted that; in above-mentioned all application; the data of personal information, financial information and some keys can pass to read write line from label, in the use occasion of these sensitivities, coded communication must be used to prevent leakage of personal information and to eliminate potential collision hazard that is economic and safety.Symmetric encipherment algorithm can be used in the design of low-power consumption microchip label, and ensures that its area, power consumption and speed meet typical RFID label tag requirement.But symmetric encipherment algorithm needs label and read write line to enjoy identical key, if therefore application huge cipher key management considerations will can be brought in large-scale open system.Relative, asymmetric-key encryption algorithm can provide relatively simple key management method: PKI can be disseminated widely, as long as and the private key that label takes good care of oneself just can complete basic communication.
Elliptic curve cryptography, as a kind of rivest, shamir, adelman, has been proved the safety anti-fake that can be applied to RFID.Each label has oneself unique private key, by the authentication means of asymmetric arithmetic, adds label by counterfeit difficulty.If provide enough memory physical protection means, the common attack to label private key almost can be prevented.Add suitable key length, be enough to provide the label of high strength to be protected, the article anti-counterfeit of high additive value can be used to.
Although rivest, shamir, adelman has above-mentioned many benefits, but due to the computational process of its complexity, encrypting and decrypting all needs time and the energy of at substantial each time, existing asymmet-ric encryption method focuses mostly on greatly research software field, even the realization of hardware, system also has a lot of problem needing to consider.
Summary of the invention
The object of the invention is for the deficiencies in the prior art, design one can complete low-power consumption elliptic curve cryptography (ECC) engine that radio-frequency (RF) identification (RFID) tag identity is differentiated fast.
Low-power consumption elliptic curve cryptography (ECC) engine of the present invention's design, by designing corresponding logical circuit for key modules, while raising arithmetic speed, control circuit power consumption and area, can be applicable to RFID label tag.
Whole encryption system comprises three levels: Part I is the realization of label base band.As the critical piece communicated with read write line, the part contains the basic modules such as front-end module, coding/decoding module, power consumption control module, elliptic curve cryptography engine can join in baseband system as security module, for system provides safety function; Part II is protocol section.ECC crypto engine algorithm may be used for the unilateral authentication of label, provides the antiforge function of label.Protocol Design is the verification process of a label of having been communicated by three between read write line and label time, and speed has very large advantage; Part III is exactly the design of ECC engine.Engine mainly comprises three large modules: arithmetical operation module (ALU), Parasites Fauna module and Logic control module; Wherein, arithmetical operation module comprises three main finite field operations subelements: finite field add operation (ADD), finite field multiplier computing (MUL) and finite field square operation (SQR); Parasites Fauna module is for storing middle operation result and exporting final calculation result; Logic control module comprises a finite state machine optimized, and is responsible for the running of the whole engine of scheduling.
Under the cooperation of three-tier system, the rapid authentication to a label and response can be completed.
Low-power consumption elliptic curve cryptography (ECC) engine of the present invention's design, its hardware structure as shown in Figure 1, comprise six large main modular and relevant control signal, six large main modular are: elliptic curve finite state machine, ALU, Parasites Fauna, finite field adder (ADD), Galois field multiplier (MUL) and finite field squarer (SQR), rear 3 modules composition arithmetical operation module (ALU).Each module in this design can be optimized and replace to corresponding operational module.
System input signal comprises key k, enabling signal ecc_start, elliptic curve basic point g and system clock clk.Output signal has x coordinate ecc_xa, z coordinate ecc_za and the computing end signal ecc_done of scalar multiplication operation result.Elliptic curve state machine carrys out memory location and the exchanged form of control register group data by register selection signal and register exchange signal; Meanwhile, elliptic curve state machine also call in control algorithm process addition, multiplication, square in a kind of finite field operations module, operation result is exported to Parasites Fauna by MUX and is stored into specific position; The control signal of MUX is also controlled by elliptic curve finite field state machine.Due in actual implementation procedure, the time of often kind of finite field operations is not identical, so each computing module has corresponding end signal notice elliptic curve state machine to carry out state switching or do corresponding operation to register.
The design of ALU module, based on Montgomery ladder algorithm, is divided into finite field adder, Galois field multiplier and finite field square operation device.Conventional Montgomery ladder algorithm comprises a lot of optimum configurations, in order to simplify state machine design and accelerate arithmetic speed, can remove some unnecessary parameters and judge and store in the design of reality.
What computing coordinate system was chosen is projected coordinate system, and this coordinate system can exempt the inversion operation that in calculating process, expense is huge, the substitute is last step inversion operation being arranged into computing.The realistic meaning done like this is the computing that can simplify tab end.Because inversion operation needs to consume long time and huge power consumption, passive label is difficult to bear so big expense.Consider that read write line has the power supply of power supply, and have powerful microprocessor, process inversion operation is relatively simple, and therefore inversion operation being given read write line to process is good work-around solution.By the conversion of coordinate system, greatly reduce the computing pressure of label, improve the speed of process and the final effect of encryption can not be affected.
Computing flow process is based on Montgomery ladder algorithm, and the algorithm data flow point after simplifying is point doubling and point add operation.Times point operation comprises 4 square operations, 2 multiply operations and the operation of 1 sub-addition, and some add operation comprises 1 square operation, 3 multiply operations and the operation of 3 sub-additions, amounts to 5 multiplyings, 5 square operations and 4 sub-addition computings.And due to doubly mutually more uncorrelated with point add operation, decrease the coupling of calculating process, facilitate the parallel processing of data flow.Algorithm data stream after simplifying as shown in Figure 2, only contains 5 multiplyings, 5 square operations and 4 sub-addition computings, and as can be seen from the figure, the computing of Zuo Sanlie and right three row is mutually uncorrelated, decreases the coupling of calculating process, facilitates the parallel processing of data flow.
In three kinds of finite field operations, need the realization considering emphatically multiplier.Multiplier can account for the overhead of more than 80%.By optimizing multiplier, ECC engine performance can be significantly improved.Multiplier adopts serial-parallel patten's design, supposes that be encrypted computing to d position wherein, iteration obtains final result a/d time at every turn by the length decile of the key of a position by d.The computing of each d position is finite field multiplier computing, in order to reduce computing clock number, the modulo operation in multiplying is designed to complete together after each iteration.In actual design, the length of d is chosen and is chosen according to carrying out balance to the requirement of power consumption and speed: larger d means larger power consumption and speed faster; And less d means less power consumption and slower speed.Multiplier system hardware block diagram as shown in Figure 3.
In order to reduce circuit complexity, operand a same partial arithmetic number b can be allowed to carry out multiply operation at every turn, adopt highest order to start the strategy (MSB) of computing in embodiment, each computing needs distributor to carry out buffer memory, uses combinational logic to complete modulo operation in calculating process.In actual applications, if parallel figure place is abundant, greatly the speed of service can be improved.But after parallel figure place is higher than 8, area and power consumption all can rise rapidly, so general design should select degree of parallelism between 4 to 8.The multiplier architecture block diagram of 5 parallel-by-bits is illustrated in this example.
In order to accelerate verification process, the present invention is based on the read write line of Fig. 4 and the communication process of label, main purpose is the time overhead in order to reduce communication, thus accelerates the speed of checking further.This verification process is label unilateral authentication, and key step comprises the following steps:
(1) generate random number r by read write line, r and elliptic curve basic point G is carried out scalar multiplication computing (rG), the x coordinate of result of calculation and z coordinate is done finite field division and obtains intermediate object program T, subsequently T is passed to label;
(2) label to receive after T at the appointed time, utilizes ECC crypto engine, T and label private key q is done scalar multiplication computing, and the x of result of calculation and z coordinate are passed to read write line together with label PKI Q;
(3) read write line utilizes private key and tag computation result verification tag identity, and certification by then carrying out follow-up operation, otherwise abandons epicycle communication.
For the efficient elliptic curve cryptography engine of above-mentioned design, present invention also offers the further optimization system performance of following scheme:
(1) adopt operand isolation, reduce the extra power consumption of idle module.Operand isolation mainly for be control to input operand in ALU;
(2) adopt gated clock and multi-clock zone design, reduce invalid clock upset.This design mainly designs for multiple register banks.
The invention has the advantages that: by optimizing elliptic curve systems framework and module realization, shortcut calculation and use Low-power Technology, can complete the asymmetric cryptography certification for RFID label tag fast.Elliptic curve engine design disclosed by the invention can not only ensure the safety that label communicates with read write line, and can reach the designing requirement of speed, area and power consumption.System architecture of the present invention, is applicable to the implementation of elliptic curve systems based on Lopez-Dahab and Montgomery ladder algorithm, can be used to the article of high additive value, as bank note false proof among.
Accompanying drawing explanation
Fig. 1 is ECC crypto engine system hardware block diagram.
Fig. 2 is cryptographic algorithm flow chart.
Fig. 3 is ECC multiplier hardware figure.
Fig. 4 is agreement FB(flow block).
Embodiment
Embodiments of the present invention are specifically described below in conjunction with accompanying drawing.
Elliptic curve cryptography automotive engine system hardware block diagram as shown in Figure 1,
Crypto engine mainly comprises three large modules: arithmetical operation module (ALU), Parasites Fauna module and arithmetic logic unit module.
Arithmetical operation module comprises three main finite field operations subelements: finite field adder (ADD), Galois field multiplier (MUL) and finite field square operation device (SQR).
Finite field adder is based on finite field add operation, and in the elliptic curve implementation represented with binary radix, the realization of add operation is exactly the xor operation of one group of parallel register group, just can complete within a clock cycle;
Galois field multiplier is based on the abbreviation form of multiplication, and 163 system-computed expression formulas are:
Can derive according to above expression formula and obtain:
Finite field multiplier operational hardware block diagram as shown in Figure 3, can allow the b of a and a part carry out multiply operation at every turn.Adopt highest order to start the strategy (MSB) of computing in this example, each computing needs distributor to carry out buffer memory, uses combinational logic to complete modulo operation in calculating process.In actual applications, after parallel figure place is higher than 8, area and power consumption all can rise rapidly, so general design alternative degree of parallelism is between 4 to 8.
Parasites Fauna module achieves 5 group of 163 bit register (designs for 163 bit encryption engines), can be read by index value or store corresponding register.In order to reduce system power dissipation, through algorithm optimization, each finite field operating process only does storage operation to a register, turns off register clock port in all the other times completely by gated clock, reduces quiescent dissipation loss.
Logic control module is embodied as the finite state machine of an optimized algorithm, is responsible for the running of whole engine.Steering algorithm flow process is switched by state machine state.After state machine completes computing, provide final termination signal.The implementation of algorithm as shown in Figure 2.This algorithm only contains 5 multiplyings, 5 square operations and 4 sub-addition computings.Therefrom can find out, the computing of Zuo Sanlie and right three row is mutually uncorrelated, decreases the coupling of calculating process, facilitates the process of data flow.
Agreement can use the simple version shown in Fig. 4, also can realize user-defined asymmetric authentication method.It is crucial that the computing of scalar multiplication in agreement, the namely use of above-mentioned ECC engine.Use scalar multiplication, the communications version of various different security intensity can be realized out easily.
In order to reach higher performance, optimised power consumption scheme can be adopted.Specifically comprise:
One, operand isolation, considers that ALU only has a module carrying out computing in same period, if by not closing in the module run, can avoid the dynamic power consumption of inactive module.By adding MUX to ALU operator module, effectively can reduce the upset of signal in module, thus reduce power consumption;
Two, gated clock scheme, for multiple register banks design, reduces the quiescent dissipation of Parasites Fauna.In addition, multi-clock zone and multiple voltage domain is adopted also significantly can to reduce the power consumption of whole label chip at base band level.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (5)
1. for a low-power consumption elliptic curve cryptography engine for the quick identity verify of electronic tag, it is characterized in that, comprise following module: elliptic curve finite state machine, ALU, Parasites Fauna, arithmetical operation module; Arithmetical operation module is made up of finite field adder, Galois field multiplier and finite field squarer; Wherein:
Input signal comprises: key k, enabling signal ecc_start, elliptic curve basic point g and system clock clk; Output signal has the x coordinate ecc_xa of scalar multiplication operation result, z coordinate ecc_za and computing end signal ecc_done; Elliptic curve state machine carrys out memory location and the exchanged form of control register group data by register selection signal and register exchange signal; Meanwhile, elliptic curve state machine also call in control algorithm process addition, multiplication, square in a kind of finite field operations module, operation result is exported to Parasites Fauna by MUX and is stored into specific position; The control signal of MUX is also controlled by elliptic curve finite field state machine; Because the time of often kind of finite field operations is not identical, each computing finite field module has corresponding end signal notice elliptic curve state machine to carry out state switching or do corresponding operation to register.
2. crypto engine according to claim 1, is characterized in that, ALU module based on Montgomery ladder algorithm, and carry out simplifying process, namely remove the unnecessary parameter of some of them and judge and store;
What computing coordinate system was chosen is projected coordinate system;
Algorithm data flow point after simplifying is point doubling and point add operation; Times point operation comprises 4 square operations, 2 multiply operations and the operation of 1 sub-addition, and some add operation comprises 1 square operation, 3 multiply operations and the operation of 3 sub-additions, amounts to 5 multiplyings, 5 square operations and 4 sub-addition computings.
3. crypto engine according to claim 2, is characterized in that, Galois field multiplier (MUL) adopts serial-parallel mode, supposes that be encrypted computing to d position wherein, iteration obtains final result a/d time at every turn by the length decile of the key of a position by d; The computing of each d position is finite field multiplier computing, in order to reduce computing clock number, the modulo operation in multiplying is designed to complete together after each iteration.
4. crypto engine according to claim 2, is characterized in that, for the communication process of read write line and label, adopt the method accelerating verifying speed, verification process is label unilateral authentication, and its step comprises:
(1) generate random number r by read write line, r and elliptic curve basic point G is carried out scalar multiplication computing (rG), the x coordinate of result of calculation and z coordinate is done finite field division and obtains intermediate object program T, subsequently T is passed to label;
(2) label to receive after T at the appointed time, utilizes ECC crypto engine, T and label private key q is done scalar multiplication computing, and the x of result of calculation and z coordinate are passed to read write line together with label PKI Q;
(3) read write line utilizes private key and tag computation result verification tag identity, and certification by then carrying out follow-up operation, otherwise abandons epicycle communication.
5. crypto engine according to claim 2, is characterized in that, additionally provides the further optimization system performance of following scheme:
(1) in ALU to input operand, adopt operand isolation, reduce the extra power consumption of idle module;
(2) for multiple register banks, adopt gated clock and multi-clock zone design, reduce invalid clock upset.
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| CN109218023A (en) * | 2017-06-29 | 2019-01-15 | 英特尔公司 | Technology for robust calculation digital signature of elliptic curve |
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Cited By (8)
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| CN109643111A (en) * | 2016-08-25 | 2019-04-16 | 宁波吉利汽车研究开发有限公司 | For detecting the method and system of the failure in vehicle control system |
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| CN112861550A (en) * | 2019-11-27 | 2021-05-28 | 思力科（深圳）电子科技有限公司 | Electronic tag object searching method, object searching system and computer readable storage medium |
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| CN113114462A (en) * | 2021-03-31 | 2021-07-13 | 南京航空航天大学 | Small-area scalar multiplication circuit applied to ECC (error correction code) safety hardware circuit |
| CN113114462B (en) * | 2021-03-31 | 2022-10-04 | 南京航空航天大学 | Small-area scalar multiplication circuit applied to ECC (error correction code) safety hardware circuit |
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