CN105356935B - A kind of cross board and implementation method for realizing SDH high order cross - Google Patents
A kind of cross board and implementation method for realizing SDH high order cross Download PDFInfo
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- CN105356935B CN105356935B CN201510840726.0A CN201510840726A CN105356935B CN 105356935 B CN105356935 B CN 105356935B CN 201510840726 A CN201510840726 A CN 201510840726A CN 105356935 B CN105356935 B CN 105356935B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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- Electromagnetism (AREA)
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Abstract
The present invention relates to a kind of cross board and implementation method for realizing SDH high order cross, including power supply module, clock module, safeguard and management module, Service Processing Module, control module and communication module, power supply module is that device is powered and monitors the voltage x current state of each power supply, communication module receives the intersection order of host computer, control module is handed down to after parsing, control module is received to intersect and instructed and judge whether correctly, as that correctly intersection information issuing service processing module will be carried out cross processing, clock module will copy as 4 tunnels after the clock multiplier received, reference clock required for providing, maintenance and management module obtain the voltage x current information of board, host computer is reported if any abnormal, and close this plate power supply, the module also reports the version information of this plate to host computer simultaneously, the information such as cross chips temperature and FPGA temperature, have the technical effect that, realize 640G × 640G cross-capacity and 40G × 20G high order cross, it is simple to operate, intersect switching accurate, in real time, it is stable.
Description
Technical field
The present invention relates to a kind of fiber optic communication cross board, more particularly to a kind of friendship for realizing SDH high order cross
Fork plate and implementation method.
Technical background
Fiber optic communication is because transmission capacity is big, small, lightweight, small volume, anti-electromagnetic interference capability is lost by force and confidentiality
Good the advantages of, in an increasingly wide range of applications in the communications, not only backbone network, Metropolitan Area Network (MAN) are all transmitted using optical fiber, and
Access network also generally realizes convergence using optical fiber.Thus brought the problem of is to carry out skill to vast as the open sea optical-fiber network information
The difficulty that art is intercepted and scouted is increasing, and especially when realizing intersection in the case that Large Copacity is accessed, hardware circuit is set
Meter is very big challenge.
The content of the invention
In view of the problem of technology is present now, the present invention provides a kind of cross board for realizing SDH high order cross, intersection is utilized
Chip realizes 640G × 640G cross-capacity, and realizes using FPGA 40G × 20G high order cross, particular technique side
Case is, a kind of cross board for realizing SDH high order cross, including power supply module, clock module, maintenance and management mould
Block, Service Processing Module, six functional modules of control module and communication module, it is characterised in that：Hot plug module is with 48V voltages
Rail connects power supply module, and power supply module powers to whole circuit, and hot plug module is also with 3.3V Voltage rails to safeguarding and management module
Power supply, clock module is unidirectionally connected with Service Processing Module, communication module respectively, and Service Processing Module passes through simultaneously with control module
Mouth is bi-directionally connected, and control module is bi-directionally connected with communication module by I2C interfaces, and control module passes through with maintenance and management module
Serial ports is bi-directionally connected, and safeguards and management module is bi-directionally connected by SPI interface with communication module, also connect by 485 interfaces, 12C
Mouthful it is bi-directionally connected with ZD connectors, communication module is bi-directionally connected by LVDS interface with ZD connectors, ZD connectors are to clock mould
Block sends 19.44M clocks, and is bi-directionally connected by differential lines with Service Processing Module；Described power supply module includes optical coupling
Chip, DC/DC power modules, digital power module, power supply chip, optical coupling chip unidirectionally connect DC/DC power modules, DC/
DC power module unidirectionally connects seven digital power modules, obtains seven Voltage rails needed for board, and wherein 3.3V power rails connect
Electric sequence Voltage rails need not be configured by connecing two power supply chips generations two；Described communication module is by FPGA and FLASH groups
Into being bi-directionally connected with configuration bus, described clock module is by a MLVDS driving chip and two clock chip concatenation groups
Into described Service Processing Module includes cross chips, FPGA, SFP+ optical module, sub-miniature A connector, and cross chips pass through input port
Unidirectionally it is connected with ZD connectors, cross chips are bi-directionally connected by parallel interface with control module, cross chips pass through delivery outlet
Unidirectionally it is connected with ZD connectors, FPGA, sub-miniature A connector, FPGA is unidirectionally connected by SERDES with SFP+ optical modules.
The method for realizing SDH high order cross is instructed according to the intersection of host computer, is docked using cross chips
The high-speed SDH signal received carries out cross processing, backboard is accessed via ZD connectors, while passing out to the two of this plate via FPGA
Individual optical module, is polled processing, and wherein power supply module is responsible for power supply and the voltage detecting of whole plate device, and clock module is responsible for carrying
For the reference clock needed for communication module and Service Processing Module, safeguard and management module be responsible for this plate monitoring information processing and
Warning information is reported, and control module is responsible for（1）Communicated by I2C interfaces with communication module, receive the intersection that communication module is issued
Routing iinformation and balanced preemphasis information.（2）Communicated by parallel interface with Service Processing Module, by the routing iinformation received
Service Processing Module is handed down to after parsing, and passes through the crossing condition of this port reading current business processing module.（3）Pass through string
Mouth communicates with maintenance and management module, will intersect the monitoring information such as errors number and cross chips temperature and reports maintenance and manage
Module, communication module is responsible for receiving the intersection order that host computer is sent, and Service Processing Module, business processing mould are handed down to after parsing
Block is responsible for（1）Cross chips（VSC3144）It is connected by parallel interface with control module, the intersection life that receive and control module is issued
ZD connectors are beamed back after order, the 128 road 5G signal cross that ZD connectors are received, are given while replicating 8 road 5G signals therein
FPGA, is used for poll.（2）FPGA（XC7K325T）It is connected by SERDES with cross chips, receives and carry out Self-crossover core
The 8 road 5G signals that piece is replicated, by high order cross, recombine two-way 10G signal and are sent by SFP+ optical modules.（3）
High speed signal can be deteriorated by signal quality after ZD connectors, by parallel interface, and control module can set cross chips
Balanced and pre-emphasis parameters, with Regulate signal quality, and are connected to the eye that high-speed oscilloscope checks current demand signal by sub-miniature A connector
Figure.
The solution have the advantages that, 640G × 640G cross-capacity and 40G × 20G high order cross are realized, with
Complete to intersect poll, it is simple to operate, intersect switching accurately, in real time, stably.
Brief description of the drawings
Fig. 1 system module circuit block diagrams.
Fig. 2 power supply module circuit block diagrams.
Fig. 3 communication module circuitry block diagrams.
Fig. 4 clock module circuit block diagrams.
Fig. 5 Service Processing Module circuit block diagrams.
Embodiment
As shown in figure 1, system function division is six functional modules, power supply module, communication module, control module, business
Processing module, clock module and maintenance and management module.Hot plug module connects power supply module, power supply module with 48V Voltage rails
Powered to whole circuit, hot plug module also with 3.3V Voltage rails to safeguard and management module power, clock module respectively with business
Processing module, communication module are unidirectionally connected, and Service Processing Module is bi-directionally connected with control module by parallel port, and control module is with leading to
Letter module is bi-directionally connected by I2C interfaces, and control module is bi-directionally connected with maintenance and management module by serial ports, is safeguarded and is managed
Module is bi-directionally connected by SPI interface with communication module, is also bi-directionally connected by 485 interfaces, 12C interfaces and ZD connectors, is led to
Letter module is bi-directionally connected by LVDS interface with ZD connectors, and ZD connectors send 19.44M clocks to clock module, and pass through
Differential lines are bi-directionally connected with Service Processing Module；
System work main-process stream is that all devices that power supply module is board are powered and monitor the voltage x current of all power supplys,
To ensure the normal operation of board, communication module receives the intersection order that host computer is issued by LVDS buses, passed through after parsing
I2C buses are handed down to control module, and control module, which is received, first checks whether order is correct after intersection instruction, if correctly will be
Intersection information is handed down to Service Processing Module by parallel port and carries out cross processing.When clock module is by the 19.44M circuits received
Clock frequency multiplication is to 155.52M and copies as 4 tunnels, and 1 tunnel is to communication module, and 3 tunnels are to Service Processing Module, required for being provided for them
Reference clock, to ensure that the clock of system is synchronous.Safeguard and management module is believed by the voltage x current of PMBUS buses acquisition board
Breath, if voltage x current has exception to report host computer by I2C buses, and closes this plate power supply, while the module also passes through
485 buses report the version information of this plate, cross chips temperature information and FPGA temperature informations.
As shown in Fig. 2 power supply module includes optical coupling chip, DC/DC power modules, digital power module, power supply chip,
Optical coupling chip unidirectionally connects power module, and power module unidirectionally connects seven digital power modules, obtains seven needed for board
Individual Voltage rails, wherein 3.3V Voltage rails, which connect two power supply chips generations two, need not configure electric sequence Voltage rails, power
Module major function is powered for board, and this plate is powered by 48V power supplys, supports hot plug, supports voltage, the real-time prison of electric current
Control, can control electricity and power down order.Hot plug uses the PIM4328 hot plug modules of Ericsson, except output 48V
Outside Voltage rails, 3.3V Voltage rails have also been provided separately, it is ensured that safeguard and management module and board other power supplys completely every
From accordingly even when the power supply module of board breaks down, maintenance and management module also can normally be run, and pass through PMBUS buses
The voltage x current information of each power supply of board is read, host computer is reported by IC2 buses after collecting, so as to quick positioning failure,
Simultaneously by controlling optocoupler TLP291 to turn off business power supply module.DC/DC power supply mould of the business power supply module first by GE
Block EBVW020A0B641Z obtains 12V Voltage rails, and digital power the module BMR464 and BMR461 for reusing Ericsson obtain plate
Each Voltage rails needed for card, the digital power supports the setting of electric sequence and power down order, it is possible to pass through PMBUS buses
By the state reporting of power supply to maintenance and management module.While the cost in order to reduce board, has used TI LDO power supply chips
TPS74401, which is produced, need not configure electric sequence and the less Voltage rails of power consumption.
As shown in figure 3, communication module is made up of FPGA and FLASH, be bi-directionally connected with configuration bus, communication module it is main
Function be receive host computer intersection instruction parsing after be handed down to control module, while to safeguard and management module report communication shape
The information such as state and crossing condition.FPGA model is XILINX XC6SLX25, and FLASH model is M25P128, and configuration is total
Line is spi bus.The reference clock that XC6SLX25 is used comes from clock module, it is ensured that the clock of system is synchronous, XC6SLX25
The intersection from host computer is received by LVDS buses to instruct, and control module is handed down to by I2C buses after parsing, and pass through
I2C buses are read with the crossing condition postponed.XC6SLX25 also monitors LVDS communications status simultaneously, and issued by contrast and
The intersection information read back, judges whether intersection succeeds.The monitoring information such as LVDS communications status and crossing condition passes through on spi bus
Offer maintenance and management module.
Constituted as shown in figure 4, clock module is serially connected by tri- chips of DS176, SI5322 and SI5330, clock mould
Block is mainly responsible for the FPGA of business module and the FPGA of communication module provides reference clock, to ensure that the clock of system is synchronous.
The workflow of clock module is that the 19.44M differential clocks that backboard ZD connectors enter are defeated by MLVDS driving chips DS176
Go out 19.44M single ended clocks and give SI5322 chips, SI5322 chips are mainly responsible for filtering, debounce and the frequency multiplication of clock.Clock passes through
The differential clocks that 155.52M is exported after SI5322 frequencys multiplication give clock chip SI5330, SI5330 to be copied into 155.52M clock
4 tunnels, 1 tunnel to communication module FPGA as reference clock, 3 tunnels are used as reference clock to the FPGA of Service Processing Module.
The chip that control module is used is single-chip microcomputer, model C8051F020, and main external interface is I2C interfaces, serial ports
And parallel interface.The function that single chip control module is mainly completed：（1）Communicated by I2C interfaces with communication module, receive communication
Interleaving route information and balanced preemphasis information that module is issued.（2）Communicated, will be connect with Service Processing Module by parallel interface
Service Processing Module is handed down to after the routing iinformation parsing received, and passes through the intersection of this port reading current business processing module
State.（3）Communicated, will intersected in the monitoring information such as errors number and cross chips temperature with maintenance and management module by serial ports
Offer maintenance and management module.
Safeguard and the chip that uses of management module is ARM7, model LPC2378, main external interface be I2C interfaces,
RS485 interfaces, SPI interface and PMBUS interfaces.Safeguard and the power supply of management module is independent, and other isolated from power, so
Even if other module for power supply it is abnormal it can also normal work, and abnormal information is read by PMBUS buses, is easy to investigation
Failure.The function that ARM is safeguarded and management module is mainly completed：（1）Communicated by PMBUS interfaces with power module, read each
The voltage x current information of power module, and the electric sequence and power down order for passing through this Interface Controller each power module.（2）
It is connected by I2C interfaces with backboard ZD connectors, when the cross chips temperature of board is too high or power module breaks down, is led to
Cross I2C interfaces and warning information is reported into host computer.（3）Communicated by SPI interface with communication module, read communication module and report
LVDS bus states and the monitoring information such as optical module luminous power.（4）It is connected by 485 interfaces with backboard ZD connectors, by plate
The information reportings such as version information, optical module luminous power and the cross chips temperature of card are to host computer.
As shown in figure 5, Service Processing Module includes cross chips, FPGA, SFP+ optical module, sub-miniature A connector, cross chips lead to
Cross input port to be unidirectionally connected with ZD connectors, cross chips are bi-directionally connected by parallel interface with control module, cross chips lead to
Cross delivery outlet to be unidirectionally connected with ZD connectors, FPGA, sub-miniature A connector, FPGA is unidirectionally connected by SERDES with SFP+ optical modules.Hand over
Fork chip model is VSC3144, and FPGA model XC7K325T, the function that Service Processing Module is specifically completed is as follows：（1）Intersect
Chip（VSC3144）It is connected by parallel interface with control module, the intersection order that receive and control module is issued, by ZD connectors
ZD connectors are beamed back after the 128 road 5G signal cross received, while 8 road 5G signals therein are replicated to FPGA, for poll
Use.（2）FPGA（XC7K325T）It is connected by SERDES with cross chips, receives the 8 road 5G letters replicated from cross chips
Number, by high order cross, recombine two-way 10G signal and sent by SFP+ optical modules.（3）High speed signal is connect by ZD
Signal quality can be deteriorated after plug-in unit, by parallel interface, and control module can set equilibrium and the pre-emphasis parameters of cross chips,
With Regulate signal quality, and the eye pattern that high-speed oscilloscope checks current demand signal is connected to by sub-miniature A connector.
Claims (2)
1. a kind of cross board for realizing SDH high order cross, including power supply module, clock module, maintenance and management mould
Block, Service Processing Module, six functional modules of control module and communication module, it is characterised in that：Hot plug module is with 48V voltages
Rail connects power supply module, and power supply module powers to whole circuit, and hot plug module is also with 3.3V Voltage rails to safeguarding and management module
Power supply, clock module is unidirectionally connected with Service Processing Module, communication module respectively, and Service Processing Module passes through simultaneously with control module
Mouth is bi-directionally connected, and control module is bi-directionally connected with communication module by I2C interfaces, and control module passes through with maintenance and management module
Serial ports is bi-directionally connected, and safeguards and management module is bi-directionally connected by SPI interface with communication module, also connect by 485 interfaces, 12C
Mouthful it is bi-directionally connected with ZD connectors, communication module is bi-directionally connected by LVDS interface with ZD connectors, ZD connectors are to clock mould
Block sends 19.44M clocks, and is bi-directionally connected by differential lines with Service Processing Module；Described power supply module includes optical coupling
Chip, DC/DC power modules, digital power module, power supply chip, optical coupling chip unidirectionally connect DC/DC power modules, DC/
DC power module unidirectionally connects seven digital power modules, obtains seven Voltage rails needed for board, and wherein 3.3V power rails connect
Electric sequence Voltage rails need not be configured by connecing two power supply chips generations two；Described communication module is by FPGA and FLASH groups
Into being bi-directionally connected with configuration bus, described clock module is by a MLVDS driving chip and two clock chip concatenation groups
Into described Service Processing Module includes cross chips, FPGA, SFP+ optical module, sub-miniature A connector, and cross chips pass through input port
Unidirectionally it is connected with ZD connectors, cross chips are bi-directionally connected by parallel interface with control module, cross chips pass through delivery outlet
Unidirectionally it is connected with ZD connectors, FPGA, sub-miniature A connector, FPGA is unidirectionally connected by SERDES with SFP+ optical modules.
2. the cross board implementation method for realizing SDH high order cross described in a kind of use claim 1, its feature
It is：Instructed according to the intersection of host computer, cross processing is carried out to the high-speed SDH signal received using cross chips, via
ZD connectors access backboard, while passing out to two optical modules of this plate via FPGA, are polled processing, wherein power supply module
It is responsible for power supply and the voltage detecting of whole plate device, clock module is responsible for providing the reference needed for communication module and Service Processing Module
Clock, is safeguarded and management module is responsible for the monitoring information processing of this plate and warning information is reported, and control module is responsible for（1）Pass through
I2C interfaces communicate with communication module, receive interleaving route information and balanced preemphasis information that communication module is issued；（2）Pass through
Parallel interface communicates with Service Processing Module, is handed down to Service Processing Module after the routing iinformation received is parsed, and pass through
Read the crossing condition of current business processing module in this port；（3）Communicated, will intersected with maintenance and management module by serial ports
The monitoring information such as errors number and cross chips temperature reports maintenance and management module, and communication module is responsible for receiving host computer hair
The intersection order come, is handed down to Service Processing Module after parsing, Service Processing Module is responsible for（1）Cross chips（VSC3144）It is logical
Cross parallel interface with control module to be connected, the intersection order that receive and control module is issued, the 128 road 5G that ZD connectors are received believe
ZD connectors are beamed back after number intersecting, while replicating 8 road 5G signals therein to FPGA, are used for poll；（2）FPGA
（XC7K325T）It is connected by SERDES with cross chips, receives the 8 road 5G signals replicated from cross chips, handed over by high-order
Fork, recombines two-way 10G signal and is sent by SFP+ optical modules；（3）High speed signal passes through signal matter after ZD connectors
Amount can be deteriorated, and by parallel interface, control module can set equilibrium and the pre-emphasis parameters of cross chips, with Regulate signal matter
Amount, and the eye pattern that high-speed oscilloscope checks current demand signal is connected to by sub-miniature A connector.
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107528635B (en) * | 2017-08-17 | 2024-03-19 | 北京广利核系统工程有限公司 | Communication device and method based on SFP optical module |
| CN108023839B (en) * | 2017-12-13 | 2023-12-08 | 天津光电通信技术有限公司 | Signal switching equipment applied to Tb/s-level optical network and control system thereof |
| CN108933971A (en) * | 2018-04-13 | 2018-12-04 | 电信科学技术第五研究所有限公司 | More equipment cross exchange control methods |
| CN109861782B (en) * | 2018-12-07 | 2020-06-12 | 天津光电通信技术有限公司 | SDH protocol signal analysis platform based on PCIE acquisition board card |
| CN111092361B (en) | 2019-12-06 | 2021-04-06 | 华东师范大学重庆研究院 | Optical comb time-frequency intelligent control method and system |
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| CN101277547A (en) * | 2008-03-18 | 2008-10-01 | 天津光电通信技术有限公司 | Large-scale strict non-blockage light-crossing connection matrix structure and control method thereof |
| CN202103685U (en) * | 2011-06-23 | 2012-01-04 | 天津光电通信技术有限公司 | SDH (Synchronous Digital Hierarchy) high-order cross control circuit based on FPGA (Field Programmable Gate Array) and realized by single-chip |
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| US5999902A (en) * | 1995-03-07 | 1999-12-07 | British Telecommunications Public Limited Company | Speech recognition incorporating a priori probability weighting factors |
| CN101277547A (en) * | 2008-03-18 | 2008-10-01 | 天津光电通信技术有限公司 | Large-scale strict non-blockage light-crossing connection matrix structure and control method thereof |
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