CN105320463A - Solid-state storage device with mixed storage mode - Google Patents
Solid-state storage device with mixed storage mode Download PDFInfo
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- CN105320463A CN105320463A CN201410331434.XA CN201410331434A CN105320463A CN 105320463 A CN105320463 A CN 105320463A CN 201410331434 A CN201410331434 A CN 201410331434A CN 105320463 A CN105320463 A CN 105320463A
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Abstract
A solid-state storage device with a mixed storage mode is mainly composed of a flash memory and a data processing module in information connection with the flash memory. The flash memory comprises a first storage magnetic region storing data in a first potential storage mode and a second storage magnetic region storing the data in a second potential storage mode, the entity block address of the first storage magnetic region is P0-PM-1, the logic block address of the first storage magnetic region is L0-LM-1, the entity block address of the second storage magnetic region is PM-PM+N-1, and the logic block address of the first storage magnetic region is LM-LM+N-1. The data processing module has the data processing mode that the logic block address contained in one instruction is unscrambled, and instruction actions are executed at the corresponding entity block address. Therefore, the solid-state storage device is high in stability and large in data storage capacity.
Description
Technical field
The present invention relates to a kind of solid state storage device, particularly relate to a kind of solid state storage device implementing two or more current potential storage mode with identical fast flash memory bank.
Background technology
With solid state storage device (Solid-StateDrive, SSD) maturation of technology, to replace existing hard disc device (HardDiskDrive gradually, HDD), the solid state storage device reaction velocity that has data access compared to existing hard disc device is quick, power consumption is low, the advantage such as lightweight.
Again, solid state storage device mainly utilizes the floating grid plate transistor of a fast flash memory bank to carry out storage data bit Data, and single stage unit formula (Single-LevelCell can be distinguished into according to the data bit element quantity that each this transistor can store, SLC) with two kinds of current potential storage modes such as multi-level unit formula (Multi-LevelCell, MLC).This single stage unit formula is in time implementing, and only have the change of two kinds of voltages, namely each this transistor only can store single data bit element, and multi-level unit formula is in time implementing, then can store two to three data bit elements in each this transistor.Therefore, in when using multi-level unit formula to implement, each this transistor can the quantity of storage data bit be the several times implemented with single stage unit formula, and with multi-level unit formula implement its manufacturing cost relative moderate of fast flash memory bank, but this kind embodiment is relatively slow in the reaction velocity of data access, the life-span is lower.But, although the fast flash memory bank implemented with single stage unit formula its have that stability is higher, the reaction velocity of data access is relatively very fast and serviceable life is longer advantage, the capacity density of its institute's energy storage data is lower, makes its manufacturing cost relatively high.
Accordingly, Ge Jia manufacturer proposes the hybrid solid state storage device including single stage unit Middle Eocene storage mode and multi-level unit Middle Eocene storage mode one after another, as TaiWan, China invents I385517 Patent Case, it discloses a kind of storage device, it is the object that the second fast flash memory bank being different from this first fast flash memory bank with one first fast flash memory bank and produces hybrid storage, but this Patent Case needs to buy more two kinds of different types of fast flash memory banks in use, make manufacturing cost still can be limited to the price of the fast flash memory bank of single stage unit Middle Eocene storage mode enforcement, cannot effectively decline.
Summary of the invention
Fundamental purpose of the present invention, is to solve existing solid state storage device only can implement data stability and the amount of data storage produced problem with single current potential storage mode.
For reaching above-mentioned purpose, the invention provides a kind of solid state storage device with mixing storage mode, this solid state storage device includes a fast flash memory bank and a data processing module.Wherein, this fast flash memory bank includes one and stores magnetic region and to be different from the second storage magnetic region of one second current potential storage mode storage data of this first current potential storage mode with first of one first current potential storage mode storage data, this the first storage magnetic region includes M block, this the second storage magnetic region includes N number of block, each this block is a corresponding physical blocks address and a logical block addresses respectively, and this first physical blocks address storing magnetic region is P
0to P
m-1, and this logical block addresses is L
0to L
m-1, this second physical blocks address storing magnetic region is P
mto P
m+N-1, and this logical block addresses is L
mto L
m+N-1.This data processing module is connected with this fast flash memory bank information, has acceptance one instruction and understands this logical block addresses that this instruction comprises and perform the data processing mode of instruction action in this physical blocks address of correspondence.
In an embodiment, this first current potential storage mode is single stage unit formula, and this second current potential storage mode is multi-level unit formula.Further, this data processing module has this logical block addresses that this instruction of a judgement comprises is L
0to L
m-1time the data-modulated pattern that one current potential modulation instruction changes the original current potential storing mode of this instruction is added to this instruction.
In an embodiment, this first current potential storage mode is multi-level unit formula, and this second current potential storage mode is single stage unit formula.Further, this data processing module has this logical block addresses that this instruction of a judgement comprises is L
mto L
m+N-1time the data-modulated pattern that one current potential modulation instruction changes the original current potential storing mode of this instruction is added to this instruction.
In an embodiment, this first data storage capacities storing magnetic region is different from the data storage capacities of this second storage magnetic region.
In an embodiment, this data processing module includes and records this first to store physical blocks address corresponding to magnetic region be P
0to P
m-1and logical block addresses L
0to L
m-1the first corresponding table, and one records this second to store physical blocks address corresponding to magnetic region is P
mto P
m+N-1and logical block addresses L
mto L
m+N-1the second corresponding table.
In an embodiment, this fast flash memory bank more includes one and stores magnetic region with the be different from the 3rd current potential storage mode storage data of this first current potential storage mode and this second current potential storage mode the 3rd, 3rd stores magnetic region includes R block, and the 3rd physical blocks address storing magnetic region is P
nto P
n+R-1, and this logical block addresses is L
nto L
n+R-1.Further, this data processing module includes and records this first to store physical blocks address corresponding to magnetic region be P
0to P
m-1and logical block addresses L
0to L
m-1the first corresponding table, one records this, and second to store physical blocks address corresponding to magnetic region be P
mto P
m+N-1and logical block addresses L
mto L
m+N-1the second corresponding table, and one records the 3rd to store physical blocks address corresponding to magnetic region is P
nto P
n+R-1and logical block addresses L
nto L
n+R-1the 3rd corresponding table.
In an embodiment, this data processing module has one and first stores magnetic region and this second elimination number of times of each this block storing magnetic region according to this and find out one and can record block and to be averaged the average write algorithm of write when this instruction is write data action.
By the above-mentioned embodiment of the present invention, compared to existing, there is following characteristics: the present invention implements with this fast flash memory bank of same transistor varieties, and this fast flash memory bank is divided into this first storage magnetic region and this second storage magnetic region, make this first store magnetic region and this second to store the current potential storing mode that magnetic region uses different, accordingly to provide the solid state storage device of a kind of tool high stability and high data storage capacities.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Accompanying drawing explanation
Fig. 1, the present invention has the unit composition diagram of solid state storage device one embodiment of mixing storage mode;
Fig. 2, the present invention has the fast flash memory bank schematic diagram of solid state storage device one embodiment of mixing storage mode;
Fig. 3, the present invention has the fast flash memory bank schematic diagram of another embodiment of solid state storage device of mixing storage mode.
Embodiment
Relate to detailed description of the present invention and technology contents, the existing accompanying drawing that just coordinates is described as follows:
Refer to Fig. 1 and Fig. 2, the solid state storage device 100 of tool mixing storage mode of the present invention, it consists predominantly of fast flash memory bank 1 and the data processing module 2 be connected with this fast flash memory bank 1 information.Further, this fast flash memory bank 1 of the present invention can be formed by multiple chipset structure, and the transistor varieties of each this chip is identical.In other words, this fast flash memory bank 1 of the present invention only has single kind of current potential storage mode, as multi-level unit formula (Multi-LevelCell, MLC) before not implementing.Again, this fast flash memory bank 1 has multiple block 11, each this block 11 is a corresponding physical blocks address (PhysicalBlockAddress respectively, and a logical block addresses (LogicalBlockAddress PBA), LBA), further, this fast flash memory bank 1 is divided into one first with this logical block addresses and is stored magnetic region 12 and one second storage magnetic region 13 by the present invention, wherein, this the first storage magnetic region 12 includes M block 11, and this physical blocks address corresponding to it is P
0to P
m-1, this logical block addresses is L
0to L
m-1, this second storage 13, magnetic region includes N number of block 11, and this corresponding physical blocks address is then P
mto P
m+N-1, this logical block addresses is L
mto L
m+N-1.
This fast flash memory bank 1 of the present invention from the above only has single kind of current potential storage mode in time not implementing, but the present invention changes the current potential storage mode of a wherein storage magnetic region to simulate another current potential storage mode record data by this data processing module 2 in the process implemented, more specifically illustrate, this the first storage magnetic region 12 of the present invention is with one first current potential storage mode storage data, this the second storage magnetic region 13 is then different from the second current potential storage mode storage data of this first current potential storage mode with one, in an embodiment, this the first current potential storage mode is single stage unit formula (Single-LevelCell, SLC), this the second current potential storage mode is then multi-level unit formula, but the present invention is not as limit, also can be this first current potential storage mode is multi-level unit formula, this the second current potential storage mode is single stage unit formula.Again, this fast flash memory bank 1 of the present invention is behind this first storage magnetic region 12 of differentiation and this second storage magnetic region 13, because this first stores magnetic region 12 second to store the current potential storage mode of magnetic region 13 different with this, data storage capacities of this first storage magnetic region 12 of the present invention is made to be different from the data storage capacities of this second storage magnetic region 13.Illustrate, when this first this first current potential storage mode storing magnetic region 12 is single stage unit formula, each this transistor in each this block 11 in this first storage magnetic region 12 only can record the data of a bit, and making this first data storage capacities storing magnetic region 12 can be less than this second storage magnetic region 13 is the data storage capacities that the second current potential storage mode is implemented with multi-level unit formula.
Hold, this data processing module 2 of the present invention is connected with this fast flash memory bank 1 information, and has an acceptance one instruction D1 and understand this logical block addresses that this instruction comprises and correspond to the data processing mode that this physical blocks address performs instruction action.More specifically illustrate, this solid state storage device 100 of the present invention can be connected with a computer installation 3 (as computing machine), and make this computer installation 3 it be carried out to the action of data write or reading, and alleged this instruction D1 of the present invention sent by this computer installation 3, when this computer installation 3 sends this instruction D1 to this solid state storage device 100, after this data processing module 2 accepts this instruction D1, namely understand this instruction D1 comprise requirement and to perform an action this logical block addresses of affiliated data, and read corresponding data according to this logical block addresses.Further, can be known by above-mentioned, this first current potential storage mode of the present invention can be implemented for multi-level unit formula, and therefore, it is L that this data processing module 2 has more this logical block addresses that this instruction of judgement D1 comprises
0to L
m-1time the data-modulated pattern that one current potential modulation instruction changes the original current potential storing mode of this instruction D1 is added to this instruction D1.In addition, if the present invention is in an embodiment, this second current potential storage mode is when implementing with multi-level unit formula, and this data-modulated pattern that this data processing module 2 has is then this logical block addresses comprised for this instruction D1 is L
mto L
m+N-1in time, implements.Hold, the present invention makes this data processing module 2 have this data-modulated pattern the current potential storage mode of original multi-level unit formula to be modeled to the current potential storage mode of single stage unit formula.Again, this current potential modulation instruction can be a flag instruction or be a paging instruction.
Moreover refer to Fig. 2 again, this data processing module 2 of the present invention more includes and records this first to store this physical blocks address corresponding to magnetic region 12 be P
0to P
m-1and this logical block addresses L
0to L
m-1the first corresponding table T1, and one records this second to store this physical blocks address corresponding to magnetic region 13 is P
mto P
m+N-1and this logical block addresses L
mto L
m+N-1the second corresponding table T2.By this, this physical blocks address of each this logical block addresses and each can complete corresponding by this first corresponding table T1 and this second corresponding table T2 by this data processing module 2 rapidly.Again, data processing module 2 more includes one and first stores magnetic region 12 and this second elimination number of times of each this block 11 storing magnetic region 13 according to this and find out one and can record block and to be averaged the average write algorithm of write when this instruction D1 is write data action.
In addition, and refer to Fig. 3, the present invention is in an embodiment, this fast flash memory bank 2 is except including this first storage magnetic region 12 and this second storage magnetic region 13, more include one and store magnetic region 14 with the be different from the 3rd current potential storage mode storage data of this first current potential storage mode and this second current potential storage mode the 3rd, the physical blocks address that 3rd storage magnetic region 14 includes R block the 11, three storage magnetic region 14 is P
nto P
n+R-1, and this logical block addresses is L
nto L
n+R-1.Illustrate, in the present embodiment, this first current potential storage mode is single stage unit formula, and this second current potential storage mode is multi-level unit formula, and the 3rd current potential storage mode can be then that a three-layer type stores (TLC).Moreover in this embodiment, this data processing module 2, except can comprising this first corresponding table T1 and this second corresponding table T2, more can include and record the 3rd to store this physical blocks address corresponding to magnetic region 14 be P
nto P
n+R-1and this logical block addresses L
nto L
n+R-1the 3rd corresponding table T3.
In sum, the solid state storage device of this tool mixing storage mode of the present invention, primarily of a fast flash memory bank and a data processing module be connected with this fast flash memory bank information.Wherein, this fast flash memory bank includes one and stores magnetic region and with second of one second current potential storage mode storage data the storage magnetic region with first of one first current potential storage mode storage data, and this first physical blocks address storing magnetic region is P
0to P
m-1, logical block addresses is L
0to L
m-1, and this second physical blocks address storing magnetic region is P
mto P
m+N-1, this logical block addresses is L
mto L
m+N-1.This data processing module has this logical block addresses that deciphering one instruction comprises and performs the data processing mode of instruction action in this physical blocks address of correspondence.Accordingly, to provide the solid state storage device of a kind of tool high stability and high data storage capacities.
Certainly; the present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection domain that all should belong to the claim appended by the present invention.
Claims (10)
1. there is a solid state storage device for mixing storage mode, it is characterized in that, include:
One fast flash memory bank, include one and store magnetic region and to be different from the second storage magnetic region of one second current potential storage mode storage data of this first current potential storage mode with first of one first current potential storage mode storage data, this the first storage magnetic region includes M block, this the second storage magnetic region includes N number of block, each this block is a corresponding physical blocks address and a logical block addresses respectively, and this first physical blocks address storing magnetic region is P
0to P
m-1, and this logical block addresses is L
0to L
m-1, this second physical blocks address storing magnetic region is P
mto P
m+N-1, and this logical block addresses is L
mto L
m+N-1; And
One data processing module, is connected with this fast flash memory bank information, has acceptance one instruction and understands this logical block addresses that this instruction comprises and perform the data processing mode of instruction action in this physical blocks address of correspondence.
2. have the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this first current potential storage mode is single stage unit formula, and this second current potential storage mode is multi-level unit formula.
3. have the solid state storage device of mixing storage mode as claimed in claim 2, it is characterized in that, it is L that this data processing module has this logical block addresses that this instruction of a judgement comprises
0to L
m-1time the data-modulated pattern that one current potential modulation instruction changes the original current potential storing mode of this instruction is added to this instruction.
4. have the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this first current potential storage mode is multi-level unit formula, and this second current potential storage mode is single stage unit formula.
5. have the solid state storage device of mixing storage mode as claimed in claim 4, it is characterized in that, it is L that this data processing module has this logical block addresses that this instruction of a judgement comprises
mto L
m+N-1time the data-modulated pattern that one current potential modulation instruction changes the original current potential storing mode of this instruction is added to this instruction.
6. have the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this first data storage capacities storing magnetic region is different from the data storage capacities of this second storage magnetic region.
7. the solid state storage device with mixing storage mode as described in claim 1,2,4 or 6, is characterized in that, this data processing module includes and records this first to store physical blocks address corresponding to magnetic region be P
0to P
m-1and logical block addresses L
0to L
m-1the first corresponding table, and one records this second to store physical blocks address corresponding to magnetic region is P
mto P
m+N-1and logical block addresses L
mto L
m+N-1the second corresponding table.
8. there is the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this fast flash memory bank more includes one and stores magnetic region with the be different from the 3rd current potential storage mode storage data of this first current potential storage mode and this second current potential storage mode the 3rd, 3rd stores magnetic region includes R block, and the 3rd physical blocks address storing magnetic region is P
nto P
n+R-1, and this logical block addresses is L
nto L
n+R-1.
9. have the solid state storage device of mixing storage mode as claimed in claim 8, it is characterized in that, this data processing module includes and records this first to store physical blocks address corresponding to magnetic region be P
0to P
m-1and logical block addresses L
0to L
m-1the first corresponding table, one records this, and second to store physical blocks address corresponding to magnetic region be P
mto P
m+N-1and logical block addresses L
mto L
m+N-1the second corresponding table, and one records the 3rd to store physical blocks address corresponding to magnetic region is P
nto P
n+R-1and logical block addresses L
nto L
n+R-1the 3rd corresponding table.
10. there is the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this data processing module has one and first stores magnetic region and this second elimination number of times of each this block storing magnetic region according to this and find out one and can record block and to be averaged the average write algorithm of write when this instruction is write data action.
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|---|---|---|---|
| CN201410331434.XA CN105320463B (en) | 2014-07-11 | 2014-07-11 | Solid state storage device with mixing storage mode |
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| TW201022933A (en) * | 2008-12-05 | 2010-06-16 | Apacer Technology Inc | Storage device and method of data management |
| CN102279815A (en) * | 2010-06-13 | 2011-12-14 | 宇瞻科技股份有限公司 | Flash-memory-based storage device and data writing method thereof |
| US20130227203A1 (en) * | 2008-11-12 | 2013-08-29 | Micron Technology, Inc. | Dynamic slc/mlc blocks allocations for non-volatile memory |
-
2014
- 2014-07-11 CN CN201410331434.XA patent/CN105320463B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080215800A1 (en) * | 2000-01-06 | 2008-09-04 | Super Talent Electronics, Inc. | Hybrid SSD Using A Combination of SLC and MLC Flash Memory Arrays |
| US20130227203A1 (en) * | 2008-11-12 | 2013-08-29 | Micron Technology, Inc. | Dynamic slc/mlc blocks allocations for non-volatile memory |
| TW201022933A (en) * | 2008-12-05 | 2010-06-16 | Apacer Technology Inc | Storage device and method of data management |
| CN102279815A (en) * | 2010-06-13 | 2011-12-14 | 宇瞻科技股份有限公司 | Flash-memory-based storage device and data writing method thereof |
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