CN105160113A - Efficient CDR verification model and method - Google Patents
Efficient CDR verification model and method Download PDFInfo
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- CN105160113A CN105160113A CN201510581441.XA CN201510581441A CN105160113A CN 105160113 A CN105160113 A CN 105160113A CN 201510581441 A CN201510581441 A CN 201510581441A CN 105160113 A CN105160113 A CN 105160113A
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Abstract
The invention discloses a high-efficiency CDR verification model and a method, which relate to the technical field of EDA verification and comprise a sampling module, a data acquisition module and a data processing module, wherein the sampling module is used for detecting whether serial data input in each half reference period is overturned and recording the overturn time value of the serial data or the current time value after the serial data passes through the half reference period; the tracking module is used for receiving input setting parameters, and the setting parameters comprise a reference period of a serial data recovery clock and a tolerable maximum deviation range of the reference period; the sampling module is also used for storing the time values recorded last two times by the sampling module, calculating the difference value of the time values and calculating the current deviation value according to the difference value and the reference period; updating the cycle of the serial data recovery clock to a reference cycle or the difference value according to whether the current deviation value exceeds the tolerable maximum deviation range; and the clock generation module is used for receiving the updated period of the current serial data recovery clock and generating the serial data recovery clock according to the period.
Description
Technical field
The present invention relates to EDA (ElectronicDesignAutomation, electric design automation) verification technique field, specifically be a kind of CDR (ClockandDataRecovery, clock and data recovery) verification model and method efficiently.
Background technology
Generally all can contain SerDes (SERializer/DESerializer goes here and there and changes device) in network chip, therefore the checking work of network chip be unable to do without the emulation to SerDes model.As everyone knows, the line side of SerDes is serial data, there is no clock signal, SerDes model can simulate the function of actual SerDes really, therefore simulated environment just needs to recover clock from the serial data that SerDes model provides, and what make that the function bus model of environment can be correct adopts data.
The serial data cycle exported due to SerDes model is not invariable, there is the amplitude of oscillation, therefore can not sample to SerDes serial data with the invariable signal consistent with reference to frequency deviation.Conventional way is in verification environment, produce the signal of a frequency than SerDes serial data frequency high several times, then to sample to serial data with this signal and calculates, thus producing corresponding serial clock.
Along with the high speed development of network, single Lane (passage) speed of SerDes is more and more higher, and therefore, existing verification method can not meet the demand to SerDes model serial clock date restoring, and its performance is as follows:
First, real SerDes model also equally with the SerDes of reality can have the process such as calibration, data tracking, although can not deviation be there is in the long run in its data frequency exported, but within a period of time, still there is tolerable deviation range, even during this period of time may cause one or more cycle of deviation, existing CDR verification model may cause the data that recover and clock error.
Second, the present mono-Lane of SerDes the most at a high speed can reach 28G, the single bit data cycle is less than 36ps (Picosecond, psec), make within the same time, need the point of sampling to increase considerably, if adopt existing method multiple repairing weld within a serial data cycle also to record to compare, emulation overhead certainly will will be increased greatly.
3rd, the capacity of present monolithic is increasing, and that is the road of SerDes will become the growth of multiple, uses the method for the CDR verification model of existing poor efficiency can reduce the efficiency of emulation to a great extent.
In a word, existing CDR verification model and method all cannot meet growing network chip verification needs in adaptability, stability and efficiency.
Summary of the invention
For the defect existed in prior art, the object of the present invention is to provide a kind of CDR verification model and method efficiently, this invention ensures that and the real-time follow-up of serial data is sampled, can prevent the serial data that recovers and clock error from producing mistake, in adaptability, stability and efficiency, all meet the needs of network chip verification; Reduce emulation overhead, improve simulation efficiency.
For reaching above object, the technical scheme that the present invention takes is: a kind of CDR verification model efficiently, comprise sampling module, tracking module and clock generating module, wherein, sampling module, whether overturn for detecting the serial data inputted in every half reference cycle, and record serial number is according to the moment value of upset or current moment value after half reference cycle occur; Tracking module, for receiving the parameters of input, parameters comprises the reference cycle of serial data recovered clock and the tolerable maximum deviation scope in this reference cycle; Also for the moment value of nearest twice record of store sample module, and calculate its difference, calculate present deviation value by this difference and reference cycle; Whether exceed tolerable maximum deviation scope according to present deviation value, is updated to reference cycle or this difference the cycle of serial data recovered clock; Clock generating module, for receiving the cycle of the current serial data recovery clock after renewal, and produces serial data recovered clock according to it.
On the basis of technique scheme, the described reference cycle is set to 35ps ~ 1ns.
On the basis of technique scheme, the described reference cycle is set to 80ps.
On the basis of technique scheme, described tolerable maximum deviation scope is set to-1000ppm to+1000ppm.
On the basis of technique scheme, present deviation value=(difference-reference cycle) × 1000000/ reference cycle.
On the basis of technique scheme, whether described tracking module exceeds tolerable maximum deviation scope according to present deviation value, if so, then the cycle of serial data recovered clock is updated to the reference cycle, and sends losing lock alarm; Otherwise the cycle of serial data recovered clock is updated to this difference.
The invention also discloses a kind of efficient CDR verification method based on above-mentioned model, comprise the following steps: step 1. tracking module receives the parameters of input, and parameters comprises the reference cycle of serial data recovered clock and the tolerable maximum deviation scope in this reference cycle; Whether the serial data that step 2. sampling module detects input in current half reference cycle overturns, and record serial number, according to there is the moment value of upset or current moment value after half reference cycle, jumps to step 3; Whether the serial data that step 3. sampling module continues to detect input in follow-up half reference cycle overturns, and record serial number, according to there is the moment value of upset or current moment value after half reference cycle, jumps to step 4; The moment value of nearest twice record of step 4. tracking module store sample module, and calculate its difference, and then calculate present deviation value by this difference and reference cycle, jump to step 5; Step 5. tracking module judges whether present deviation value exceeds tolerable maximum deviation scope, if so, then the cycle of current serial data recovery clock is updated to the reference cycle, and sends losing lock alarm, jump to step 6; Otherwise, the cycle of current serial data recovery clock is updated to this difference, jumps to step 6; Step 6. clock generating module receives the cycle of the current serial data recovery clock after upgrading, and produces serial data recovered clock according to it, is back to step 3.
On the basis of technique scheme, the idiographic flow of step 2 is: whether the serial data that step 21. sampling module detects input in current half reference cycle overturns; If so, step 22 is jumped to; Otherwise, jump to step 23; Step 22. record serial number, according to the moment value that upset occurs, jumps to step 3; Step 23. records current moment value after half reference cycle, jumps to step 3.
On the basis of technique scheme, the idiographic flow of step 3 is: whether the serial data that step 31. sampling module continues to detect input in follow-up half reference cycle overturns; If so, step 32 is jumped to; Otherwise, jump to step 33; Step 32. record serial number, according to the moment value that upset occurs, jumps to step 4; Step 33. records current moment value after half reference cycle, jumps to step 4.
On the basis of technique scheme, the idiographic flow of step 5 is: step 51. tracking module judges whether present deviation value exceeds tolerable maximum deviation scope, if so, jumps to step 52; Otherwise, jump to step 53; The cycle of current serial data recovery clock is updated to the reference cycle by step 52., and sends losing lock alarm, jumps to step 6; The cycle of current serial data recovery clock is updated to this difference by step 53., jumps to step 6.
Beneficial effect of the present invention is:
1, the present invention is by arranging sampling module, tracking module and clock generating module, dynamic conditioning serial data recovered clock can follow the tracks of the mechanical periodicity situation of serial data: when upset does not occur serial data, serial data recovered clock will continue to use the recovered clock cycle of last time, when upset occurs serial data, the cycle of serial data recovered clock will be upgraded.Ensure that and the real-time follow-up of serial data is sampled, can prevent the serial data that recovers and clock error from producing mistake, in adaptability, stability and efficiency, all meet the needs of network chip verification.
2, the present invention only introduces this variable of cycle of serial data recovered clock, do not introduce new clock signal, within of a SerDes model serial data cycle, only need carrying out at most a sampling and compare, because this reducing emulation overhead, improve simulation efficiency.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of efficient CDR verification model in the embodiment of the present invention;
Fig. 2 is the process flow diagram of efficient CDR verification method in the embodiment of the present invention;
Fig. 3 is the example waveform figure of efficient CDR verification model in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Shown in Figure 1, embodiments provide a kind of CDR verification model efficiently, comprise sampling module, tracking module and clock generating module, wherein, sampling module is connected with clock generating module with tracking module respectively, and tracking module is connected with clock generating module.
Whether sampling module, overturn for detecting the serial data inputted in every half reference cycle, and record serial number is according to the moment value of upset or current moment value after half reference cycle occur.
Tracking module, for receiving the parameters of input, parameters comprises the reference cycle of serial data recovered clock and the tolerable maximum deviation scope in this reference cycle; Reference cycle is set to 35ps ~ 1ns (the SerDes model of corresponding existing 28G ~ 1G), and tolerable maximum deviation scope is set to-1000ppm (partpermillion, 1,000,000/) to+1000ppm.Preferably, the reference cycle is set to 80ps.Tracking module also for the moment value of nearest twice record of store sample module, and calculates its difference, calculates present deviation value by this difference and reference cycle; Wherein, present deviation value=(difference-reference cycle) × 1000000/ reference cycle.Whether exceed tolerable maximum deviation scope according to present deviation value, is updated to reference cycle or this difference the cycle of serial data recovered clock; Concrete, whether tracking module exceeds tolerable maximum deviation scope according to present deviation value, if so, then the cycle of serial data recovered clock is updated to the reference cycle, and sends losing lock alarm, reminds operating personnel to safeguard; Otherwise the cycle of serial data recovered clock is updated to this difference.
Clock generating module, for receiving the cycle of the current serial data recovery clock after renewal, and produces serial data recovered clock according to it.
Shown in Figure 2, the embodiment of the present invention also provides a kind of efficient CDR verification method based on above-mentioned model, specifically comprises the following steps:
Step S1. tracking module receives the parameters of input, and parameters comprises the reference cycle of serial data recovered clock and the tolerable maximum deviation scope in this reference cycle.Reference cycle is set to 35ps ~ 1ns, and tolerable maximum deviation scope is set to-1000ppm to+1000ppm.Preferably, the reference cycle is set to 80ps.
Step S2. sampling module every half reference cycle once samples, and whether the serial data detecting input in current half reference cycle overturns; If so, step S3 is jumped to; Otherwise, jump to step S4.
Step S3. record serial number, according to the moment value that upset occurs, jumps to step S5.
Step S4. records current moment value after half reference cycle, jumps to step S5.
Whether the serial data that step S5. sampling module continues to detect input in follow-up half reference cycle overturns; If so, step S6 is jumped to; Otherwise, jump to step S7.
Step S6. record serial number, according to the moment value that upset occurs, jumps to step S8.
Step S7. records current moment value after half reference cycle, jumps to step S8.
The moment value of nearest twice record of step S8. tracking module store sample module, and calculate its difference, and then calculate present deviation value by this difference and reference cycle, jump to step S9.Concrete, present deviation value=(difference-reference cycle) × 1000000/ reference cycle.
Step S9. tracking module judges whether present deviation value exceeds tolerable maximum deviation scope, if so, jumps to step S10; Otherwise, jump to step S11.
The cycle of current serial data recovery clock is updated to the reference cycle by step S10., and sends losing lock alarm, reminds operating personnel to safeguard, jumps to step S12.
The cycle of current serial data recovery clock is updated to this difference by step S11., jumps to step S12.
Step S12. clock generating module receives the cycle of the current serial data recovery clock after upgrading, and produces serial data recovered clock according to it, is back to step S5.
With the example waveform figure of 12.5GCDR model, the present invention will be further described below.
Shown in Figure 3, for intercepting the result of one section of simulation time, the cycle (DATA) of serial data is in the fluctuation having ± 25ppm (± 0.002ps) sometime, finally be stabilized on 80.002ps, by the CDR verification model of the present embodiment, the recovered clock (CLKCDR) exported has corresponding swing when serial data cyclic swing, because the recovered clock exported is in the stage casing of data, therefore ensures that little swing can not cause the reception of error in data; After the serial data cycle is finally stabilized in 80.002ps, the recovered clock cycle is also stabilized in 2 bat 80.003ps, 1 and claps on 80.002ps, 2 bat 80.001ps, on average gets off for 80.002ps, therefore, has well followed the tracks of the cycle of serial data.
The present invention is not limited to above-mentioned embodiment, and for those skilled in the art, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications are also considered as within protection scope of the present invention.The content be not described in detail in this instructions belongs to the known prior art of professional and technical personnel in the field.
Claims (10)
1. an efficient CDR verification model, is characterized in that: comprise sampling module, tracking module and clock generating module, wherein,
Whether sampling module, overturn for detecting the serial data inputted in every half reference cycle, and record serial number is according to the moment value of upset or current moment value after half reference cycle occur;
Tracking module, for receiving the parameters of input, parameters comprises the reference cycle of serial data recovered clock and the tolerable maximum deviation scope in this reference cycle;
Also for the moment value of nearest twice record of store sample module, and calculate its difference, calculate present deviation value by this difference and reference cycle; Whether exceed tolerable maximum deviation scope according to present deviation value, is updated to reference cycle or this difference the cycle of serial data recovered clock;
Clock generating module, for receiving the cycle of the current serial data recovery clock after renewal, and produces serial data recovered clock according to it.
2. CDR verification model efficiently as claimed in claim 1, is characterized in that: the described reference cycle is set to 35ps ~ 1ns.
3. CDR verification model efficiently as claimed in claim 2, is characterized in that: the described reference cycle is set to 80ps.
4. CDR verification model efficiently as claimed in claim 1, is characterized in that: described tolerable maximum deviation scope is set to-1000ppm to+1000ppm.
5. CDR verification model efficiently as claimed in claim 1, is characterized in that: present deviation value=(difference-reference cycle) × 1000000/ reference cycle.
6. CDR verification model efficiently as claimed in claim 1, it is characterized in that: whether described tracking module exceeds tolerable maximum deviation scope according to present deviation value, if so, then the cycle of serial data recovered clock is updated to the reference cycle, and sends losing lock alarm; Otherwise the cycle of serial data recovered clock is updated to this difference.
7., based on the efficient CDR verification method of model described in claim 1, it is characterized in that, comprise the following steps:
Step 1. tracking module receives the parameters of input, and parameters comprises the reference cycle of serial data recovered clock and the tolerable maximum deviation scope in this reference cycle;
Whether the serial data that step 2. sampling module detects input in current half reference cycle overturns, and record serial number, according to there is the moment value of upset or current moment value after half reference cycle, jumps to step 3;
Whether the serial data that step 3. sampling module continues to detect input in follow-up half reference cycle overturns, and record serial number, according to there is the moment value of upset or current moment value after half reference cycle, jumps to step 4;
The moment value of nearest twice record of step 4. tracking module store sample module, and calculate its difference, and then calculate present deviation value by this difference and reference cycle, jump to step 5;
Step 5. tracking module judges whether present deviation value exceeds tolerable maximum deviation scope, if so, then the cycle of current serial data recovery clock is updated to the reference cycle, and sends losing lock alarm, jump to step 6; Otherwise, the cycle of current serial data recovery clock is updated to this difference, jumps to step 6;
Step 6. clock generating module receives the cycle of the current serial data recovery clock after upgrading, and produces serial data recovered clock according to it, is back to step 3.
8. CDR verification method efficiently as claimed in claim 7, it is characterized in that, the idiographic flow of step 2 is:
Whether the serial data that step 21. sampling module detects input in current half reference cycle overturns; If so, step 22 is jumped to; Otherwise, jump to step 23;
Step 22. record serial number, according to the moment value that upset occurs, jumps to step 3;
Step 23. records current moment value after half reference cycle, jumps to step 3.
9. CDR verification method efficiently as claimed in claim 7, it is characterized in that, the idiographic flow of step 3 is:
Whether the serial data that step 31. sampling module continues to detect input in follow-up half reference cycle overturns; If so, step 32 is jumped to; Otherwise, jump to step 33;
Step 32. record serial number, according to the moment value that upset occurs, jumps to step 4;
Step 33. records current moment value after half reference cycle, jumps to step 4.
10. CDR verification method efficiently as claimed in claim 7, it is characterized in that, the idiographic flow of step 5 is:
Step 51. tracking module judges whether present deviation value exceeds tolerable maximum deviation scope, if so, jumps to step 52; Otherwise, jump to step 53;
The cycle of current serial data recovery clock is updated to the reference cycle by step 52., and sends losing lock alarm, jumps to step 6;
The cycle of current serial data recovery clock is updated to this difference by step 53., jumps to step 6.
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| CN111371523A (en) * | 2018-12-25 | 2020-07-03 | 深圳市中兴微电子技术有限公司 | Clock signal processing device and method |
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