CN104050128A - High-speed clock data restoring circuit for USB (Universal Serial Bus) 2.0 - Google Patents
High-speed clock data restoring circuit for USB (Universal Serial Bus) 2.0 Download PDFInfo
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- CN104050128A CN104050128A CN201310078979.XA CN201310078979A CN104050128A CN 104050128 A CN104050128 A CN 104050128A CN 201310078979 A CN201310078979 A CN 201310078979A CN 104050128 A CN104050128 A CN 104050128A
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Abstract
The invention discloses a high-speed clock data restoring circuit for USB (Universal Serial Bus) 2.0. The high-speed clock data restoring circuit comprises a sampling circuit, a data decision circuit and an elastic buffer circuit, wherein the sampling circuit is used for sampling serial data within a 1bit period for five times, so as to obtain 5bit data and transmitting the 5bit data to the data decision circuit; the data decision circuit is used for generating 1bit data and a data control signal according to the input 5bit data and then sending the 1bit data and the data control signal to the elastic buffer circuit; the elastic buffer circuit is used for compensating data clock difference of a transceiving end and processing the input 1bit data under the control of the data control signal, so as to obtain restored serial data. By using the high-speed clock data restoring circuit, the tolerance of data deviation of plus or minus 40% at most can be realized, thereby correctly restoring data.
Description
Technical field
The present invention relates to USB(Universal Serial Bus USB (universal serial bus)) field, particularly relate to a kind of for USB2.0 clock data recovery circuit at a high speed.
Background technology
It is faster that USB interface has transmission speed, supports hot plug and the feature that connects a plurality of equipment.In all kinds of external units, adopted widely at present, become one of interfacing equipment being most widely used.USB2.0 host-host protocol at a high speed supported widely, and various movable storage devices nearly all can support USB2.0 at a high speed, apply very extensive.Usb protocol can be realized unclocked data transmission, in the correct recovery data of receiving end, is piths that usb protocol is realized.Wherein, clock data recovery circuit is the requisite ingredient of USB2.0 high speed.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of for USB2.0 clock data recovery circuit at a high speed, can realize the tolerance of the data deviation of maximum ± 40%, therefrom correct recovery data.
For solving the problems of the technologies described above, of the present invention for USB2.0 clock data recovery circuit at a high speed, comprising:
Sample circuit, samples in the cycle and obtains 5bit data 5 times at 1bit serial data, and is sent to data judging circuit;
Described data judging circuit, according to the 5bit data of input, generates 1bit data and data controlling signal, is then sent into elastic buffer circuit;
Described elastic buffer circuit, for compensating the data clock difference of sending and receiving end; Under the control of described data controlling signal, the 1bit data of input are processed to the serial data that is restored out.
The present invention is based on USB2.0 over-sampling implementation at a high speed, by the judgement of over-sampling data is therefrom extracted to clock information, and recover correct data.The present invention is by retaining last sample information, in conjunction with current sample information, judge, by compensation data, cross or delete, can tolerate to be up to ± 40% data width error, the very effective interference being tolerated under various transmission environments, is guaranteed the correct transmission of data.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is clock data recovery circuit theory diagram;
Fig. 2 is data judging schematic block circuit diagram in Fig. 1;
Fig. 3 is Fig. 1 Elastic buffer circuit theory diagram;
Fig. 4 is data selection algorithm schematic diagram.
Embodiment
Shown in Figure 1, described clock data recovery circuit, comprising: sample circuit, data judging circuit, elastic buffer circuit.
Described sample circuit, to serial data at 1bit(bit) in the cycle sampling obtain 5bit data 5 times, and sent to described data judging circuit.
Described data judging circuit, according to the 5bit data of input, generates 1bit data and data controlling signal, then sends into described elastic buffer circuit.
Described elastic buffer circuit, for compensating the data clock difference of sending and receiving end; Under the control of described data controlling signal, the 1bit data of input are processed to the serial data that is restored out.
Shown in Fig. 2, described data judging circuit, comprising: Data flipping decision circuit, Data flipping is preserved circuit, data phase selector switch and data selector.
Whether described Data flipping decision circuit, there is the Data flipping between 0,1 according to the 5bit data judging of input, if there is Data flipping, produces Data flipping information and sent to Data flipping and preserve circuit and data phase selector switch; The 5bit data of input are sent in described data selector and wait for and selecting.
Described Data flipping is preserved circuit, and described Data flipping information is preserved.
Described data phase selector switch, the last Data flipping information of preserving according to described Data flipping preservation circuit and current Data flipping information are calculated the data select signal of current data and are sent to described data selector, and the output of generated data control signal.If there is not Data flipping, continue to use last data select signal.Described data controlling signal comprises " increase, reduce, be constant " three kinds of information.
Described data selector is selected the output of 1bit data in 5bit data according to described data select signal.
In conjunction with shown in Fig. 3, described elastic buffer circuit, comprises elastic buffer and mask logic circuit again.
Described elastic buffer carries out buffer memory to the 1bit data of the data selector output of described data judging circuit, and under the control of described data controlling signal, these 1bit data are carried out data increase or removed, then data are exported to described mask logic circuit.
The data that described mask logic circuit is not exported described elastic buffer make zero, and then carry out XOR and are integrated into 1bit data, the serial data output that is restored out.
Shown in Figure 4, the method that described data judging circuit carries out data judging is as follows:
Definition D4～D0 is sampled data, and wherein D4 is sampled data the earliest, and D0 is last sampled data, and D0 ' is the D0 data of last last sampling.P4～P0 is Data flipping information.P4=D0 ' XOR D4 wherein, P3=D4 XOR D3, P2=D3 XOR D2, P1=D2 XOR D1, P0=D1 XOR D0.The upset information that P4 '～P0 ' obtains for last sampling.
Sampling principle is as follows, from left to right searches P4～P0, first occurs 1 the upset that predicates, and then generated data is selected signal.P4=1, selects D2; P3=1, selects D1; P2=1, selects D0; P1=1, selects D4; P0=1, selects D3; If P4～P0 is 0, data select signal is constant.When P4～P0 searches from left to right, P4 '～P0 ' searches from right to left.If P0 '=1, first P2 is 1 simultaneously, and the data controlling signal generating is " increase "; If P1 '=1, first P3 or P2 are 1 simultaneously, and the data controlling signal generating is " increase "; If P2 '=1, first P1 or P0 are 1 simultaneously, and the data controlling signal generating is " minimizing "; If P3 '=1, first P1 is 1 simultaneously, and the data controlling signal generating is " minimizing "; The data controlling signal that other situations generate is " constant ".
By embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. for a USB2.0 clock data recovery circuit at a high speed, it is characterized in that, comprising:
Sample circuit, samples in the cycle and obtains 5bit data 5 times at 1bit serial data, and is sent to data judging circuit;
Described data judging circuit, according to the 5bit data of input, generates 1bit data and data controlling signal, is then sent into elastic buffer circuit;
Described elastic buffer circuit, for compensating the data clock difference of sending and receiving end; Under the control of described data controlling signal, the 1bit data of input are processed to the serial data that is restored out.
2. clock data recovery circuit as claimed in claim 1, is characterized in that, described data judging circuit, comprising:
Whether Data flipping decision circuit, there is the Data flipping between 0,1 according to the 5bit data judging of input, if there is Data flipping, produces Data flipping information and sent to Data flipping and preserve circuit and data phase selector switch; The 5bit data of input are sent in data selector and wait for and selecting;
Described Data flipping is preserved circuit, and described Data flipping information is preserved;
Described data phase selector switch, the last Data flipping information of preserving according to described Data flipping preservation circuit and current Data flipping information are calculated the data select signal of current data and are sent to described data selector, and the output of generated data control signal; If there is not Data flipping, continue to use last data select signal;
Described data selector is selected the output of 1bit data in 5bit data according to described data select signal.
3. clock data recovery circuit as claimed in claim 1, is characterized in that: described data controlling signal comprises " increase, reduce, be constant " three kinds of information.
4. as the clock data recovery circuit as described in arbitrary in claims 1 to 3, it is characterized in that, described elastic buffer circuit, comprising:
Elastic buffer, carries out buffer memory to the 1bit data of the data selector output of described data judging circuit, and under the control of described data controlling signal, these 1bit data is carried out data increase or removed, and then data is exported to mask logic circuit;
Described mask logic circuit, the data that described elastic buffer is not exported make zero, and then carry out XOR and are integrated into 1bit data, the serial data output that is restored out.
5. as the clock data recovery circuit as described in arbitrary in claims 1 to 3, it is characterized in that, described data judging circuit carries out data judging in the following way:
Definition D4～D0 is sampled data, and wherein, D4 is sampled data the earliest, and D0 is last sampled data, and D0 ' is the D0 data of last last sampling; P4～P0 is Data flipping information, P4=D0 ' XOR D4 wherein, P3=D4 XOR D3, P2=D3 XOR D2, P1=D2 XOR D1, P0=D1 XOR D0; The upset information that P4 '～P0 ' obtains for last sampling;
Sampling principle is as follows, from left to right searches P4～P0, first occurs 1 the upset that predicates, and then generated data is selected signal; P4=1, selects D2; P3=1, selects D1; P2=1, selects D0; P1=1, selects D4; P0=1, selects D3; If P4～P0 is 0, data select signal is constant;
When P4～P0 searches from left to right, P4 '～P0 ' searches from right to left, if P0 '=1, first P2 is 1 simultaneously, and the data controlling signal generating is " to increase; If P1 '=1, first P3 or P2 are 1 simultaneously, and the data controlling signal generating is " increase "; If P2 '=1, first P1 or P0 are 1 simultaneously, and the data controlling signal generating is " minimizing "; If P3 '=1, first P1 is 1 simultaneously, and the data controlling signal generating is " minimizing "; The data controlling signal that other situations generate is " constant ".
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310078979.XA CN104050128A (en) | 2013-03-13 | 2013-03-13 | High-speed clock data restoring circuit for USB (Universal Serial Bus) 2.0 |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310078979.XA CN104050128A (en) | 2013-03-13 | 2013-03-13 | High-speed clock data restoring circuit for USB (Universal Serial Bus) 2.0 |
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| CN104050128A true CN104050128A (en) | 2014-09-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105160113A (en) * | 2015-09-11 | 2015-12-16 | 烽火通信科技股份有限公司 | Efficient CDR verification model and method |
| WO2020151698A1 (en) * | 2019-01-22 | 2020-07-30 | 华为技术有限公司 | Driver and data transmission method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6545507B1 (en) * | 2001-10-26 | 2003-04-08 | Texas Instruments Incorporated | Fast locking CDR (clock and data recovery circuit) with high jitter tolerance and elimination of effects caused by metastability |
| CN102457261A (en) * | 2010-10-15 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Glitch-free oversampling clock and data recovery |
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2013
- 2013-03-13 CN CN201310078979.XA patent/CN104050128A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6545507B1 (en) * | 2001-10-26 | 2003-04-08 | Texas Instruments Incorporated | Fast locking CDR (clock and data recovery circuit) with high jitter tolerance and elimination of effects caused by metastability |
| CN102457261A (en) * | 2010-10-15 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Glitch-free oversampling clock and data recovery |
Non-Patent Citations (1)
| Title |
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| 李浩亮: ""基于USB2.0的高速串行通信接口电路设计技术研究"", 《中国博士学位论文全文数据库 信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105160113A (en) * | 2015-09-11 | 2015-12-16 | 烽火通信科技股份有限公司 | Efficient CDR verification model and method |
| CN105160113B (en) * | 2015-09-11 | 2018-08-21 | 烽火通信科技股份有限公司 | Efficient CDR verification system and method |
| WO2020151698A1 (en) * | 2019-01-22 | 2020-07-30 | 华为技术有限公司 | Driver and data transmission method |
| US11973856B2 (en) | 2019-01-22 | 2024-04-30 | Huawei Technologies Co., Ltd. | Drive and data transmission method |
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