CN105141352B - A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method - Google Patents
A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method Download PDFInfo
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Abstract
A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method, the present invention relates to satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method.The invention aims to solve the problems, such as that the satellite data transmission data system performance that the prior art is made of under the conditions of high code check Bit Error Ratio Measurement, frame identification classification and VCID sequences is low.It is achieved through the following technical solutions：A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system, it is characterised in that it includes：Front end for being cached to input data caches fifo module；For comparing statistical module to error code of the input data by bit comparisons；Frame for the extraction of identical VCID data frame classifications identifies sort module；For the VCID combining modules to same VCID data sortings；For the data buffer storage fifo module cached to output data.The present invention is applied to satellite data transmission technical field.
Description
Technical field
The present invention relates to satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method.
Background technology
The progress of human society and the development of Space Science and Technology are closely bound up, and satellite and its system are in broadcast communication, gas
As the field such as research forecast, resource exploration, military surveillance, communications and transportation, disaster alarm and agricultural planting play it is important
Effect.Satellite reconaissance (observation) obtain information it is quick, it is accurate, contain much information, have not available for other information obtaining means
Advantage.Current each state is all greatly developing the satellite of this country and its application, and satellite in orbit quantity is increasingly huge, and satellite species is into more
Sample, satellite function are gradually enriched, and satellite development has also moved towards commercialization, civil nature from Military Application.
Satellite implements target using satellite borne sensor the data that observation is formed, and is that shape is presented in the basic of satellite science data
Formula, as satellite species is on the increase, function is increasingly abundanter, and the species of load also becomes increasingly abundant on star, the data volume of load
Follow the performance boost of satellite and sharply increase.The transmission of satellite load data be satellite carry out acquisition of information, transmission, processing and
Using indispensable intermediate channel.Load data amount gradually increases, but the window time of satellite data transmission does not increase
Add, therefore it is to improve satellite data transmission (referred to as " satellite data transmission ") that earth station, which successfully obtains information maximally efficient mode,
Speed, satellite data transmission speed lifted to current Gbps ranks from past Mbps ranks.In order to preferably solve sky
Between information processing with ground and transmission problem, Nasa the main space state such as European Space Agency and is organized in
Nineteen eighty-two has set up consultative committee for space data system (Consulative Committee for Space Data
System, CCSDS).Using the satellite data transmission system of the CCSDS AOS standards suggested, data transfer to earth station, floor treatment
The base band data that system needs radio demodulating carries out frame head synchronization, Bit Error Ratio Measurement, frame identification classification, data unpacking, solution
It after the processing procedures such as compression storage, display, could be identified by load user, be used for data processing centre for analysis.
It is continuously improved as number passes data bit rate so that the frame identification classification of the bit levels of high bit rate and VCID rows
Sequence difficulty increases, and becomes a key factor of restricting current satellite data disposal ability lifting；Meanwhile bit grades of satellite data
The statistical analysis of the bit error rate, is to improve satellite channel link-quality, analyzes the important means of Data transfer system performance.For input
The different virtual channel datas mixed in different physical channels are handled, after identical tunnel extraction is carried out, due to number
According to from different physical channel receptions, the data frame for causing input is to be passed under frame count confusion in time, simultaneously because channel
The influence of performance, there are following special pattern for data frame count：There are frame count hopping amplitude is excessive, more than defined step-out model
Enclose；Due to counter overflow or mass data frame loss, there is normal huge step in frame count, causes under the conditions of high code check
The satellite data transmission data pretreatment performance being made of Bit Error Ratio Measurement, frame identification classification and VCID sequences is low, therefore, improves
The performance for the satellite data transmission data system being made of under the conditions of high code check Bit Error Ratio Measurement, frame identification classification and VCID sequences is straight
Connect the performance for affecting satellite data transmission system.
The content of the invention
The invention aims to solve the prior art under the conditions of high code check by Bit Error Ratio Measurement, frame identification classification and
The problem of satellite data transmission data system performance of VCID sequence compositions is low, and a kind of satellite high-speed digital transmission base band data error code is provided
Statistics and frame sequence processing system and method.
The technical scheme is that：
A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system, it is characterised in that it includes：
Front end for being cached to input data caches fifo module；
For comparing statistical module to error code of the input data by bit comparisons；
Frame for the extraction of identical VCID data frame classifications identifies sort module；
For the VCID combining modules to same VCID data sortings；
For the data buffer storage fifo module cached to output data.
A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing method, it is characterised in that it includes：
Front end for being cached to input data caches FIFO steps；
For comparing statistic procedure to error code of the input data by bit comparisons；
Frame for the extraction of identical VCID data frame classifications identifies classifying step；
For the VCID combining steps to same VCID data sortings；
For the data buffer storage FIFO steps cached to output data.
Invention effect
A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method using the present invention are right
Error code comparison is carried out in any bit in a frame data and counts comparison result, since input data is parallel data, to do
Can be set to data bits, treated under different clocks it is more different than data bits, while will within a clock by one simultaneously
The result of all bits of row data is counted, with the following method：1) bit compared as needed is by input data
Pre-processed, step-by-step and operation will be carried out to each data to be compared in each clock according to normal data, need not
The data being compared are carried out with 0 operation, it is necessary to which the progress of comparison data position and 1 operation, realize data bit mask selection function；2)
Count, all bits of a parallel data are summed in a clock, using decrease for comparing result
Wide flowing water adder, realizes the comparison result statistics in a clock；It is excessive for existing frame count hopping amplitude, exceed
Defined step-out scope；Counter overflow or mass data frame loss, cause frame count normal huge step problem, root occur
Frame count is stored when factually, is continuously read according to physical address and designs relevant control state machine；Solve existing
The satellite data transmission data prediction system that technology is made of under the conditions of high code check Bit Error Ratio Measurement, frame identification classification and VCID sequences
The problem of performance of uniting is low, makes to be made of Bit Error Ratio Measurement, frame identification classification and VCID sequences under the conditions of the high code check based on FPGA
Satellite data transmission data pretreatment its speed can reach 4*2.5Gbps.
Brief description of the drawings
Fig. 1 is a kind of satellite high-speed digital transmission base band data Bit Error Code Statistics of the present invention and frame sequence processing system overall plan frame
Figure, 1 caches fifo module for front end, and 2 compare statistical module for error code, and 3 identify sort module for frame, and 4 be VCID combining modules,
5 be data buffer storage fifo module；
Fig. 2 compares statistical module single channel design frame chart for error code；
Fig. 3 identifies sort module design frame chart for frame；
Fig. 4 is VCID combining module single channel conceptual design block diagrams；
Fig. 5 is flowing water Bit Error Code Statistics adder figure；
Fig. 6 compares statistical module state machine diagram for error code；
Fig. 7 a show test data error code digit figure for simulation result；
Fig. 7 b compare statistical module simulation result figure for error code；
Fig. 8 identifies sort module state machine diagram for frame；
Fig. 9 identifies sort module simulation result figure for frame
Figure 10 is VCID combining writing module state machine diagrams；
Figure 11 is VCID combining read through model write address state machine diagrams；
Figure 12 reads data state figure for VCID combinings read through model；
Figure 13 a show test data for simulation result；
Figure 13 b are normal mode of operation analogous diagram；
Figure 14 counts the stability simulation figure that becomes larger for frame losing；
Figure 15 recovers analogous diagram after being disturbed saltus step for frame count value；
Figure 16 is disturbed multiple saltus step analogous diagram for frame count；
Figure 17 expires analogous diagram for frame count meter；
Figure 18 for frame count be disturbed diminish after recover analogous diagram.
Embodiment
Embodiment one：Illustrate present embodiment, a kind of satellite high-speed digital transmission base band data error code with reference to Fig. 1
Statistics and frame sequence processing system, it includes：
For the front end caching fifo module (1) cached to input data；
For comparing statistical module (2) to error code of the input data by bit comparisons；
Frame identification sort module (3) for the extraction of identical VCID data frame classifications；
For the VCID combinings module (4) to same VCID data sortings；
For the data buffer storage fifo module (5) cached to output data.
Embodiment two：Present embodiment is described further embodiment one, error code described in present embodiment
Comparing statistical module (2) includes：
For the module compared by turn that input data is compared by bit；
Random access memory (RAM) module for the comparison data for storing standard；
For the data after being compared by bit to be carried out with the Bit Error Code Statistics module of Bit Error Code Statistics；
For the data buffer storage fifo module cached to input data.
Embodiment three：Present embodiment is described further embodiment one, and frame described in present embodiment is known
Other sort module (3) includes：
Module for the channel selecting made choice to front passage input data；
For identifying sort module to the VCID of input data identification classification according to (tunnel value) VCID, according to VCID
Identify sort module recognition result；If VCID values are correct, input data is cached in VCID FIFO；If VCID value mistakes, right
Input data is abandoned.
Embodiment four：Present embodiment is described further embodiment one, VCID described in present embodiment
Combining module (4) includes：
For the combining sorting module being ranked up according to the VCID Counter Values of input data；
For selector (MUX) module made choice according to combining sorting module control signal to front end data；
For controlling the data flow control module of data flow according to combining sorting module control signal；
For the step-out data buffer storage fifo module cached to continuous step-out data；
The data read module for being read out caching for completing data to sequence；
For handling the data buffer storage fifo module for completing data and carrying out caching and being used for rear module.
Embodiment five：A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing method, it is wrapped
Include：
Front end for being cached to input data caches FIFO steps；
For comparing statistic procedure to error code of the input data by bit comparisons；
Frame for the extraction of identical VCID data frame classifications identifies classifying step；
For the VCID combining steps to same VCID data sortings；
For the data buffer storage FIFO steps cached to output data.
Embodiment six：Present embodiment is described further embodiment five, error code described in present embodiment
Comparing statistic procedure includes：
For input data is compared by bit comparison by turn the step of；
Random access memory (RAM) step for the comparison data for storing standard；
For the data after being compared by bit to be carried out with the Bit Error Code Statistics step of Bit Error Code Statistics；
For the data buffer storage FIFO steps cached to input data.
Embodiment seven：Present embodiment is described further embodiment five, and frame described in present embodiment is known
Other classifying step includes：
For front passage input data is made choice channel selecting the step of,
For identifying classifying step to the VCID of input data identification classification according to (tunnel value) VCID, according to VCID
Identify sort module recognition result；If VCID values are correct, input data is cached in VCID FIFO；If VCID value mistakes, right
Input data is abandoned.
Embodiment eight：Present embodiment is described further embodiment five, VCID described in present embodiment
Combining step includes：
For the combining sequence step being ranked up according to the VCID Counter Values of input data；
For selector (MUX) step made choice according to combining sorting module control signal to front end data；
For controlling the data flow rate-determining steps of data flow according to combining sorting module control signal；
For the step-out data buffer storage FIFO steps cached to continuous step-out data；
The data reading step for being read out caching for completing data to sequence；
For handling the data buffer storage FIFO steps for completing data and carrying out caching and being used for rear module.
Embodiment
A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system, it is characterised in that it includes：
For the front end caching fifo module (1) cached to input data；
For comparing statistical module (2) to error code of the input data by bit comparisons；
Frame identification sort module (3) for the extraction of identical VCID data frame classifications；
For the VCID combinings module (4) to same VCID data sortings；
For the data buffer storage fifo module (5) cached to output data.
A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing method, it is characterised in that it includes：
Front end for being cached to input data caches FIFO steps；
For comparing statistic procedure to error code of the input data by bit comparisons；
Frame for the extraction of identical VCID data frame classifications identifies classifying step；
For the VCID combining steps to same VCID data sortings；
For the data buffer storage FIFO steps cached to output data.
Front end caching fifo module realizes the caching to input data, ensures in data processing, input port number
According to continuity, smoothed data flow velocity rate, improves system to bursty data disposal ability, and transmits data to subsequent module progress
Processing.
Bit Error Ratio Measurement module realized to input data by the comparison of bit, to comparison result progress error code digit statistics,
According to the transmission performance of analysis of statistical results Data transfer system, and transmit data to subsequent module and handled.
Frame identification sort module realizes the classification extraction of identical VCID data frames, fills the discarding of frame data, makes same
VCID frame data are stored in same buffering area, easy to follow-up VCID combinings.
VCID combinings module realizes the ranking function to same VCID data, and out of order frame data are ranked up, make it
Used as continuous frame data for other systems.
Rear end caching fifo module realizes the caching to output data, ensures in data processing, output port number
According to
Error code compares statistical module according to standard comparison frame data and compares the mistake of position to input data progress by turn
Code compares and counts the error code digit of frame data.Standard frame Data Data is pre-written into RAM, and a frame data are length
1024btye, the system data bit width are 256bit, and the comparison position in data frame can configure, and module is according to comparing position start-stop
Signal compares input data by turn, counts the summation of different digit, after having compared a frame data, data buffer storage to FIFO
In, it is output in frame classification identification module, error code digit summation is set in the register of 64 bit wides.
This module is handled using four path parallel, its single channel conceptual design is as shown in Figure 2.
System handles data frame by frame, and module data bit wide is 256, and module data is inputted by front end FIFO, single
Frame data processing needs to read 32 times, compares start-stop position by PCIe register input controls.According to compare position control signal,
The standard comparison data (sample frame) being temporarily stored into RAM are compared module by turn with the data inputted, and comparison result carries out
Bit Error Code Statistics.
Error code alignments are that sample frame data and input data carried out xor operation, and 1 digit is in comparison result
For wrong digit, the data bit width of the system is 256, and the statistics of error code comparison result needs to 1 in 256 data
Number count and added up, and a clock can not count the error code number in 256 data at the same time, designs 9 grades of adders
Flowing water counts, as shown in figure 5, the first order is exported as 2bit using the adder of 128 1bit；The second level uses 64 2bit
Adder, successively, the adder of 1 8bit of the 8th grade of use, is output in the accumulator of a 64bit, while statistical result is defeated
Go out to PCIe registers.Input data is cached in FIFO to be used for rear end frame identification sort module.+ number expression adder.
The single pass state machine of module such as Fig. 6；
IDLE is idle condition, and when front end, FIFO has data, and when rear end FIFO is non-full, module is entered by IDLE state
READ_non states；
READ_non states normally read data according to position control signal；When read need compare position when
Module enters Wait_C states；
Wait_C states compare the data of reading with standard comparison data by turn, and comparison result is sent to 9 grades of additions
Device carries out error code result statistics；When comparing to when terminating to compare position, module enters And_last_C states
And_last_C states；Want comparison data that position comparison is compared to last；Next clock module enters
Wait_last_C states；
Wait_last_C states compare the last position data that compares；If last comparison data for a frame data most
256 data of the latter, then module into READ_non states continue read data, until a frame data read complete or
Wai_last_C comparison datas wait next frame data to be handled to jump to IDLE state after a frame final data.
Statistical conditions are compared according to actual error code, test data is set and compares position, wherein the error code position of a frame data
Number is 8, carries out emulation testing, as a result as shown in figs. 7 a and 7b.
Simulation result shows that test data error code digit is 512 in Fig. 7 a, sets and is consistent with emulation data.
It is to handle a frame data used time that simulation result tape measure is in Fig. 7 b time, is 35 clock (clock cycle
10ns), the processing bit rate of test is：36.57Gbps.
It is to handle a frame data used time that simulation result tape measure is time, is 35 clocks (clock cycle 10ns), surveys
The processing bit rate of examination is：36.57Gbps.
The simulation clock cycle is arranged to 10ns, and two yellow cursor present positions are a frame data respectively in simulation result figure
The starting of processing and final position, ERS_error_Total signals are Bit Error Code Statistics as a result, setting result phase with data in figure
Together；A frame 1024byte data are handled, it is necessary to which 33 clock cycle, system use 156.25MHz frequency clocks, the number of this module
It is according to processing speed：1024byte/ (33 × 1/156.25MHz)=3.88 × 10^10bps=38.8Gbps.
Received data are carried out VCID classification by frame identification sort module design first in VCID sort modules.Due to
Data entry rate is high and 4 channel datas to classify pair at the same time, and data rate reaches 10Gbps, at bit data classification
Reason average delay is less than 0.1ns.To improve data processing speed and controlling caching capabilities to step-out data, using parallel extraction
2 tunnels, after the extraction of data VCID data, to carry out follow-up data combining, ensure that data are not lost because combining is delayed
Lose, the data after extraction are first sent into the buffering of 2 push-up storages (FIFO) progress data frame levels.Frame identification classification
The design frame chart of module such as Fig. 3.
Passage one is same VCID values with valid data in passage two, other VCID Value Datas are filling frame data；Passage
Three with valid data in passage four be another VCID values, other VCID Value Datas are to fill frame data.
Channel selecting is by the way of poll, if data are more than a frame in the FIFO of front end, reading process, judges after processing
Another passage FIFO.Judge another passage FIFO if front end data fifo is less than a frame, circulate interpretation.According to each after initialization
VCID occurrences, carry out each frame and compare one by one.To save space and resource, will directly be abandoned for infilled frame VCID.Number passes frame
A length of 1024byte, and used data bit width is 256bit, therefore determine after VCID will be at continuous 32 for comparing
Clock completes the classification storage of a frame data, while takes next frame to carry out data VCID forms and judge.Compare correct VCID data
Frame is stored into corresponding FIFO.During the VCID data that will carry out next frame take out judgement, it will read before judging
Data volume in FIFO is held, if will be waited less than a frame, pause classification.It will determine that in write-in, the poor frames of rear end FIFO will
Man Shi, will stop writing, is waited.
The state machine of module is as shown in Figure 8.
IDLE is idle condition, when rear end FIFO is non-full and front end FIFO non-NULLs whens enters MUX states；
MUX states expire signal according to the sky of last time reading FIFO flag Ch values and front end FIFO leads into row of channels reading data
Road selects, and FISRT states are entered after selection；
FISRT states pre-process channel data, enter AND_A or AND_B states according to Ch values；
AND_A or AND_B states to first time data carry out VCID be worth identifying, after identification enter READ_non_A or
READ_non_B states；
READ_non_A or READ_non_B carries out frame data remaining data reading process, when a frame data after treatment
Into IDLE state, prepare the processing of next frame data.
All it is non-NULL by setting front end FIFO, for one first frame data of passage to fill out frame data, other data are normal
Data, two data of passage are all normal data.Emulation testing, the results are shown in Figure 9.
According to VCID values output data is identified classification in simulation result display module, and it is processing the time that tape measure, which is,
One frame data used time, is 35 clocks (clock cycle 10ns), and the processing bit rate of test is：36.57Gbps.
Ch signals are front passage data selection marker position in figure, and the time shown in scale is a frame data processing time,
For 35 clock cycle；VCDU is VCID exceptional value flag bits, and the first frame data are exception VCID data；Module front end two
FIFO all non-NULLs, Ch values are in 1 and 0 direct checker, and data select alternately to read data in the FIFO of front end two, with imitating
True set is consistent.Frame identifies that the single channel bit rate of sort module is：1024byte/ (35 × 1/156.25MHz)=3.57 ×
10^10bps=35.7Gbps.
VCID combinings module designs, and VCID combinings module is realized and is ranked up the data frame of same VCID by frame count,
By using data in continuous payload data stream sequence of positions, i.e. frame count, it is continuous right to calculate the frame in data frame
Under the conditions of its to tackling in actual chip external memory address, and this data frame is written in chip external memory address.Therefore,
When data read module carries out digital independent according to physical memory module of the incremental order in address outside piece, frame meter can be obtained
The continuous number of number passes data frame, realizes that frame data sort.
VCID is counted as shown in table 2-1 before VCID data combinings, and data is are randomly distributed in 2 passages, after combining
VCID is counted as shown in table 2-2, and data is in continuous storage Mr. Yu section cachings.
VCID is counted before table 2-1 combinings
VCID is counted after table 2-2 combinings
| VCID is counted | … | 1 | 2 | 3 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | … |
VCID combinings sorting module is by the way of two-way parallel processing, and single channel VCID combining ordering designs block diagram is as schemed
Shown in 4, module input identifies sort module output for front end frame.Frame data are caused to occur when there is the increase extremely of VCID counters
During step-out, temporarily by data buffer storage in FIFO is cached extremely, if normal VCID Counter Value saltus steps, abnormal to cache FIFO numbers
Sort according to re-starting.
VCID combining module single channel conceptual design block diagrams are as shown in Figure 4；
Combining is sorted：It is ranked up according to the VCID Counter Values of input data；
MUX：Front end data is made choice according to combining sorting sub-module control signal；
Data flow controls：Data flow is controlled according to combining sorting sub-module control signal；
Step-out data buffer storage FIFO：Continuous step-out data are cached；
Digital independent：Data are completed to sequence and are read out caching；
Data buffer storage FIFO：The data that are disposed carry out caching and are used for rear module；
Off-chip memory module：Large capacity data memory, the caching of complete paired data frame, ensures to meet in the range of step-out
Data storage requirement.In data input, realize that the value for by the frame data in data FIFO1, being written to address FIFO1 is corresponding
In the outer storage address of piece.In reading data course, realize to read out the data frame of address FIFO2 corresponding address and be sent to
In data FIFO2；
VCID combinings, which are sorted, writes state machine such as Figure 10 of data module.According to real data situation, VCID change in count point
For 6 kinds of patterns, concrete condition is shown in Table 2-1, and (1) is normal condition, and (2) are counter jump increase situation, and (3) are normal with (4)
Occurs abnormal frame data situation in frame data, (5) normally redirect situation after being counted completely for Counter Value (24 bit wide), and (6) are counting
Device jump reduction situation；
VCID combining module status machine explanations：
It is idle：When front end FIFO empty or rear end cache FIFO completely, waited into idle condition；
VCID counters are read：The VCID Counter Values of frame data are read out；
Compare：VCID Counter Values are compared with plot (Counter Value) size；
Mathematic interpolation 1：VCID Counter Values subtract plot；
Mathematic interpolation 2：Plot subtracts VCID Counter Values；
Saltus step is handled：Address after calculating saltus step；
Address computation 1：The physical address of data storage is calculated according to difference 1 and plot；
Address computation 2：The physical address of data storage is calculated according to difference 2 and plot；
Plot modification 1：Base address ways of carrying out one is changed；
Address stores：Address storage is cached in FIFO to address date；
Step-out processing：Data step-out is judged according to the VCID counter values of difference and previous frame data, respectively to first step-out
Frame data, continuous step-out frame data (out-of-step free with respect to previous frame step-out frame data) and discontinuous step-out frame data are (on relatively
One step-out frame data are still step-out frame data) into line flag；
Count：Continuous step-out frame data are counted, discontinuous step-out frame data are from New count；
Plot modification 2：Base address ways of carrying out two is changed；
Data store：Frame data are write into caching FIFO；
Flag bit processing control：According to the flag bit of front position carry out read data-triggered set, front end data selection with
And Back end data traffic organising；
Data read module：Data read module carries out data frame to reading according to the incremental order in address from external memory storage
Take, obtain frame count continuous logarithmic biography data frame of ascending the throne, sort so as to fulfill frame.Data read module is divided into write address FIFO moulds
Block is with reading data fifo module, write address fifo module state machine such as Figure 11：
State description：
(1) it is idle：Etc. the trigger signal that continues
(2) normal mode：Write 512 frame data addresses
(3) step-out pattern：Write 1024 frame data addresses
(4) 1 is waited：Address FIFO is completely waited
(5) 2 are waited：Address FIFO is completely waited
Read data module status machine such as Figure 12：
State description：
(1) it is idle：Data FIFO empty waits
(2) VCID values judge：Frame data VCID values are read compared with setting value, export judging result
(3) data are read：Read frame data and store into caching FIFO
Table 2-3 VCID change in count situation tables
For the true counter situation of change of six classes in table 2-3, emulation is set, as a result for：
(1) result is as shown in Figure 13 a, Figure 13 b.
Two scale lines are that to handle time of 1 frame data be 33 clock cycle in Figure 13 a, bit rate 38.8Gbps.
(2) complete to count frame data to the frame data processing for redirecting increase by normal VCID, base address conversion, sets data
Carry out simulation result such as Figure 14.
Wr_en signals cache the realistic energy control signals of FIFO for Back end data in figure, and wr_en is 0 between scale line, is held
The continuous time is 5 frame data processing times (166 clock cycle), and data are postponed into step-out data buffer storage FIFO during this, etc.
When data accumulation reaches 5 frames continuously to redirect data, base address is changed, data are cached in Back end data FIFO again.
(3) abnormal data is given up after postponement processing being carried out to abnormal frame data, sets data to carry out simulation result as schemed
15。
In Figure 15 after abnormal data postpones four frames, normal frame data answers step-out data buffer storage FIFO after entering
Position, it is reset signal to abandon rst signals in abnormal frame data figure, high effectively.
(4) similar with (3), Tu16Zhong, abnormal frame data is postponed in FIFO, when the abnormal frame data relative to caching
When next frame data or step-out abnormal data, module is resetted step-out data buffer storage FIFO, abandons abnormal data fifo.
(5) test data, simulation result such as Figure 17.
Time in figure shown in scale is 5 frame data, and when counter counts are completely changed into 0, module will keep in 5 frame data, when
After being filled with 5 frame data, module modification base address, is cached in the FIFO of rear end after 5 temporary frame data are handled as correction data.
(6) data are set to carry out simulation result such as Figure 18.
In Figure 18, after abnormal data postpones four frames, normal frame data answers step-out data buffer storage FIFO after entering
Position, abandons abnormal frame data, position shown in cursor line is step-out data buffer storage FIFO reset signals (rst) high active homing.
By carrying out emulation testing to six class data in table 2-3, module can normally handle six class VCID technical situations, resume module
One frame data need 33 clock cycle, its bit rate is 38.8Gbps.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, technique according to the invention scheme and its
Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (2)
1. a kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system, it is characterised in that it includes：
Front end for being cached to input data caches fifo module；
For comparing statistical module to error code of the input data by bit comparisons；
The error code, which compares statistical module, to be included：
For the module compared by turn that input data is compared by bit；
Random access memory modules for the comparison data for storing standard；
For the data after being compared by bit to be carried out with the Bit Error Code Statistics module of Bit Error Code Statistics；
For the data buffer storage fifo module cached to input data；
Using the wide flowing water adder of decrease, the comparison result statistics in a clock is realized；
Frame for the extraction of identical VCID data frame classifications identifies sort module；
The frame identification sort module includes：
Module for the channel selecting made choice to front passage input data；
For identifying sort module to the VCID of input data identification classification according to VCID, sort module identification is identified according to VCID
As a result；If VCID values are correct, input data is cached in VCID FIFO；If VCID value mistakes, lose input data
Abandon；
For the VCID combining modules to same VCID data sortings；
The VCID combinings module includes：
For the combining sorting module being ranked up according to the VCID Counter Values of input data；
For the selector module made choice according to combining sorting module control signal to front end data；
For controlling the data flow control module of data flow according to combining sorting module control signal；
For the step-out data buffer storage fifo module cached to continuous step-out data；
The data read module for being read out caching for completing data to sequence；
For handling the data buffer storage fifo module for completing data and carrying out caching and being used for rear module；
For the data buffer storage fifo module cached to output data；
The VCID is tunnel value.
2. a kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing method, it is characterised in that it includes：
Front end for being cached to input data caches FIFO steps；
For comparing statistic procedure to error code of the input data by bit comparisons；
The error code, which compares statistic procedure, to be included：
For input data is compared by bit comparison by turn the step of；
Random access memory step for the comparison data for storing standard；
For the data after being compared by bit to be carried out with the Bit Error Code Statistics step of Bit Error Code Statistics；
For the data buffer storage FIFO steps cached to input data；
Using the wide flowing water adder of decrease, the comparison result statistics in a clock is realized；
Frame for the extraction of identical VCID data frame classifications identifies classifying step；
The frame identification classifying step includes：
For front passage input data is made choice channel selecting the step of,
For identifying classifying step to the VCID of input data identification classification according to VCID, sort module identification is identified according to VCID
As a result；If VCID values are correct, input data is cached in VCID FIFO；If VCID value mistakes, lose input data
Abandon；
For the VCID combining steps to same VCID data sortings；
The VCID combinings step includes：
For the combining sequence step being ranked up according to the VCID Counter Values of input data；
For the selector step made choice according to combining sorting module control signal to front end data；
For controlling the data flow rate-determining steps of data flow according to combining sorting module control signal；
For the step-out data buffer storage FIFO steps cached to continuous step-out data；
The data reading step for being read out caching for completing data to sequence；
For handling the data buffer storage FIFO steps for completing data and carrying out caching and being used for rear module；
For the data buffer storage FIFO steps cached to output data.
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| CN106788675A (en) * | 2016-12-05 | 2017-05-31 | 中国资源卫星应用中心 | Using the method for null frame data statistics satellite in orbit initial data error code |
| CN107453799B (en) * | 2017-06-30 | 2020-08-25 | 上海卫星工程研究所 | Satellite high-speed data ground processing system and test method thereof |
| CN111385056B (en) * | 2018-12-27 | 2023-02-10 | 中国电子科技集团公司第十五研究所 | Real-time stream processing method for effective load data |
| CN112783827A (en) * | 2019-11-11 | 2021-05-11 | 北京京邦达贸易有限公司 | Multi-sensor data storage method and device |
| CN111711476B (en) * | 2020-04-26 | 2022-04-19 | 四川润泽经伟信息技术有限公司 | Real-time frame synchronization system and method based on satellite communication countermeasure system |
| CN111650618B (en) * | 2020-06-30 | 2023-06-20 | 天津云遥宇航科技有限公司 | GNSS occultation detection signal processing method |
| CN113132070A (en) * | 2021-04-16 | 2021-07-16 | 中国电子科技集团公司第五十四研究所 | High-speed data transmission baseband data no-frame structure error code statistical system |
| CN114124193A (en) * | 2021-11-12 | 2022-03-01 | 中国科学院国家空间科学中心 | High-performance data transmission baseband odd-even combination real-time processing system and method thereof |
| CN115085863A (en) * | 2022-03-30 | 2022-09-20 | 上海航天电子有限公司 | Frame counting correction and frame loss statistical method for wireless data |
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