CN104750871B - AOS satellite data transmission valid data area's extraction system and method based on FPGA - Google Patents
AOS satellite data transmission valid data area's extraction system and method based on FPGA Download PDFInfo
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- CN104750871B CN104750871B CN201510187602.7A CN201510187602A CN104750871B CN 104750871 B CN104750871 B CN 104750871B CN 201510187602 A CN201510187602 A CN 201510187602A CN 104750871 B CN104750871 B CN 104750871B
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Abstract
AOS satellite data transmission valid data area's extraction system and method based on FPGA, belong to satellite load technical field of data processing.The present invention is that processing speed has the problem of bottleneck in order to solve that satellite load data are handled and distributed by the way of Software for Design.System includes three data memory modules, verification is compared in the essential information for being carried to AOS standards frame data, gives up mistake frame data, exports the format check module and data extraction module of correct frame data；Method includes three data storing steps, verification is compared in the essential information for being carried by format check module to AOS standards frame data, give up mistake frame data, the step of exporting correct frame data and for being required by data extraction module according to data pattern correct frame data, the step of being extracted according to data cell, and being spliced into expected length parsing data.The present invention is used for satellite data transmission valid data area and extracted.
Description
Technical field
The present invention relates to AOS satellite data transmission valid data area's extraction system based on FPGA and method, belong to satellite load
Technical field of data processing.
Background technology
Demand with mankind's exploration of the universe space constantly increases, and spacecraft and space transoportation instrument need to realize sky
An one empty, empty ground, a nil link transmit a variety of digital informations simultaneously, in order to set up extensive three-dimensional in different aspects
Global data network for spatial data information exchange support, consultative committee for space data system of International Organization for standardization are provided
CCSDS (Consultative Committee for Space Data Systems) has formulated Advanced Orbiting Systems AOS
(Advanced Orbiting Systems), AOS define the mode of much information exchange between Air-Ground, include space
Stand, the data-transmission mode of the spacecraft such as satellite, space shuttle, be Aerospace Data Systems information exchange and processing it is important according to
According to.At present, application of the countries in the world for CCSDS AOS standards is more prevalent, and it effectively and the characteristics of open turns into most of
The preferred option of new spacecraft data system system.In recent years, the project that China cooperates with European Space Agency --- " detection No.1 ", " visit
Survey No. two ", CCSDS AOS normal datas are received by respective earth station jointly；China Lunar Exploration Program lunar rover uses CCSDS AOS
Standard carries out moonscape and closely observes load data packing processing, transmits terrestrial system.
The data that satellite load collects are packed by multiplexer according to CCSDS AOS standards, by satellite-ground link passage
Under pass, by ground system to the satellite data protocol analysis received and information processing, finally extract original science charge number
According to.At present, the load that satellite carries is more and more, and data volume is increasing, and storage pressure is excessive, the transmission of satellite downlink
Speed must improve, and the demand that ground system is handled high-speed data in real time is also constantly being strengthened.Traditional ground
System is that the processing and distribution of satellite data are carried out by the way of Software for Design, and the speed of processing has bottleneck.
The content of the invention
The invention aims to solve that satellite load data are handled and distributed by the way of Software for Design, place
There is the problem of bottleneck in reason speed, there is provided a kind of AOS satellite data transmission valid data area's extraction system and method based on FPGA.
A kind of AOS satellite data transmission valid data area extraction system based on FPGA of the present invention, it includes：
For storing the satellite load data memory module of AOS standard frame data；
Verification is compared in essential information for being carried to AOS standards frame data, gives up mistake frame data, and output is correct
The format check module of frame data；
For storing the frame data memory module of correct frame data；
For being required according to data pattern correct frame data, after being extracted according to data cell, expected length is spliced into
The data extraction module of degree parsing data；
Parsing data memory module for storing and resolving data.
Format check module includes：
For monitoring the process signal of pending AOS standards frame data and entering to comparing correction verification module and output selecting module
The verification control module of row control；
For processing to be compared to AOS standard frame data according to the comparison control signal of verification control module, it is determined that working as
Preceding AOS standards frame data are the Inspection module of wrong frame data or correct frame data；The wrong frame data and correct frame
Data are to meet the frame data of AOS forms；
It is defeated for wrong frame data or correct frame data select according to the output control signal of verification control module
Go out, by erroneous frame rejection of data, export the output selecting module of correct frame data.
Verification control module includes four kinds of state of a controls, and respectively idle condition, control information compare state, control is given up
Erroneous frame data mode and control export correct frame data state,
Idle condition：Etc. to be launched, when monitoring the process signal of pending AOS standards frame data, believe into control
Cease comparison state；
Control information compares state：Processing is compared to AOS standard frame data to correction verification module in control ratio, when comparison school
Test module and determine current AOS standards frame data when being correct frame data, correct frame data state is exported into control；When comparison school
Test module and determine current AOS standards frame data when being wrong frame data, into giving up erroneous frame data mode；
Control exports correct frame data state：Export correct frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state is compared into control information, otherwise into idle condition；
Erroneous frame data mode is given up in control：Give up mistake frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state is compared into control information, otherwise into idle condition.
Data extraction module includes：
For according to setting mode of operation logarithm it is judged that module, mode boot module and significance bit computing module are controlled
The extraction control module of system；
For according to the judgement control signal of extraction control module to the invalid number in the correct frame data that transmit each time
According to being given up, the data judge module of frame valid data is obtained；
The pattern of the valid data in frame valid data is carried out for the mode control signal according to extraction control module
Judge, determine that valid data area is by lowest order or by the mode boot mould not least position in frame valid data
Block；
For carrying out having to low level shift align operation to the frame valid data that valid data area is started from not least position
Imitate alignment of data module；
For the valid data area that is exported to mode boot module by the frame valid data and valid data lowest order
The data cache module that frame valid data after alignment module progress low level shift align operation are stored；
For being obtained according to the mode of operation signal of change of extraction control module when what previous framing valid data included has
Imitate the significance bit computing module of data bit length；
For by the valid data bit length included when previous framing valid data and being worked as according to parsing data predicting length
The length of the splicing data of preceding cycle concatenation module output is compared, it is determined that for be intercepted when previous framing valid data
The length of data bits, remaining data digit and the splicing for judging whether to be enough to complete a data by this splicing compares mould
Block；
For the data bits to be intercepted that is exported according to length comparison module will work as previous framing valid data with it is current
The unfinished splicing data of cycle splicing selecting module output carry out splicing and obtain current splicing data, and calculate and worked as
The concatenation module of the length of data is completed in preceding splicing；
Remaining data digit for being exported according to length comparison module will be worked as remaining effective in previous framing valid data
Data shift the remaining data shift module for splicing data to high-order mobile obtain；
Signal is completed in data splicing for being exported according to length comparison module makes currently to splice data as parsing data
Select the output selecting module of output；
Parsing number of the signal to output selecting module output is completed in data splicing for being exported according to length comparison module
Selected according to the displacement splicing data exported with remaining data shift module, for the splicing selecting module spliced next time.
Extraction control module includes four kinds of states, respectively idle condition, mode decision state, displacement aligned condition and directly
Connect assigned state；
Idle condition：Wait, when monitoring correct frame data, Dietary behavior judges state；
Mode decision state：Control data judge module is carried out to the invalid data in the correct frame data that transmit each time
Give up, obtain frame valid data, then control model guiding module determines the pattern of frame valid data, when valid data area is by most
When low level starts pattern, into indirect assignment state；When valid data area is that not least position starts pattern, alignd into displacement
State；
Shift aligned condition：The frame valid data that control valid data alignment module starts to not least position carry out low displacement
Position alignment operation, obtain low level shift align operation frame valid data after, into indirect assignment state, otherwise into idle shape
State；
Indirect assignment state：When obtaining valid data area by the frame valid data lowest order, oneself state is kept；It is no
Then enter idle condition.
A kind of AOS satellite data transmission valid data area extracting method based on FPGA, it includes：
The step of for by AOS standard frame data Cun Chudao satellite load data memory modules；
Verification is compared in essential information for being carried by format check module to AOS standards frame data, gives up mistake
Frame data by mistake, the step of exporting correct frame data；
The step of for the storage of correct frame data to be arrived into frame data memory module；
For being required by data extraction module according to data pattern correct frame data, carried according to data cell
The step of taking, and being spliced into expected length parsing data；
The step of for data Cun Chudao parsing data memory modules will to be parsed.
The step of exporting correct frame data includes：
For monitoring the process signal of pending AOS standards frame data and to comparing correction verification module by verifying control module
The step of being controlled with output selecting module；
For by Inspection module, being entered according to the comparison control signal of verification control module to AOS standard frame data
Row comparison is handled, it is determined that the step of current AOS standards frame data are wrong frame data or correct frame data；The wrong frame data
It is the frame data that meet AOS forms with correct frame data；
For by exporting selecting module, according to the output control signal of verification control module to wrong frame data or correct
Frame data carry out selection output, by erroneous frame rejection of data, the step of exporting correct frame data.
Verification control module includes four kinds of state of a controls, and respectively idle condition, control information compare state, control is given up
Erroneous frame data mode and control export correct frame data state,
Idle condition：Etc. to be launched, when monitoring the process signal of pending AOS standards frame data, believe into control
Cease comparison state；
Control information compares state：Processing is compared to AOS standard frame data to correction verification module in control ratio, when comparison school
Test module and determine current AOS standards frame data when being correct frame data, correct frame data state is exported into control；When comparison school
Test module and determine current AOS standards frame data when being wrong frame data, into giving up erroneous frame data mode；
Control exports correct frame data state：Export correct frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state is compared into control information, otherwise into idle condition；
Erroneous frame data mode is given up in control：Give up mistake frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state is compared into control information, otherwise into idle condition.
The step of being spliced into expected length parsing data includes：
For the setting mode of operation logarithm by extracting control module it is judged that module, mode boot module and significance bit
The step of computing module is controlled；
For correct to what is transmitted each time according to the judgement control signal of extraction control module by data judge module
Invalid data in frame data is given up, obtain frame valid data the step of；
For by mode boot module, the pattern according to the mode control signal of extraction control module to frame valid data
Judged, determine the step of valid data area is by lowest order or by not least position；
For the frame valid data that valid data area is started from not least position are carried out by valid data alignment module to
The step of low level shift align operation；
For being had by data cache module to the valid data area that mode boot module exports by the frame lowest order
The step of frame valid data after effect data and valid data alignment module progress low level shift align operation are stored；
Work as previous group for being obtained by significance bit computing module according to the mode of operation signal of change of extraction control module
The step of valid data bit length that frame valid data include；
For will be had by length comparison module according to parsing data predicting length when what previous framing valid data included
Data bit length is imitated compared with the length for the splicing data that current period concatenation module exports, it is determined that for working as previous framing
Data bits that valid data to be intercepted, remaining data digit and judge whether be enough to complete data by this splicing
The step of splicing；
The data bits to be intercepted for being exported by concatenation module according to length comparison module, which will work as previous framing, to be had
Imitate data and the unfinished splicing data progress splicing of current period splicing selecting module output obtain current splicing data,
And calculate and obtain the step of length of data is completed in current splicing；
Remaining data digit for being exported by remaining data shift module according to length comparison module will work as previous group
Remaining valid data obtain the step of data are spliced in displacement to a high position is mobile in frame valid data；
Signal is completed in data splicing for being exported by exporting selecting module according to length comparison module to be made currently to splice
The step of data are as parsing data selection output；
Data splicing for being exported by splicing selecting module according to length comparison module completes signal and output is selected
The parsing data of module output and the displacement splicing data of remaining data shift module output are selected, for splicing next time
The step of.
Extraction control module includes four kinds of states, respectively idle condition, mode decision state, displacement aligned condition and directly
Connect assigned state；
Idle condition：Wait, when monitoring correct frame data, Dietary behavior judges state；
Mode decision state：Control data judge module is carried out to the invalid data in the correct frame data that transmit each time
Give up, obtain frame valid data, then control model guiding module determines the pattern of frame valid data, when valid data area is by most
When low level starts pattern, into indirect assignment state；When valid data area is that not least position starts pattern, alignd into displacement
State；
Shift aligned condition：The frame valid data that control valid data alignment module starts to not least position carry out low displacement
Position alignment operation, obtain low level shift align operation frame valid data after, into indirect assignment state, otherwise into idle shape
State；
Indirect assignment state：When obtaining valid data area by the frame valid data lowest order, oneself state is kept；It is no
Then enter idle condition.
Advantages of the present invention：The present invention completes place of each module to data using FPGA FPGA
Reason, FPGA is a kind of customizable hardware circuit, has that flexibility is high, can concurrent working, data throughout is big, data processing speed
The fast advantage of rate.It can be achieved to parse extraction to the real time high-speed of AOS standard frame data.
Present system and method can parse to the AOS standard datas that satellite packing passes down, carry as requested
Wherein different data fields is taken, then the data after extraction are constantly spliced into data and the storage of same bit-width, is thus reduced
Satellite gathered data is obtained, the foundation of aerospace strategy research is carried out as ground staff.
The present invention carries out high speed extraction for the science load data of AOS forms, mainly includes frame format verification, data carry
Take and splice two parts, cache module can also select control signal to replace to complete the operation to AOS Data Stream Processings.
The present invention can flexibly change in the design of data bit width, and bit wide is bigger, and the handling capacity of data processing is then higher.Cause
For the length and on-fixed of the frame data of AOS mono-, the bit wide of data processing can be identical with frame data length, can also compare frame data
Length is small, and its data extraction method is identical, and the time simply needed is different.
Brief description of the drawings
Fig. 1 is the overall procedure signal of the AOS satellite data transmission valid data area extraction system of the present invention based on FPGA
Figure；
Fig. 2 is the principle frame of AOS satellite data transmission valid data area's extraction system based on FPGA and method of the present invention
Figure；
Fig. 3 is the state diagram for verifying control module；
Fig. 4 is the state diagram for extracting control module.
Embodiment
Embodiment one：Illustrate present embodiment with reference to Fig. 1 and Fig. 2, FPGA is based on described in present embodiment
AOS satellite data transmission valid data area extraction system, it includes：
For storing the satellite load data memory module 1 of AOS standard frame data；
Verification is compared in essential information for being carried to AOS standards frame data, gives up mistake frame data, and output is correct
The format check module 2 of frame data；
For storing the frame data memory module 3 of correct frame data；
For being required according to data pattern correct frame data, after being extracted according to data cell, expected length is spliced into
The data extraction module 4 of degree parsing data；
Parsing data memory module 5 for storing and resolving data.
First, AOS standards are illustrated.AOS data frames are earthward transmitted by physical channel, AOS Spatial data chains
An ideas in basic in the agreement of road is pseudo channel VC (Virtual Channel).Pseudo channel this functionality allows
One physical channel can be shared by a variety of high level data streams, and every kind of data flow carries different business needs.Therefore, one
Individual individually physical channel is divided into several different data channel, and each data channel is a pseudo channel.
The form of AOS transmission frames is as shown in table 1.
The AOS transmission frames of table 1
One AOS data frame mainly has following several regions：Transmission frame dominates head, transmission frame insert district (optional), transmission
Region frame data and transmission frame postamble (optional).Each frame data must all include the data of a leading head and a regular length
Area, data field is by user's sets itself length.Top guide provides Protocol Control Information, and the data of higher business are carried in data field
Unit.
Introduction more than to AOS frame data features, the satellite based on FPGA calculating acceleration described in present embodiment carry
The annexation of each module of lotus data extraction system is as shown in Figure 1.Wherein satellite load data memory module 1 is to AOS standards
Frame data are stored, and remain subsequent treatment.The essential information carried in the frame data that format check module 2 passes down to satellite is entered
Row compares, and prevents wrong frame data, once erroneous frame occur gives up data.Frame data memory module 3, which is used to store, to be believed
Breath compares errorless frame data, prevents upper level module from being had an impact when there is the situation that frame is given up to Subordinate module.Data carry
Modulus block 4 extracts, and be spliced into the number of uniform length according to the demand of different mode to the different pieces of information unit of frame data
According to.Parsing data memory module 5 is used to preserve the data being parsed, and is used for other users.
Format check module 2 in present embodiment carries out verification judgement to the data of input, leaves correct frame data.
Data extraction module 4 is extracted according to the length change of valid data under different mode and carries out the splicing of designated length, most
The data flow of valid data is exported afterwards.
Embodiment two：Illustrate present embodiment with reference to Fig. 2, present embodiment is made into one to embodiment one
Step explanation, format check module 2 include：
For monitoring the process signal of pending AOS standards frame data and to comparing correction verification module 2-2 and output selection mould
The verification control module 2-1 that block 2-3 is controlled；
For processing to be compared to AOS standard frame data according to verification control module 2-1 comparison control signal, it is determined that
Current AOS standards frame data are the Inspection module 2-2 of wrong frame data or correct frame data；Wrong frame data and just
True frame data are the frame data for meeting AOS forms；
For being selected according to verification control module 2-1 output control signal wrong frame data or correct frame data
Output, by erroneous frame rejection of data, export the output selecting module 2-3 of correct frame data.
Format check module 2 in present embodiment is used for the verification for completing VCDU essential informations, and information is correctly counted
According to the downward previous module transmission of frame, mistake give up.It is AOS frame data that it, which is inputted, and after format check, output is to meet
The frame data of AOS forms.
Embodiment three：Illustrate present embodiment with reference to Fig. 3, present embodiment is made into one to embodiment two
Step explanation, verification control module 2-1 include four kinds of state of a controls, and respectively idle condition 21, control information compares state 22, control
System gives up erroneous frame data mode 23 and control exports correct frame data state 24,
Idle condition 21：Etc. to be launched, when monitoring the process signal of pending AOS standards frame data, into control
Information compares state 22；
Control information compares state 22：Processing is compared to AOS standard frame data to correction verification module 2-2 in control ratio, when
Inspection module 2-2 determines current AOS standards frame data when being correct frame data, and correct frame data state is exported into control
24；When it is wrong frame data that Inspection module 2-2, which determines current AOS standards frame data, into giving up mistake frame data shape
State 23；
Control exports correct frame data state 24：Export correct frame data；When monitoring pending AOS standards frame data
During process signal, state 22 is compared into control information, otherwise into idle condition 21；
Erroneous frame data mode 23 is given up in control：Give up mistake frame data；When monitoring pending AOS standards frame data
During process signal, state 22 is compared into control information, otherwise into idle condition 21.
The state machine of present embodiment is used to realize the behaviour to be launched such as control, idle condition 21 to form correction verification module 2
Make, when pending data in upper level cache module be present, module starts, and control information is entered after startup and compares shape
State 22, comparison result enter output selecting module 2-3 as Rule of judgment, and when comparison result is correct, data are defeated as virtual value
Go out, comparison result mistake then gives up data.The data for entering module after starting every time are all complete frame data.
Embodiment four：Illustrate present embodiment with reference to Fig. 2, present embodiment to embodiment one, two or
Three are described further, and data extraction module 4 includes：
For according to setting mode of operation logarithm it is judged that module 4-2, mode boot module 4-3 and significance bit computing module
The extraction control module 4-1 that 4-6 is controlled；
For according to extraction control module 4-1 judgement control signal to invalid in the correct frame data that transmit each time
Data are given up, and obtain the data judge module 4-2 of frame valid data；
For being entered according to extraction control module 4-1 mode control signal to the pattern of the valid data in frame valid data
Row judges, determines that valid data area is by lowest order or by the mode boot mould not least position in frame valid data
Block 4-3；
For carrying out having to low level shift align operation to the frame valid data that valid data area is started from not least position
Imitate alignment of data module 4-4；
For to the valid data area that mode boot module 4-3 is exported by the frame valid data and significant figure lowest order
The data cache module 4-5 that the frame valid data after low level shift align operation are stored is carried out according to alignment module 4-4；
For obtaining what is included when previous framing valid data according to extraction control module 4-1 mode of operation signal of change
The significance bit computing module 4-6 of valid data bit length；
For by the valid data bit length included when previous framing valid data and being worked as according to parsing data predicting length
The length of the splicing data of preceding cycle concatenation module 4-8 outputs is compared, it is determined that for be cut when previous framing valid data
Whether the data bits, remaining data digit and the judgement that take are enough to complete the length ratio of the splicing of a data by this splicing
Compared with module 4-7；
The data bits to be intercepted for being exported according to length comparison module 4-7 will work as previous framing valid data with working as
The unfinished splicing data of preceding cycle splicing selecting module 4-11 outputs carry out splicing and obtain current splicing data, and calculate
Obtain the concatenation module 4-8 that the length of data is completed in current splicing；
Remaining data digit for being exported according to length comparison module 4-7, which will work as residue in previous framing valid data, to be had
Data are imitated to the high-order mobile remaining data shift module 4-9 for obtaining displacement splicing data；
Signal is completed in data splicing for being exported according to length comparison module 4-7 makes currently to splice data as parsing number
According to the output selecting module 4-10 of selection output；
Data splicing for being exported according to length comparison module 4-7 completes signal to output selecting module 4-10 outputs
Parsing data and the displacement splicing data of remaining data shift module 4-9 outputs are selected, for the splicing spliced next time
Selecting module 4-11.
The function of data extraction module 4 is by the phase in each frame data according to different mode of operations in present embodiment
Answer data area to be extracted and carry out splicing restructuring according to specified length.The challenge of this module is flexible quick data
Disposal ability, the data of one section of indefinite length in different frame data are extracted to the data for being spliced into regular length.Module
Input is AOS form frame data, and output is the data flow for the regular length that valid data are formed.
Here the method for the extraction data used is all to be moved for the data of part to be extracted to low level alignment, together
When for the mode of operation of setting calculate the byte number for needing to extract data, frame data by displacement and its comprising it is effective
Byte number is as output, and Subordinate module can obtain the precise area of valid data accordingly, and the data field is by lowest byte
Start, convenient that data are completed to splice, therefore, the processing to data is tentatively extracted that is, having carried out data.
Whether data judge module 4-2 is used for sentencing in correct frame data comprising frame valid data in present embodiment
Disconnected, because the length of correct frame data is different, in transmittance process, data may be by the transmission of whole frame, it is also possible to is once
A part for whole frame data is delivered, the situation that part is transmitted, that is, the situation not comprising valid data, data judge module be present
4-2 will remove correct frame data and not include the part of valid data in gradation transmittance process, and retain comprising valid data
Partial frame valid data.
Embodiment five：Illustrate present embodiment with reference to Fig. 1 to Fig. 4, present embodiment is to embodiment four
It is described further, extraction control module 4-1 includes four kinds of states, respectively idle condition 41, mode decision state 42, displacement
Aligned condition 43 and indirect assignment state 44；
Idle condition 41：Wait, when monitoring correct frame data, Dietary behavior judges state 42；
Mode decision state 42：Control data judge module 4-2 is to the invalid number in the correct frame data that transmit each time
According to being given up, frame valid data are obtained, then control model guiding module 4-3 determines the pattern of frame valid data, works as significant figure
It is by lowest order during pattern, into indirect assignment state 44 according to area；When valid data area is that not least position starts pattern,
Into displacement aligned condition 43；
Shift aligned condition 43：The frame valid data that control valid data alignment module 4-4 starts to not least position are carried out
Low level shift align operation, obtain low level shift align operation frame valid data after, into indirect assignment state 44, otherwise enter
Enter idle condition 41；
Indirect assignment state 44：When obtaining valid data area by the frame valid data lowest order, oneself state is kept；
Otherwise idle condition 41 is entered.
With reference to Fig. 1 to Fig. 4 processes that illustratively data are tentatively extracted.It there are when in higher level's data cache module
When imitating data, module starts, and the mode decision in control module, the data validity under different mode is sentenced
Disconnected, Land use models guiding module carries out shifting registration process or directly inputs cache module guarantor in the case of comprising valid data
Deposit.The strategy of mode boot is, when valid data are then directly inputted to cache module by data lowest order；Work as valid data
It is not after then first carrying out shift align operation by lowest order, then inputs to cache module.Also, each group of output data,
All it is responsible for calculating the valid data position wherein included by control module.
Data carry out proceeding by splicing after tentatively extracting, the flow of data splicing：First to including significance bit
Input data carry out length comparison, the length of the data, i.e. its valid data number included and a upper cycle is not complete
Length into splicing data is compared, it is determined that wanting the digit of data intercept, the digit of remaining data and judging that this splicing is
The no splicing for being enough to complete a data.Next, according to the digit of the data intercept calculated by this cycle data and upper one
Cycle remaining data is sent into concatenation module and carries out splicing, while the length for calculating splicing is conveyed to length comparison module.
Remaining data input shift module, it is mobile to a high position.Spliced data have two kinds of situations：A kind of is the data whole of input
Length does not export then now still not enough, it is necessary to splice again after being spliced, as a result by splicing selecting module choose after
It is continuous to be spliced next time；One kind is that data do not participate in splicing all, and remaining data are shifted, splice the data of completion by
Export selecting module and determine output, remaining data are spliced selecting module and choose the concatenation participated in next time.
The design of memory module：The setting one of memory module is to ensure that the result of upper level module does not influence next stage
The computing of module, ensure the accurate transmission of data and improve throughput.When the situation for having frame data to be rejected occurs, form school
Test module 2 does not have data output for some time, but has no effect on processing of the data extraction module 4 to data, as long as frame number
According to there is remaining data in memory module 3, computing would not stop；Second, in order to subsequently need temporarily to preserve data, this hair
The bright parsing for satellite down-link data is for other equipment or librarian use, therefore, in the last of extraction plus parsing data
Memory module 5 is to be used to preserve data to be sent temporarily.
The present invention is for meeting AOS standards, the data of any Service Data Unit of carrying are extracted and with any bit wide
Restructuring.
AOS of the present invention is a kind of more flexible data format protocol, in agreement to specific data unit length simultaneously
There is no strict limitation, a route can be included according to the data field to the introduction to AOS data formats, a frame AOS data
Protocol Data Unit MPDU (Multiplexing Protocol Data Unit), a bit stream protocol Data Unit BPDU
(Bitstream Protocol Data Unit), pseudo channel incision Service Data Unit VCASDU (Virtual
Channel Access Service Data Unit) or invalid data in one kind.
For convenience of the mode of operation of the present invention is understood, now citing includes bit stream protocol Data Unit BPDU AOS frame data
Illustrate the extracting mode of data cell.Illustratively BPDU composition first, as shown in table 2.
Table 2
Wherein, reservation spare bit is standing is set to " 00 ", may insert invalid number after bit stream data in BPDU data fields
According to bit stream data pointer is the position for being used to refer to last valid data.
Below i.e. for carrying the handling process after the AOS data flows of BPDU data cells enter present system：
AOS frame data enter system in the form of data flow, can regard the data of successive frame, and frame header position, frame number as
It is all known according to length.Next frame data are verified, judges its essential information correctness carried, information is correct
Frame data continue transmission downwards.The data cell carried in frame data is extracted again, the pattern of extraction can be set, here really
Determine mode of operation to extract for BPDU data cells, the bit stream data pointer in BPDU top guides is first read before extraction, determines each frame
The data volume extracted is needed in data, data cell is moved to by displacement and originated by low level, so obtains one by
Beginning position start and length known to data field to be extracted, into splicing, concatenation module is by calculating these data fields
Data are shifted length and splicing, is spliced to setting length and then exports, otherwise waits for next frame data and continue to splice.
Above is the example extracted to the BPDU data cells in AOS data flows, similarly, the present invention can be also directed to
Other Service Data Units in AOS business are extracted, and go back protosatellite science load data.
Embodiment six：Illustrate present embodiment with reference to Fig. 1 and Fig. 2, FPGA is based on described in present embodiment
AOS satellite data transmission valid data area extracting method, it includes：
The step of for by AOS standard frame data Cun Chudao satellite loads data memory module 1；
Verification is compared in essential information for being carried by format check module 2 to AOS standards frame data, gives up mistake
Frame data by mistake, the step of exporting correct frame data；
The step of for the storage of correct frame data to be arrived into frame data memory module 3；
For being required by data extraction module 4 according to data pattern correct frame data, carried according to data cell
The step of taking, and being spliced into expected length parsing data；
The step of for data Cun Chudao parsing data memory module 5 will to be parsed.
The annexation of each module of satellite load data extraction method accelerated is calculated described in present embodiment based on FPGA
As shown in Figure 1.Wherein satellite load data memory module 1 stores to AOS standard frame data, remains subsequent treatment.Lattice
The essential information carried in the frame data that formula correction verification module 2 passes down to satellite is compared, and prevents wrong frame data, once
There is erroneous frame and give up data.Frame data memory module 3 is used for storage information and compares errorless frame data, prevents upper level mould
Block occurs having an impact Subordinate module during the situation that frame is given up.Data extraction module 4 according to different mode demand, to frame number
According to different pieces of information unit extracted, and be spliced into the data of uniform length.Data memory module 5 is parsed to be used to preserve parsing
The data of completion, used for other users.
Format check module 2 in present embodiment carries out verification judgement to the data of input, leaves correct frame data.
Data extraction module 4 is extracted according to the length change of valid data under different mode and carries out the splicing of designated length, most
The data flow of valid data is exported afterwards.
Embodiment seven：Illustrate present embodiment with reference to Fig. 2, present embodiment is made into one to embodiment six
The step of step illustrates, exports correct frame data includes：
For monitoring the process signal of pending AOS standards frame data and to Inspection by verifying control module 2-1
The step of module 2-2 and output selecting module 2-3 are controlled；
For by Inspection module 2-2, according to verification control module 2-1 comparison control signal to AOS standard frames
Processing is compared in data, it is determined that the step of current AOS standards frame data are wrong frame data or correct frame data；The mistake
Frame data and correct frame data are the frame data for meeting AOS forms；
For by exporting selecting module 2-3, according to verification control module 2-1 output control signal to wrong frame data
Or correct frame data carry out selection output, by erroneous frame rejection of data, the step of exporting correct frame data.
Format check module 2 in present embodiment is used for the verification for completing VCDU essential informations, and information is correctly counted
According to the downward previous module transmission of frame, mistake give up.It is AOS frame data that it, which is inputted, and after format check, output is to meet
The frame data of AOS forms.
Embodiment eight：Illustrate present embodiment with reference to Fig. 3, present embodiment is made into one to embodiment seven
Step explanation, verification control module 2-1 include four kinds of state of a controls, and respectively idle condition 21, control information compares state 22, control
System gives up erroneous frame data mode 23 and control exports correct frame data state 24,
Idle condition 21：Etc. to be launched, when monitoring the process signal of pending AOS standards frame data, into control
Information compares state 22；
Control information compares state 22：Processing is compared to AOS standard frame data to correction verification module 2-2 in control ratio, when
Inspection module 2-2 determines current AOS standards frame data when being correct frame data, and correct frame data state is exported into control
24；When it is wrong frame data that Inspection module 2-2, which determines current AOS standards frame data, into giving up mistake frame data shape
State 23；
Control exports correct frame data state 24：Export correct frame data；When monitoring pending AOS standards frame data
During process signal, state 22 is compared into control information, otherwise into idle condition 21；
Erroneous frame data mode 23 is given up in control：Give up mistake frame data；When monitoring pending AOS standards frame data
During process signal, state 22 is compared into control information, otherwise into idle condition 21.
The state machine of present embodiment is used to realize the behaviour to be launched such as control, idle condition 21 to form correction verification module 2
Make, when pending data in upper level cache module be present, module starts, and control information is entered after startup and compares shape
State 22, comparison result enter output selecting module 2-3 as Rule of judgment, and when comparison result is correct, data are defeated as virtual value
Go out, comparison result mistake then gives up data.The data for entering module after starting every time are all complete frame data.
Embodiment nine：Illustrate present embodiment with reference to Fig. 2, present embodiment to embodiment six, seven or
Eight are described further, and being spliced into the step of expected length parses data includes：
For the setting mode of operation logarithm by extracting control module 4-1 it is judged that module 4-2, mode boot module 4-
The step of 3 and significance bit computing module 4-6 is controlled；
For by data judge module 4-2 according to extraction control module 4-1 judgement control signal to transmitting each time
Correct frame data in invalid data given up, obtain frame valid data the step of；
For by mode boot module 4-3, according to extraction control module 4-1 mode control signal to frame valid data
Pattern judged, determine valid data area be by lowest order or by not least position the step of；
For being carried out by valid data alignment module 4-4 to valid data area by the frame valid data not least position
The step of to low level shift align operation；
For the valid data area that is exported by data cache module 4-5 to mode boot module 4-3 by lowest order
Frame valid data and valid data alignment module 4-4 carry out the frame valid data after low level shift align operation and stored
Step；
For being worked as by significance bit computing module 4-6 according to extraction control module 4-1 mode of operation signal of change
The step of valid data bit length that previous framing effective data packets contain；
For will be included by length comparison module 4-7 according to parsing data predicting length when previous framing valid data
Valid data bit length is compared with the length of the current period concatenation module 4-8 splicing data exported, it is determined that for current
Whether data bits, remaining data digit and the judgement that one framing valid data to be intercepted are enough to complete one by this splicing
The step of splicing of data；
The data bits to be intercepted for being exported by concatenation module 4-8 according to length comparison module 4-7 will work as previous
Framing valid data and the unfinished splicing data of current period splicing selecting module 4-11 outputs carry out splicing and worked as
Preceding splicing data, and calculate and obtain the step of length of data is completed in current splicing；
For ought according to the length comparison module 4-7 remaining data digits exported by remaining data shift module 4-9
Remaining valid data obtain the step of data are spliced in displacement to a high position is mobile in previous framing valid data；
Signal is completed in data splicing for being exported by exporting selecting module 4-10 according to length comparison module 4-7 to be made to work as
The step of preceding splicing data are as parsing data selection output；
Data splicing for being exported by splicing selecting module 4-11 according to length comparison module 4-7 completes signal to defeated
Go out the parsing data of selecting module 4-10 outputs and the displacement splicing data of remaining data shift module 4-9 outputs selected,
The step of for splicing next time.
The function of data extraction module 4 is by the phase in each frame data according to different mode of operations in present embodiment
Answer data area to be extracted and carry out splicing restructuring according to specified length.The challenge of this module is flexible quick data
Disposal ability, the data of one section of indefinite length in different frame data are extracted to the data for being spliced into regular length.Module
Input is AOS form frame data, and output is the data flow for the regular length that valid data are formed.
Here the method for the extraction data used is all to be moved for the data of part to be extracted to low level alignment, together
When for the mode of operation of setting calculate the byte number for needing to extract data, frame data by displacement and its comprising it is effective
Byte number is as output, and Subordinate module can obtain the precise area of valid data accordingly, and the data field is by lowest byte
Start, convenient that data are completed to splice, therefore, the processing to data is tentatively extracted that is, having carried out data.
Embodiment ten：Illustrate present embodiment with reference to Fig. 4, present embodiment is made into one to embodiment nine
Step explanation, extraction control module 4-1 include four kinds of states, respectively idle condition 41, mode decision state 42, displacement alignment shape
State 43 and indirect assignment state 44；
Idle condition 41：Wait, when monitoring correct frame data, Dietary behavior judges state 42；
Mode decision state 42：Control data judge module 4-2 is to the invalid number in the correct frame data that transmit each time
According to being given up, frame valid data are obtained, then control model guiding module 4-3 determines the pattern of frame valid data, works as significant figure
It is by lowest order during pattern, into indirect assignment state 44 according to area；When valid data area is that not least position starts pattern,
Into displacement aligned condition 43；
Shift aligned condition 43：The frame valid data that control valid data alignment module 4-4 starts to not least position are carried out
Low level shift align operation, obtain low level shift align operation frame valid data after, into indirect assignment state 44, otherwise enter
Enter idle condition 41；
Indirect assignment state 44：When obtaining valid data area by the frame valid data lowest order, oneself state is kept；
Otherwise idle condition 41 is entered.
With reference to Fig. 1 to Fig. 4 processes that illustratively data are tentatively extracted.It there are when in higher level's data cache module
When imitating data, module starts, and the mode decision in control module, the data validity under different mode is sentenced
Disconnected, Land use models guiding module carries out shifting registration process or directly inputs cache module guarantor in the case of comprising valid data
Deposit.The strategy of mode boot is, when valid data are then directly inputted to cache module by data lowest order；Work as valid data
It is not after then first carrying out shift align operation by lowest order, then inputs to cache module.Also, each group of output data,
All it is responsible for calculating the valid data position wherein included by control module.
Data carry out proceeding by splicing after tentatively extracting, the flow of data splicing：First to including significance bit
Input data carry out length comparison, the length of the data, i.e. its valid data number included and a upper cycle is not complete
Length into splicing data is compared, it is determined that wanting the digit of data intercept, the digit of remaining data and judging that this splicing is
The no splicing for being enough to complete a data.Next, according to the digit of the data intercept calculated by this cycle data and upper one
Cycle remaining data is sent into concatenation module and carries out splicing, while the length for calculating splicing is conveyed to length comparison module.
Remaining data input shift module, it is mobile to a high position.Spliced data have two kinds of situations：A kind of is the data whole of input
Length does not export then now still not enough, it is necessary to splice again after being spliced, as a result by splicing selecting module choose after
It is continuous to be spliced next time；One kind is that data do not participate in splicing all, and remaining data are shifted, splice the data of completion by
Export selecting module and determine output, remaining data are spliced selecting module and choose the concatenation participated in next time.
The design of memory module：The setting one of memory module is to ensure that the result of upper level module does not influence next stage
The computing of module, ensure the accurate transmission of data and improve throughput.When the situation for having frame data to be rejected occurs, form school
Test module 2 does not have data output for some time, but has no effect on processing of the data extraction module 4 to data, as long as frame number
According to there is remaining data in memory module 3, computing would not stop；Second, in order to subsequently need temporarily to preserve data, this hair
The bright parsing for satellite down-link data is for other equipment or librarian use, therefore, in the last of extraction plus parsing data
Memory module 5 is to be used to preserve data to be sent temporarily.
The present invention is for meeting AOS standards, the data of any Service Data Unit of carrying are extracted and with any bit wide
Restructuring.
Claims (6)
1. a kind of AOS satellite data transmission valid data area extraction system based on FPGA, it is characterised in that it includes：
For storing the satellite load data memory module (1) of AOS standard frame data；
Verification is compared in essential information for being carried to AOS standards frame data, gives up mistake frame data, exports correct frame number
According to format check module (2)；
For storing the frame data memory module (3) of correct frame data；
For being required according to data pattern correct frame data, after being extracted according to data cell, expected length solution is spliced into
Analyse the data extraction module (4) of data；
Parsing data memory module (5) for storing and resolving data；
Format check module (2) includes：
For monitoring the process signal of pending AOS standards frame data and to comparing correction verification module (2-2) and output selecting module
The verification control module (2-1) that (2-3) is controlled；
For processing to be compared to AOS standard frame data according to the comparison control signal of verification control module (2-1), it is determined that working as
Preceding AOS standards frame data are the Inspection module (2-2) of wrong frame data or correct frame data；Wrong frame data and just
True frame data are the frame data for meeting AOS forms；
Wrong frame data or correct frame data select for the output control signal according to verification control module (2-1) defeated
Go out, by erroneous frame rejection of data, export the output selecting module (2-3) of correct frame data；
Verification control module (2-1) includes four kinds of state of a controls, and respectively idle condition (21), control information compares state
(22), erroneous frame data mode (23) is given up in control and control exports correct frame data state (24),
Idle condition (21)：Etc. to be launched, when monitoring the process signal of pending AOS standards frame data, believe into control
Cease comparison state (22)；
Control information compares state (22)：Processing is compared to AOS standard frame data to correction verification module (2-2) in control ratio, when
Inspection module (2-2) determines current AOS standards frame data when being correct frame data, and correct frame data shape is exported into control
State (24)；When it is wrong frame data that Inspection module (2-2), which determines current AOS standards frame data, into giving up erroneous frame
Data mode (23)；
Control exports correct frame data state (24)：Export correct frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state (22) is compared into control information, otherwise into idle condition (21)；
Erroneous frame data mode (23) is given up in control：Give up mistake frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state (22) is compared into control information, otherwise into idle condition (21).
2. the AOS satellite data transmission valid data area extraction system according to claim 1 based on FPGA, it is characterised in that
Data extraction module (4) includes：
For according to setting mode of operation logarithm it is judged that module (4-2), mode boot module (4-3) and significance bit computing module
The extraction control module (4-1) that (4-6) is controlled；
For the judgement control signal according to extraction control module (4-1) to the invalid number in the correct frame data that transmit each time
According to being given up, the data judge module (4-2) of frame valid data is obtained；
The pattern of the valid data in frame valid data is carried out for the mode control signal according to extraction control module (4-1)
Judge, determine that valid data area is by lowest order or by the mode boot module not least position in frame valid data
(4-3)；
For the frame valid data that valid data area is started from not least position to be carried out with the significant figure to low level shift align operation
According to alignment module (4-4)；
For to the valid data area that mode boot module (4-3) exports by the frame valid data and valid data lowest order
The data cache module (4-5) that frame valid data after alignment module (4-4) progress low level shift align operation are stored；
For being obtained according to the mode of operation signal of change of extraction control module (4-1) when what previous framing valid data included has
Imitate the significance bit computing module (4-6) of data bit length；
For by the valid data bit length included when previous framing valid data and currently all according to parsing data predicting length
The length of the splicing data of phase concatenation module (4-8) output is compared, it is determined that for be intercepted when previous framing valid data
Data bits, remaining data digit and length of splicing for judging whether to be enough to complete a data by this splicing compare
Module (4-7)；
For the data bits to be intercepted that is exported according to length comparison module (4-7) will work as previous framing valid data with it is current
The unfinished splicing data of cycle splicing selecting module (4-11) output carry out splicing and obtain current splicing data, and calculate
Obtain the concatenation module (4-8) that the length of data is completed in current splicing；
Remaining data digit for being exported according to length comparison module (4-7) will be worked as remaining effective in previous framing valid data
Data shift the remaining data shift module (4-9) for splicing data to high-order mobile obtain；
Signal is completed in data splicing for being exported according to length comparison module (4-7) makes currently to splice data as parsing data
Select the output selecting module (4-10) of output；
Data splicing for being exported according to length comparison module (4-7) completes signal to output selecting module (4-10) output
Parsing data and the displacement splicing data of remaining data shift module (4-9) output are selected, for the spelling spliced next time
Connect selecting module (4-11).
3. the AOS satellite data transmission valid data area extraction system according to claim 2 based on FPGA, it is characterised in that
Extraction control module (4-1) includes four kinds of states, respectively idle condition (41), mode decision state (42), displacement alignment shape
State (43) and indirect assignment state (44)；
Idle condition (41)：Wait, when monitoring correct frame data, Dietary behavior judges state (42)；
Mode decision state (42)：Control data judge module (4-2) is to the invalid number in the correct frame data that transmit each time
According to being given up, frame valid data are obtained, then control model guiding module (4-3) determines the pattern of frame valid data, when effective
Data field is by lowest order during pattern, into indirect assignment state (44)；When valid data area is that not least position starts mould
During formula, into displacement aligned condition (43)；
Shift aligned condition (43)：The frame valid data that control valid data alignment module (4-4) starts to not least position are carried out
Low level shift align operation, after the frame valid data for obtaining low level shift align operation, into indirect assignment state (44), otherwise
Into idle condition (41)；
Indirect assignment state (44)：When obtaining valid data area by the frame valid data lowest order, oneself state is kept；It is no
Then enter idle condition (41).
4. a kind of AOS satellite data transmission valid data area extracting method based on FPGA, it is characterised in that it includes：
The step of for by AOS standard frame data Cun Chudao satellite loads data memory modules (1)；
Verification is compared in essential information for being carried by format check module (2) to AOS standards frame data, gives up mistake
Frame data, the step of exporting correct frame data；
The step of for the storage of correct frame data to be arrived into frame data memory module (3)；
For being required by data extraction module (4) according to data pattern correct frame data, extracted according to data cell,
And the step of being spliced into expected length parsing data；
The step of for data Cun Chudao parsing data memory module (5) will to be parsed；
The step of exporting correct frame data includes：
For monitoring the process signal of pending AOS standards frame data and to comparing calibration mode by verifying control module (2-1)
The step of block (2-2) and output selecting module (2-3) are controlled；
For by Inspection module (2-2), according to the comparison control signal of verification control module (2-1) to AOS standard frames
Processing is compared in data, it is determined that the step of current AOS standards frame data are wrong frame data or correct frame data；The mistake
Frame data and correct frame data are the frame data for meeting AOS forms；
For by exporting selecting module (2-3), according to the output control signal of verification control module (2-1) to wrong frame data
Or correct frame data carry out selection output, by erroneous frame rejection of data, the step of exporting correct frame data；
Verification control module (2-1) includes four kinds of state of a controls, and respectively idle condition (21), control information compares state
(22), erroneous frame data mode (23) is given up in control and control exports correct frame data state (24),
Idle condition (21)：Etc. to be launched, when monitoring the process signal of pending AOS standards frame data, believe into control
Cease comparison state (22)；
Control information compares state (22)：Processing is compared to AOS standard frame data to correction verification module (2-2) in control ratio, when
Inspection module (2-2) determines current AOS standards frame data when being correct frame data, and correct frame data shape is exported into control
State (24)；When it is wrong frame data that Inspection module (2-2), which determines current AOS standards frame data, into giving up erroneous frame
Data mode (23)；
Control exports correct frame data state (24)：Export correct frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state (22) is compared into control information, otherwise into idle condition (21)；
Erroneous frame data mode (23) is given up in control：Give up mistake frame data；When the place for monitoring pending AOS standards frame data
When managing signal, state (22) is compared into control information, otherwise into idle condition (21).
5. the AOS satellite data transmission valid data area extracting method according to claim 4 based on FPGA, it is characterised in that
The step of being spliced into expected length parsing data includes：
For the setting mode of operation logarithm by extracting control module (4-1) it is judged that module (4-2), mode boot module
The step of (4-3) and significance bit computing module (4-6) are controlled；
For by data judge module (4-2) according to extraction control module (4-1) judgement control signal to transmitting each time
Correct frame data in invalid data given up, obtain frame valid data the step of；
For by mode boot module (4-3), according to the mode control signal of extraction control module (4-1) to frame valid data
Pattern judged, determine valid data area be by lowest order or by not least position the step of；
For the frame valid data that valid data area is started from not least position are carried out by valid data alignment module (4-4) to
The step of low level shift align operation；
For the valid data area that is exported by data cache module (4-5) to mode boot module (4-3) by lowest order
Frame valid data and valid data alignment module (4-4) carry out low level shift align operation after frame valid data stored
The step of；
For being worked as by significance bit computing module (4-6) according to the mode of operation signal of change of extraction control module (4-1)
The step of valid data bit length that previous framing effective data packets contain；
For will be had by length comparison module (4-7) according to parsing data predicting length when what previous framing valid data included
Data bit length is imitated compared with the length for the splicing data that current period concatenation module (4-8) exports, it is determined that for current
Whether data bits, remaining data digit and the judgement that one framing valid data to be intercepted are enough to complete one by this splicing
The step of splicing of data；
The data bits to be intercepted for being exported by concatenation module (4-8) according to length comparison module (4-7) will work as previous
Framing valid data and the unfinished splicing data of current period splicing selecting module (4-11) output carry out splicing acquisition
Current splicing data, and calculate and obtain the step of length of data is completed in current splicing；
Remaining data digit for being exported by remaining data shift module (4-9) according to length comparison module (4-7) ought
Remaining valid data obtain the step of data are spliced in displacement to a high position is mobile in previous framing valid data；
Signal is completed in data splicing for being exported by exporting selecting module (4-10) according to length comparison module (4-7) to be made to work as
The step of preceding splicing data are as parsing data selection output；
Data splicing for being exported by splicing selecting module (4-11) according to length comparison module (4-7) completes signal to defeated
Go out the parsing data of selecting module (4-10) output and the displacement splicing data of remaining data shift module (4-9) output are selected
Select, the step of for splicing next time.
6. the AOS satellite data transmission valid data area extracting method according to claim 5 based on FPGA, it is characterised in that
Extraction control module (4-1) includes four kinds of states, respectively idle condition (41), mode decision state (42), displacement alignment shape
State (43) and indirect assignment state (44)；
Idle condition (41)：Wait, when monitoring correct frame data, Dietary behavior judges state (42)；
Mode decision state (42)：Control data judge module (4-2) is to the invalid number in the correct frame data that transmit each time
According to being given up, frame valid data are obtained, then control model guiding module (4-3) determines the pattern of frame valid data, when effective
Data field is by lowest order during pattern, into indirect assignment state (44)；When valid data area is that not least position starts mould
During formula, into displacement aligned condition (43)；
Shift aligned condition (43)：The frame valid data that control valid data alignment module (4-4) starts to not least position are carried out
Low level shift align operation, after the frame valid data for obtaining low level shift align operation, into indirect assignment state (44), otherwise
Into idle condition (41)；
Indirect assignment state (44)：When obtaining valid data area by the frame valid data lowest order, oneself state is kept；It is no
Then enter idle condition (41).
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