CN105049834B - Real-time auto-stereoscopic playing system based on FPGA (Field Programmable Gate Array) - Google Patents
Real-time auto-stereoscopic playing system based on FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention discloses a real-time auto-stereoscopic playing system based on an FPGA (Field Programmable Gate Array). The system comprises a video input module, a DDR (Double Data Rate) storage control module, a DDR memory, a data splitting module, a target image generation module and an on-screen display module, wherein the video input module alternatively receives and combines reference image data and a corresponding depth image, and alternatively sends the combined data to a DDR storage control module; the DDR storage control module stores the reference image data and the depth image data to the DDR memory and outputs to the data splitting module according to a line spacing; the data splitting module splits the received reference image data and depth image data and sends to the target image generation module; the target image generation module synthesizes N target images through a DIBR (Depth Image Based Rendering) algorithm so as to form N stereo image pairs; a multi-view image fusion module fuses the N stereo image pairs to obtain a synthetic image of the N stereo image pairs and sends to the on-screen display module to carry out on-screen display. According to the system, real-time playing of a 3D (Three-Dimensional) video is implemented.
Description
Technical field
The invention belongs to Naked 3D technology field, more specifically, it is related to a kind of real-time Naked 3D based on FPGA to broadcast
Place system.
Background technology
Bore hole 3D shows that (auto-stereoscopic display, also referred to as free stereo show for i.e. Naked stereoscopic display
Show), cardinal principle is to utilize human eye parallax characteristic, can be simultaneously naked (auxiliary without the wearing helmet, polariscope etc. regarding condition in many people
Help equipment) under show the lifelike stereoscopic image being suspended in spatial depth and image outside screen.In fact many research aircrafts
Structure has had begun to the research shown to Naked 3D, including major universities and colleges, research institute, company etc..Britain Reality Vision
Company more early proposes HAD (Holographic Autostereoscopic Display, holographic Auto-stereo display) technology
Concept, is the important advance of bore hole formula 3D technology.2009, the PureDepth companies in the U.S. researched and developed similar technique MLD
(Multi-Layer Display, Multi-level display technology), using multilayer LCD in tandem, difference display foreground and background, shape
Into front and rear depth perception.With continuing to develop for 3D TV tech, many different types of 3D video formats (3D video are occurred in that
format).Wherein 3D videos (the depth-image-based 3D video) form based on depth image is by its compatibility
Good, implementation is easy, be widely accepted the characteristics of be widely used.The characteristics of this 3D video formats is by video and its right
The depth image answered is constituted.Wherein depth image is gray level image of the width gray value 0~255, and each gray value is with 8
Bit is represented.This form to the benefit that the realization of 3D television systems brings mainly have it is following some：
1. the view of a range of any viewpoint can be generated in decoding end, there is stronger interactivity；
2. stereotelevision function just can be realized by transmission of one line video and its corresponding depth image, occupied bandwidth is small,
Code efficiency is high；
3. 2D/3D switchings are very convenient, when television set only shows video section without performing DIBR functions, just switch to
2D videos；
4. various stereoscopic display devices (including auto-stereoscopic display, holographic imaging systems) are easily supported.
At present, it is responsible for the H.264 joint video team (Joint Video Team, JVT) of standard formulation and European
ATTEST projects are it is recommended that using the 3D video formats of " video+depth ", HDMI (High Definition Multimedia
Interface, HDMI) latest edition 1.4 of standard also supported " left view+depth (Left+depth) "
Deng 3D video formats.
However, the real-time player of this form is supported at present seldom, so research is a kind of to support to be based on depth image
The bore hole 3D players of 3D video on live just seem and are even more important.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, there is provided a kind of real-time Naked 3D based on FPGA plays system
System, realizes the generation and fusion to N number of stereo pairs, realizes the real-time broadcasting of 3D videos.
For achieving the above object, real-time Naked 3D Play System of the present invention based on FPGA, including video input mould
Block, DDR storage control modules, DDR memory, data split module, target image generation module, multi-view image Fusion Module
With upper screen display module, wherein：
Video input module alternately receives reference image data and corresponding depth image, is write every time according to DDR memory
The data package size for entering or reading data is combined to reference image data and depth image data respectively, by the number after combination
DDR storage control modules are sent to according to replacing；Combination is expressed as with formula：
a1(3x+b1)=z
a2(y+b2)=z
Wherein, x represents the digit of each component data in three RGB components of each pixel in reference image data, y tables
Show the digit of each pixel data in depth image data, z represents DDR memory write-in or the data package size for reading every time；
a1Represent the number of combinations of color component data, a1It is positive integer, b1High-order zero padding position is individual when representing that reference image data is combined
Number, b1It is nonnegative integer；a2Represent the number of combinations of depth data, a2It is positive integer, b2It is high when representing that depth image data is combined
The number of position zero padding position, b2It is nonnegative integer；
DDR storage control modules receive the reference image data and depth image data of video input module output, storage
To DDR memory, then module is split according to a line reference image data, a line depth image data interval output to data；
Data split rule of combination of the module according to reference image data and depth image data in video input module
Reference image data and depth image data to receiving split, and delete high-order zero padding position, the number that will be obtained after fractionation
According to being sent to target image generation module；
The reference picture and its corresponding depth image that target image generation module will be received are joined according to default N number of viewpoint
Number synthesizes N number of target image by DIBR algorithms, reference picture and each target image is respectively constituted into stereo pairs, by N
Individual stereo pairs are sent to multi-view image Fusion Module；
N number of stereo pairs are carried out sub-pixel extraction by multi-view image Fusion Module, and fusion obtains N number of stereo pairs
Composograph, be sent to screen display module；
Upper screen display module carries out upper screen and shows to composograph.
The present invention based on FPGA real-time Naked 3D Play System, including video input module, DDR storage control modules,
DDR memory, data split module, target image generation module and upper screen display module, and video input module alternately receives ginseng
Examine view data and corresponding depth image and be combined, the data after combination are alternately sent to DDR storage control modules；
DDR storage control modules store to DDR memory reference image data and depth image data, and are exported to number by between-line spacing
According to fractionation module；Data split module and are split according to the reference image data and depth image data to receiving, and send
Give target image generation module；Target image generation module synthesizes N number of target image by DIBR algorithms, constitutes N number of stereogram
As right；The fusion of N number of stereo pairs is obtained multi-view image Fusion Module the composograph of N number of stereo pairs, is sent to
Upper screen display module carries out screen and shows.The present invention realizes the real-time broadcasting to 3D videos.
Brief description of the drawings
Fig. 1 is the specific embodiment structure chart of real-time Naked 3D Play System of the present invention based on FPGA；
Fig. 2 is the specific embodiment structural representation of video input module；
Fig. 3 is the structural representation of DDR storage control modules；
Fig. 4 is the specific embodiment structure chart of Naked 3D Play System of the present invention；
Fig. 5 is the structure chart of hdmi_in modules in Fig. 4；
Fig. 6 is the structure chart of MPMC modules in Fig. 4；
Fig. 7 is DDR read-write sequence figures；
Fig. 8 is ddr2_cmd emulation Time-Series analysis figures；
Fig. 9 is the structure chart of col_dep_div modules.
Specific embodiment
Specific embodiment of the invention is described below in conjunction with the accompanying drawings, so as to those skilled in the art preferably
Understand the present invention.Requiring particular attention is that, in the following description, when known function and design detailed description perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Fig. 1 is the specific embodiment structure chart of real-time Naked 3D Play System of the present invention based on FPGA.Such as Fig. 1 institutes
Show, real-time Naked 3D Play System of the present invention based on FPGA includes that video input module 1, DDR storage control modules 2, DDR are deposited
Reservoir 3, data splits module 4, DIBR algoritic modules 5, multi-view image Fusion Module 6 and upper screen display module 7.In order that Fig. 1
It is more succinct clear, omit the systems such as clock module and power module necessity module.Each module is illustrated separately below.
● video input module 1
Video input module 1 alternately receives reference image data and corresponding depth image, that is, receive the first frame with reference to figure
As after data, receiving the corresponding depth image data of the first frame reference picture, the second frame reference image data is then received, then so
After be the corresponding depth image data of the second frame reference picture.Write or read the packet of data every time according to DDR memory
Size, is combined to reference image data and depth image data respectively, and combination is expressed as with formula：
a1(3x+b1)=z
a2(y+b2)=z
Wherein, x represents the digit of each component data in three RGB components of each pixel in reference image data, y tables
Show the digit of each pixel data in depth image data, z represents DDR memory write-in or the data package size for reading every time.
a1Represent the number of combinations of color component data, a1It is positive integer, b1High-order zero padding position is individual when representing that reference image data is combined
Number, b1It is nonnegative integer.a2Represent the number of combinations of depth data, a2It is positive integer, b2It is high when representing that depth image data is combined
The number of position zero padding position, b2It is nonnegative integer.The parameters of data combination, are all previously according to actual video input data
Set with DDR memory.This combination can be considered as the serioparallel exchange to reference image data and depth image data.
Data after combination are alternately sent to DDR storage control modules 2 by video input module 1.
Due to reference image data and depth image data be alternately input, therefore depth image data input port
A physical port can be shared with one of them in the three of reference image data component inputs mouthful, can so saved
Input port.
Fig. 2 is the specific embodiment structural representation of video input module 1.As shown in Fig. 2 video input module 1 is wrapped
Include startup control module 11, video read-write management module 12, reference picture cache module 13, depth image cache module 14.
Start the initialization completion signal that control module 11 monitors DDR memory, when initialization completion signal is effective,
Start frame is determined according to field sync signal, then enabling signal is sent to video read-write management module 12.Because input number
According to not necessarily since first pixel of a frame reference picture, so to determine start frame according to field sync signal.
Video read-write management module 12 receives the enabling signal for starting control module, alternately receives reference image data and right
The depth image answered, writes or reads the data package size of data every time according to DDR memory 3, according to respective rule of combination,
Control storage enables signal, and reference image data and depth image data are exported to reference picture cache module 13 and depth respectively
Degree image buffer storage module 14.
Reference image data after the caching combination of reference picture cache module 13, exports to DDR storage controls module 2.
Depth image data after the caching combination of depth image cache module 14, exports to DDR storage controls module 2.
Reference picture cache module 13 and depth image cache module 14 are alternately output when data output is carried out.
Using cache module, can solve to be input into the clock and store clock of reference image data and corresponding depth image
It is inconsistent, i.e. cross clock domain problem.
● DDR storage control modules
DDR storage control modules 2 receive the reference image data and depth image data of the output of video input module 1, storage
To DDR memory 3, then module 4 is split according to a line reference image data, a line depth image data interval output to data.
Fig. 3 is the structural representation of DDR storage control modules.As shown in figure 3, DDR storage control modules are produced including address
Raw module 21, read-write generation module 22, DDR controller control signal generation module 23 and DDR controller 24, specific works
Flow is as follows：
When the first two field picture, i.e. the first frame reference image data is received, address generating module 21 is according to DDR memory
In the first paragraph address space of reference image data that marks in advance export write initial address to DDR controller control signal line by line
Generation module 23；Read-write generation module 22 receives the first frame reference image data and is controlled as write-in data output to DDR
Device control signal generation module 23 processed, while exporting write control signal to DDR controller control signal generation module 23；DDR is controlled
Device control signal generation module 23 processed receives the initial address of writing of reference image data first paragraph address space, produces correspondence to write ground
Location, DDR controller 24 is sent to together with the write control signal for receiving and the first frame reference image data；DDR controller 24 exists
Under the control of write control signal, the first frame reference image data is stored in DDR memory according to write address；
When the second two field picture, the i.e. multiimage of the first frame reference picture is received, do not write or read operation；
When the corresponding depth image of the 3rd two field picture, i.e. the first frame reference picture is received, address generating module 21 is pressed
Exported line by line according to the first paragraph address space of depth image data marked in advance in DDR memory and write initial address and control to DDR
Device control signal generation module 23 processed；Read-write generation module 22 receives the first frame depth image data and as write-in data
Output is to DDR controller control signal generation module 23, while exporting write control signal to DDR controller control signal produces mould
Block 23；DDR controller control signal generation module 23 receives the initial address of writing of depth image data first paragraph address space, produces
The corresponding write address of life, DDR controller 24 is sent to together with the write control signal for receiving and the first frame depth image data；DDR
Be stored in the first frame reference image data in DDR memory according to write address under the control of write control signal by controller 24；
When the 4th two field picture, the i.e. multiimage of the first frame depth image is received, address generating module 21 is according to DDR
The first paragraph address space of the first paragraph address space of reference image data and depth image data is alternately defeated by row in memory
Go out the reading initial address of reference image data and depth image data to DDR controller control signal generation module 23；Read-write letter
Number generation module 22 produces reference image data and the read control signal of depth image data to export to DDR controller control signal
Generation module 23；DDR controller control signal generation module 23 receives the first paragraph address space and depth of reference image data
The reading initial address of the first paragraph address space of view data, produces corresponding reading address, together with the read control signal for receiving
It is sent to DDR controller 24；DDR controller 24 under the control of read control signal, according to reading address by the first frame reference picture
Data and the first frame depth image data read out from DDR memory, export and split module to data；The reading process will
It is continued until that the first frame reference image data and the first frame depth image data all read to finish；
When the 5th two field picture, i.e. the second frame reference picture is received, address generating module 21 is according to pre- in DDR memory
The second segment address space of the reference image data for first marking is exported line by line writes initial address to DDR controller control signal generation
Module 23；Read-write generation module 22 receives the second frame reference image data and as write-in data output to DDR controller
Control signal generation module 23, while exporting write control signal to DDR controller control signal generation module 23；DDR controller
Control signal generation module 23 receives the initial address of writing of reference image data second segment address space, and generation is corresponding to write ground
Location, DDR controller 24 is sent to together with the write control signal for receiving and the second frame reference image data；DDR controller 24 exists
Under the control of write control signal, the first frame reference image data is stored in DDR memory according to write address；
When the 6th two field picture, the i.e. multiimage of the second frame reference picture is received, do not write or read operation；
When the corresponding depth image of the 7th two field picture, i.e. the second frame reference picture is received, address generating module 21 is pressed
Exported line by line according to the second segment address space of depth image data marked in advance in DDR memory and write initial address and control to DDR
Device control signal generation module 23 processed；Read-write generation module 22 receives the second frame depth image data and as write-in data
Output is to DDR controller control signal generation module 23, while exporting write control signal to DDR controller control signal produces mould
Block 23；DDR controller control signal generation module 23 receives the initial address of writing of depth image data second segment address space, produces
The corresponding write address of life, DDR controller 24 is sent to together with the write control signal for receiving and the second frame depth image data；
Be stored in the second frame reference image data in DDR memory according to write address under the control of write control signal by DDR controller 24；
When the 8th two field picture, the i.e. multiimage of the second frame depth image is received, address generating module 21 is according to DDR
The second segment address space of the second segment address space of reference image data and depth image data is alternately defeated by row in memory
Go out the reading initial address of reference image data and depth image data to DDR controller control signal generation module 23；Read-write letter
Number generation module 22 produces reference image data and the read control signal of depth image data to export to DDR controller control signal
Generation module 23；DDR controller control signal generation module 23 receives the second segment address space and depth of reference image data
The reading initial address of the second segment address space of view data, produces corresponding reading address, together with the read control signal for receiving
It is sent to DDR controller 24；DDR controller 24 under the control of read control signal, according to reading address by the second frame reference picture
Data and the second frame depth image data read out from DDR memory, export and split module to data；The reading process will
It is continued until that the second frame reference image data and the second frame depth image data all read to finish；
Follow-up each picture frame is circulated according to the first frame to the processing mode of the 8th frame, until image end of input.
● DDR memory
DDR memory 3 is used to store reference image data and depth image data that DDR storage control modules 2 send.
● data split module
Data split combination rule of the module 4 according to reference image data and depth image data in video input module 1
Then the reference image data and depth image data that receive are split, high-order zero padding position is deleted, by what is obtained after fractionation
Data is activation is to target image generation module 5.That is, data split the reference that module 4 will read from DDR memory 3
View data and depth image data are reduced into the data pattern of the reception of video input module 1, and due to DDR storage control moulds
The storage control of block 2, eliminates image reproduction data, only remains effective view data.
● target image generation module
Target image generation module 5 N number of is regarded according to the reference picture and its corresponding depth image that receive according to default
Point parameter synthesizes N number of target image by DIBR algorithms, and reference picture and each target image are respectively constituted into stereo pairs,
N number of stereo pairs are sent to multi-view image Fusion Module 6.
● multi-view image Fusion Module
N number of stereo pairs are carried out sub-pixel extraction by multi-view image Fusion Module 6, and fusion obtains N number of stereo-picture
To composograph, be sent to screen display module 7.
● above shield display module
Upper screen display module 7 carries out upper screen and shows to composograph.
Embodiment
Below with a specific embodiment, to be illustrated to technical scheme.
Fig. 4 is the specific embodiment structure chart of Naked 3D Play System of the present invention.
As shown in figure 4, in the present embodiment, bore hole 3D Play Systems include that video input module hdmi_in, DDR store control
Molding block MPMC, image split module col_dep_div, image co-registration module comp_dibr and upper screen display module lvds, with
And one be used for provide the Clock management module blk_ddr2_dcm of clock signal and for storage image data
DDR2SDRAM.These modules are illustrated in detail below.
1st, blk_ddr2_dcm modules
Blk_ddr2_dcm be used to generating reset signal rst_n and the two pairs of differential clock signals (clk0 and clk90,
Clk200 and clkdiv0) used for internal system, the module is consistent with the function of the Clock management module commonly used in FPGA,
This is repeated no more.
2nd, hdmi_in modules
Hdmi_in modules are used to reading in vision signal (including colored reference image data and corresponding depth image number
According to), exported after being reconfigured to data.In the present embodiment, DDR memory uses DDR2SDRAM, its each write-in
Or when reading data, data package size is 128bit.The resolution ratio of each image is 1280*720, reference picture in vision signal
During input, each component data of RGB is 10bit, is combined into the form of the three of pixel RGB components are mended into 0 with two high
One data of 32bit, in output, the data of every 4 32bit are combined into 1 data output of 128bit, i.e., every 4 pixels
Data exported for one group, combinatorial formula can be expressed as 4 (3*10+2)=128.When depth image is input into, each pixel
Data be 8bit, output when 16 pixel datas are combined into 1 data output of 128bit, combinatorial formula can be represented
It is 16* (8+0)=128.
Fig. 5 is the structure chart of hdmi_in modules in Fig. 4.Table 1 is the input/output port list of hdmi_in modules.Right
When colored diagram data is processed, tri- color components of RGB are by hdmi_write_read_process block combiners into
32bit data are transferred to hdmi_col_ram, and signal is combined into 128bit by hdmi_col_ram again；Meanwhile, to depth map number
During according to being processed, because depth map data only has one-component, therefore only made by the least-significant byte of B component (i.e. hdmi_qb signals)
For signal is combined into 128bit by depth map data signal transmission to hdmi_dep_ram, then by hdmi_dep_ram.
Table 1
As shown in figure 5, hdmi_in modules include 4 submodules in the present embodiment, it is respectively to start control module clr_
Gen, video read-write management module hdmi_write_read_process；Input reference picture cache module hdmi_col_ram,
Input depth image cache module hdmi_dep_ram.
2.1clr_gen module
The initialization completion signal phy_init_done of clr_gen module monitors DDR memories, works as phy_init_done
For it is effective when, start frame is determined according to field sync signal hdmi_vsync, then to video read-write management module hdmi_write_
Read_process and MPMC modules, col_dep_div modules, comp_dibr modules and lvds modules send enabling signal
start.Because input data is not necessarily since first pixel of a frame, thus will according to field sync signal come
Determine start frame, it usually needs the former two field pictures of removal, the frame number for removing image can be arranged as required to.It is determined that start frame
Afterwards, send a start signal to hdmi_write_read_proces modules and represent that down-stream can start.
2.2hdmi_write_read_process module
After hdmi_write_read_process modules receive the enabling signal start of clr_gen modules, start to replace
Reference image data and corresponding depth image data are received, the input port of depth image data is hdmi_ in the present embodiment
Qb ports, i.e., share a port with the B component in RGB component in reference image data.Storage position according to DDR memory
Width, according to parametric image data and the respective rule of combination of depth image data, control storage enables signal, by reference picture number
Exported respectively to hdmi_col_ram and hdmi_dep_ram modules according to depth image data.Hdmi_ in the present embodiment
The pixel clock hdmi_odck of the video data of write_read_process modules input is 74.25MHz, according to clock
Data are stored in hdmi_col_ram modules and hdmi_dep_ram modules by the DDR operation clocks of clk200 (200MHz).
2.3hdmi_col_ram modules and hdmi_dep_ram modules
Hdmi_col_ram modules and hdmi_dep_ram modules are all the IP kernels for directly generating, for data cached.
The data that 128bit after combination is one group are exported and give MPMC moulds by hdmi_col_ram modules and hdmi_dep_ram modules
Block.The effect of the two modules has two：One is solving the problems, such as data combination, i.e. parametric image data and depth image number
Stored according to after zero padding；The second is solving the problems, such as cross clock domain, the clock for writing data is the picture of hdmi_odck (74.25MHz)
Plain clock, when output be but DDR work clock clk200 (200MHz), ram modules just solve this automatically
The problem of cross clock domain.
3rd, MPMC modules
DDR storage control modules in the present embodiment use MPMC modules, i.e., many mouthfuls random access memory controller module (multi-
port memory controller).MPMC modules mainly realize using DDR memory as the memory mechanism of external cache,
The reference image data and depth image data that subsequent module is needed all are stored into external memory storage, are passed through after then reading
Cross image fractionation module col_dep_div to be split, it (is multi-view in the present embodiment to be then sent to DIBR algoritic modules
As Fusion Module comp_dibr), it is ensured that reference image data and depth image data are sent at subsequent module simultaneously
Reason.The data-bus width of output is 128bit.The output data that MPMC modules read from DDR2 memories in the present embodiment
By a line color reference image data (the i.e. 320 colored diagram datas of 128bit) and a line depth map data (i.e. 80
The depth map data of 128bit) interval composition.
Fig. 6 is the structure chart of MPMC modules in Fig. 4.As shown in fig. 6, MPMC modules include that address produces mould in the present embodiment
Block 21dma_gen, read-write generation module ddr2_mpmc, DDR controller control signal generation module ddr2_cmd and DDR
Controller ddr2_sdram.Table 2 is the input/output port list of MPMC modules.
Table 2
3.1dma_gen module
Dma_gen modules are the important modules in MPMC modules, control frame number, the initial address of read-write picture frame of write-in
Deng important content, the read/write address of whole DDR2SDRAM is managed collectively.Produced in each hdmi_de signal period and write data
The initial address of initial address and reading data.Table 3 is the input/output port list of dma_gen modules.
Table 3
As table 3 understands that dma_gen module output signals have two groups, four altogether, one group of initial address for being to write DDR, one
Group is to read the initial address of DDR.Location includes the initial address for reading or writing of reference image data and depth image respectively to each group,
I.e. reference picture write-in initial address mpmc_wr_col_addr_start, reference picture read initial address mpmc_rd_col_
Addr_start, depth image write-in initial address mpmc_wr_dep_addr_start, depth image read initial address
mpmc_rd_dep_addr_start.That is, will be to ddr2_cmd modules one with reference to figure in each hdmi_de cycle
With the initial value of the read/write address of depth map, the calculating of this initial value is given by following formula：
mpmc_wr_col_addr_start<=wr_col_addr_base+wr_col_addr_temp,
mpmc_rd_col_addr_start<=rd_col_addr_base+rd_col_addr_temp；
mpmc_wr_dep_addr_start<=wr_dep_addr_base+wr_dep_addr_temp,
mpmc_rd_dep_addr_start<=rd_dep_addr_base+rd_dep_addr_temp；
Above formula is calculated by the way of base address adds side-play amount, "<=" represent assignment.Wherein, wr_col_addr_
Base represents the base address of reference picture write-in, and wr_col_addr_temp represents the side-play amount of parametric image writing address；rd_
Col_addr_base represents the base address that reference picture reads, and wr_col_addr_temp represents that reference picture reads address
Side-play amount；Wr_dep_addr_base represents the base address of depth image write-in, and wr_dep_addr_temp represents depth image
The side-play amount of writing address；Rd_dep_addr_base represents the base address that depth image reads, rd_dep_addr_temp tables
Show that depth image reads the side-play amount of address.
Input image resolution in the present embodiment is 1280*720, therefore the number of addresses that a line reference image data needs
For 640 (each address 64bit in DDR2SDRAM, and after input data serioparallel exchange it is 128bit, therefore each two address table
Show a data.Often row has 320 128bit data after combination, therefore needs 640 addresses), so the side-play amount wr_ of reference picture
Col_addr_temp and rd_col_addr_temp often run into a rising edge of hdmi_de just plus 640, and base address wr_
Col_addr_base and rd_col_addr_base are then to run into a rising edge of field sync signal hdmi_vsync just often
Another set address is changed to, depth map is also the same.Simply in the rising edge of each hdmi_de depth image side-play amount
Wr_dep_addr_temp and rd_dep_addr_temp add 160 (because 16 8bit data constitute one in the present embodiment
128bit data, therefore number of addresses needed for depth map a line is 1280/16*2=160).Thus just can by change base address come
It is determined that any piece image of which frame read and write in the time of which frame.
But, it is not that the reference picture or depth image of each frame input are required for writing DDR2SDRAM.Because
In a practical situation, it by frequency multiplication, i.e. video source is identical with reference to two, figure with two width identicals that the video data of input is
The input of depth map interval.In the present embodiment, design be 60Hz frame frequency video source file, wherein with reference to figure and its correspondence
Depth map interval input.But due to code stream instrument, it can only read video source with the frame frequency speed of 30Hz, then
Become the video of 60Hz by way of replicating again.That is, the image after every width real image is the real image
Duplicated frame, real image is effective image, and duplicated frame is invalid image.Assuming that video source file only has four width images, first
Frame is reference picture, and the second frame is the corresponding depth image of the first frame, and it is also reference picture that the 3rd frame is, the 4th frame is the 3rd frame
Corresponding depth image.When code stream instrument reads, this four width image is read with the frame per second of 30Hz, then all entered per piece image
Row is exported after once replicating, and thus exports 8 width images with the frame per second of 60Hz.The order of this eight width figure is that the first frame is with reference to figure
Picture, the first frame reference picture, the second frame depth image, the second frame depth image, the 3rd frame reference picture, the 3rd frame are with reference to figure
Picture, the 4th frame depth image, the 4th frame depth image.
Therefore when view data is write into DDR2SDRAM, it is necessary to whether according to view data be effective image determine
Whether write.Knowable to describing before, effective image and invalid image are the presence of rule sequentially, therefore just can basis
This order come determine whether write current frame image.In the present invention, 4 memory blocks are marked off in DDR memory, wherein 2
Individual for storing reference image data, address space is designated as C1 and C2 respectively, and 2 are used for storage depth view data, ground in addition
Location space is designated as D1 and D2 respectively.
Fig. 7 is DDR read-write sequence figures.As shown in fig. 7, the time of the 1st frame started in program, first writes cromogram FC1,
That thus give is the first paragraph address space C1 for depositing reference picture.The second frame time due to being identical duplicated frame, thus
This frame does not take any write-in or read operation.When three frames, this frame is reference picture FC1 and its corresponding depth
Image FD1 provides the first paragraph address space D1 of depth image and carries out write operation, it is necessary to stored.4th frame
When, in all having existed for DDR2SDRAM due at this time reference picture FC1 and depth image FD1, and the image being input into is
The duplicated frame FD1 of depth image is input into when three frames, so not taking write operation, reference picture in the time of this frame
FC1 and corresponding depth image FD1 then read simultaneously.During five frames, due to reference picture FC1 and depth image FD1 before
It is still in not being refreshed in DDR2SDRAM, this frame in continues the reading of the two images, simultaneously because new reference
Image FC2 has arrived, therefore to carry out write operation to it；The difference is that address space C1 is in occupied state, here
Need to FC1 distribution address spaces C2.During six frames, reference picture FC1 and depth image FD1 proceed read operation, by
In input is duplicated frame, so write operation is not carried out.Read operation is still to read FC1 and FD1 simultaneously during seven frames, this
When that arrive is the second amplitude deepness image FD2, the image will be written among address space D2.During eight frames, due to being to replicate
Frame, the operation not write, and now had FC2 and FD2 respectively in address space C2 and D2, they will be read simultaneously
Go out.
In a subsequent frame, the mode of read-write operation is similar with process above, that is, write operation is followed " with 4 frames
Be the cycle, the first frame carries out reference picture write operation, and the 3rd frame carries out depth image write operation " rule, and read behaviour
Follow the rule of " if being read simultaneously while have FCn and FDn and do not fallen by new Refresh Data in DDR2 ".Press
Such read-write is regular to the 15th frame, it is seen that the read-write state of this frame DDR2 and the state of the 7th frame are identicals, shows
Right 16th frame will repeat the read-write state of the 8th frame, and read-write state below also will be the weight of the 9th frame to the 15th frame
It is multiple.Therefore since the 9th frame, if systems stay works, then the read-write state of DDR2 will be 8 frames with a cycle
Circulation continuous go down.
The 4th frame from foregoing description it can further be seen that after read-write process, each frame is all being read
Go out operation, and each FCn and FDn can continuously be read four frames.The purpose for the arrangement is that in order to allow DDR2 output images
Frame per second can keep the uniformity with system input frame rate.
3.2ddr2_mpmc module
Ddr2_mpmc modules are read-write generation modules, and major function is the reference picture that will write DDR2SDRAM
Data hdmi_rd_col_data [127:0] and depth image data hdmi_rd_dep_data [127:0] merge that (this two
Circuit-switched data is that timesharing is not to arrive so can merge simultaneously), output DDR write-in data mpmc_data_in [127:
0], and provide one group of more succinct signal to ddr2_cmd modules judge read-write DDR time ordered interval and subsequent module sentence
When disconnected DDR output datas arrive.Table 4 is the input/output port list of ddr2_mpmc modules.
Table 4
From Fig. 6 and Biao 4 as can be seen that the output of ddr2_mpmc modules is divided into two parts, Part I is reference picture number
According to write-in useful signal mpmc_wr_col_en, depth image data write-in useful signal mpmc_wr_dep_en, reference picture
Data read control signal mpmc_rd_col_en, depth image data read control signal mpmc_rd_dep_en, DDR write-in data
mpmc_data_in[127:0], this part is used for belonging to another module ddr2_cmd of mpmc submodules together, second
Dividing includes that reference image data reads useful signal ddr_rdcol2process_en, depth image data and reads useful signal
Ddr_rddep2process_en, the two signals be substantially exactly mpmc_rd_col_en, mpmc_rd_dep_en but they
Output is used to Subordinate module.The working method of ddr2_mpmc modules is described in detail below.
Because prime input module employs reference picture and depth image frame is separately sentenced otherwise, therefore input signal
It is divided into two states in different time, one kind is reference picture frame state, a kind of depth image frame state.Reference picture frame state
When the reference image data useful signal hdmi_rd_col_en that is input into and reference image data hdmi_rd_col_data effectively,
And depth map data useful signal hdmi_rd_dep_en and depth map data hdmi_rd_dep_data then continue down for ' 0 '
It is invalid to keep；And be then that opposite situation hdmi_rd_dep_en and hdmi_rd_dep_data have in depth image frame state
Effect, hdmi_rd_col_en and hdmi_rd_col_data then continues to keep invalid down for ' 0 '.Thus ddr2_mpmc modules
Different frame states are gone out according to input-signal judging, providing different DDR read-writes in different frame states enables control signal
And data valid signal.
Useful signal mpmc_wr_col_en and depth image data write-in useful signal are write for reference image data
Mpmc_wr_dep_en, their reference image data useful signal hhdmi_rd_col_en and depth image data with input
Useful signal hhdmi_rd_dep_en is consistent, and it be respectively 1600ns and 400ns that significant level is held time.For reference
View data useful signal hdmi_rd_col_en, because the reference image data being input into is by the 128bit after serioparallel exchange
Data, therefore the duration of data line is 1280 (pixel columns) × (32/128) (conversion proportion) × 5ns (during treatment
The clock cycle)=1600ns, so the duration of hdmi_rd_col_en is 1600ns.Same hdmi_rd_dep_en's continues
Time is, 1280 (pixel columns) × (8/128) (conversion proportion) × 5ns (treatment clock cycle)=400ns.At these three
Between write DDR the control signals mpmc_wr_col_en and mpmc_wr_dep_en of section output be height, the operation of DDR is write in execution.Need
It is noted that the two will not effectively, because reference image data write-in useful signal mpmc_wr_col_en and ginseng simultaneously
Examine view data useful signal hdmi_rd_col_en consistent, only can be effective when reference image frame hdmi_de is low, and depth
Useful signal mpmc_wr_dep_en is consistent with depth image data useful signal hdmi_rd_dep_en for view data write-in, only
Can be effective when depth image frame hdmi_de is low.So the two data valid signals will not effectively simultaneously.
For reference image data read control signal mpmc_rd_col_en and depth image data read control signal mpmc_
Rd_dep_en signals, holding time for reference image data read control signal mpmc_rd_col_en is 1900ns, depth image
Data read control signal mpmc_rd_dep_en is 700ns.It is with reference image data read control signal mpmc_rd_col_en
Some parts in example, 1900ns this periods, have carried out reading DDR operation.Reference image data read control signal in sequential
Mpmc_rd_col_en needs 1900ns, is because while to send read command to really receiving data needs 100ns, significant figure
It is 1600ns, altogether 1700ns according to the duration, but valid data are not continuous, when sometimes occurring that interruption is several
Clock is further continued for providing the situation of data, so suitably relax receive the enable control signal that DDR2SDRAM reads data here, with
Guarantee to receive the data read from DDR2SDRAM completely.Depth image data read control signal mpmc_rd_dep_en
It is also the same.Reference image data read control signal mpmc_rd_col_en and depth image data read control signal mpmc_rd_
Dep_en is to provide effective period of time by the method for counting, and reference image data read control signal mpmc_rd_col_en exists
Before depth image data read control signal mpmc_rd_dep_en.Reference image data reads useful signal ddr_
Rdcol2process_en and depth image data read useful signal ddr_rddep2process_en be respectively with reference to figure
As data read control signal mpmc_rd_col_en and the homologous letters of depth image data read control signal mpmc_rd_dep_en
Number, sequential is the same.
It is comprehensive above it will be appreciated that, reference image data write-in useful signal mpmc_wr_col_en, reference image data read control
Signal mpmc_rd_col_en processed, depth image data write-in useful signal mpmc_wr_dep_en and depth image data read control
Signal mpmc_rd_dep_en processed reads with reference image data useful signal hdmi_rd_col_en, reference image data respectively
Useful signal ddr_rdcol2process_en, depth image data useful signal hdmi_rd_dep_en, depth image data
It is identical sequential to read useful signal ddr_rddep2process_en.And DDR write-in data mpmc_data_in [127:0]
It is reference image data hdmi_rd_col_data [127:0] and depth image data hdmi_rd_dep_data [127:0] exist
Splicing on time shaft.
3.3ddr2_cmd module
Although ddr2_cmd modules do not directly receive external data, the external data that other modules are received will be through
Feeding ddr2_sdram control modules after the module is processed are crossed, therefore therefore the module is extremely important.
Table 5 is the input/output port list of ddr2_cmd modules.
Table 5
The Main Function of ddr2_cmd modules is interacted with ddr2_sdram control modules.Data are stored in or
Read DDR2SDRAM.Ddr2_sdram control modules use MIG controllers in the present embodiment, therefore are first according to xilinx passes
The control sequential being written and read to DDR by MIG is drawn in the technical manual of MIG.Fig. 8 is ddr2_cmd emulation Time-Series analyses
Figure.The sequential of a line reference image data is read in Fig. 8 for write-in.The packet of DDR2SDRAM is write in the present invention containing reference
Picture frame and depth image frame, write-in read-out principle is identical, is introduced in this sequential to reference image data.
Fig. 8 is to be illustrated according to the temporal model for writing a line reading one-row pixels.Write the process of DDR2SDRAM
In, address app_af_addr [30:0] DDR read-write control signals app_af_wren for it is high when carry out Jia 8 operating, app_af_
The every 4 clock high jumps of wren are once；It is continuously high, app_af_addr [30 that app_af_wren is during reading:0]
It is continuously Jia 8.Note, rd_data_valid (is equal to ddr_rd_valid letters after inferior 20 clk200 of ordinary circumstance
Number) signal can be drawn high, but rd_data_valid (ddr_rd_valid) signal is possible to discontinuous, middle occasional interruption is several
Individual clock, so need certain differentiation mechanism, could right-on reception data, this is also that ddr_mpmc modules allow reference
View data read control signal mpmc_rd_col_en signals continue 1900ns, the reason for rather than 1700ns.
Additionally, the reference image data in ddr2_cmd according to input writes useful signal mpmc_wr_col_en, depth
View data writes useful signal mpmc_wr_dep_en, reference image data read control signal mpmc_rd_col_en, depth
View data read control signal mpmc_rd_dep_en judges read-write state and the picture frame for reading or writing, so as to when different
Carve, provide different DDR read/write address, it is ensured that read-write is correct.
3.4ddr2_sdram control module
Ddr2_sdram control modules are MIG controllers in the present embodiment, and directly the DDR2SDRAM with bottom is handed over
Mutually, it is IP kernel that xilinx is ready for, that call herein is the MIG of the versions of MIG 2.1.Table 6 is ddr2_sdram control moulds
The input/output port list of block.
Table 6
4th, col_dep_div modules
Col_dep_div modules are used to split the ddr_rd_data numbers that mpmc modules are exported according to the rule of combination of data
It is believed that number, reference map data therein and depth map data are split, high-order zero padding position is deleted, so that target image is generated
Module (i.e. DIBR modules) is used.
Fig. 9 is the structure chart of col_dep_div modules.As shown in figure 9, col_dep_div modules include three submodules,
It is respectively to read data to split module col_dep_wr_rd, read reference image data cache module col_div_ram, read
Depth image data cache module dep_div_ram.Table 7 is the input/output port list of col_dep_div modules.
Table 7
The main functional modules of col_dep_div modules are col_dep_wr_rd modules, and it is completed to ddr_rd_data
Data split, the write-in of management col_div_ram modules and dep_div_ram modules with read, its concrete operations is：
When ddr_rd_col_en is high, data are stored in col_div_ram modules, when ddr_rd_dep_en is high, data are deposited
Enter dep_div_ram modules.
5th, comp_dibr modules
The function that target image generation module comp_dibr modules are mainly completed is using reference picture and its corresponding depth
Degree image synthesizes the view of new viewpoint, that is, target image by DIBR algorithms, so as to constitute stereo pairs.Obtained by it
Image be the postrun result of series of algorithms., it is necessary to generate 8 groups of images pair of different points of view in the present embodiment, therefore
8 DIBR modules of exampleization in comp_dibr modules, 8 groups of different parameters are respectively adopted carry out example has parallax to obtain 8 groups
Image pair, finally by this 8 groups of images to being input to lvds modules.Table 8 is the input/output port row of comp_dibr modules
Table.
Table 8
The concrete structure of DIBR modules becomes scaling method to determine according to the 3-D view based on DIBR for specifically being used.This
The DIBR modules used in embodiment may refer to that " Chinese patent is a kind of based on hard-wired DIBR systems
.CN103533327A.2014-01-22”。
6th, lvds modules
Lvds modules include multi-view image Fusion Module and upper screen display module.Multi-view image blending algorithm is to be based on
The key issue that the bore hole 3D of grating shows.The function that it is completed is to carry out sub-pixel to several views containing human eye parallax
Extract, then arranged according to grating arrangement of subpixels table, be finally synthesizing and obtain the bore hole stereoscopic display for being suitably based on grating
The composograph that device shows.The multi-view image blending algorithm used in the present embodiment is with reference to a kind of " multi-views of Chinese patent
As fusing device .CN104185011A.2014-12-03 ".
Upper screen display module carries out upper screen and shows to the composograph that multi-view image Fusion Module is exported, specific naked
Eye 3D display screens see the video with bore hole 3D effect.Upper screen display module is the common module of bore hole 3D Play Systems,
Will not be repeated here.
In the present embodiment, using based on Xilinx5FPGA development platforms build real-time Naked of the invention
3D Play Systems.Table 9 is the real-time Naked resource occupation statistical form of 3D Play Systems in this implementation.
Table 9
Real-time Naked 3D Play System of the invention takes not to the hardware resource under the platform as can be seen from Table 9
Height, is a kind of relatively inexpensive hardware implementation mode, and the system can be run on the hardware platform completely, is realized to bore hole 3D
The real-time broadcasting of video.
Although being described to illustrative specific embodiment of the invention above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the invention is not restricted to the scope of specific embodiment, to the common skill of the art
For art personnel, as long as various change is in appended claim restriction and the spirit and scope of the present invention for determining, these
Change is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (4)
1. a kind of real-time Naked 3D Play System based on FPGA, it is characterised in that including video input module, DDR storage controls
Molding block, DDR memory, data split module, target image generation module, multi-view image Fusion Module and upper screen display mould
Block, wherein：
Video input module alternately receive reference image data and corresponding depth image, write every time according to DDR memory or
The data package size for reading data is combined to reference image data and depth image data respectively, and the data after combination are handed over
For being sent to DDR storage control modules；Combination is expressed as with formula：
a1(3x+b1)=z
a2(y+b2)=z
Wherein, x represents the digit of each component data in three RGB components of each pixel in reference image data, and y represents deep
The digit of each pixel data in degree view data, z represents DDR memory write-in or the data package size for reading every time；a1Table
Show the number of combinations of color component data, a1It is positive integer, b1The number of high-order zero padding position when representing that reference image data is combined,
b1It is nonnegative integer；a2Represent the number of combinations of depth data, a2It is positive integer, b2It is high-order when representing that depth image data is combined
The number of zero padding position, b2It is nonnegative integer；
DDR storage control modules receive the reference image data and depth image data of video input module output, store to DDR
Memory, then splits module according to a line reference image data, a line depth image data interval output to data；
Data split rule of combination docking of the module according to reference image data and depth image data in video input module
The reference image data and depth image data for receiving are split, and delete high-order zero padding position, the data hair that will be obtained after fractionation
Give target image generation module；
Target image generation module leads to the reference picture of reception and its corresponding depth image according to default N number of viewpoint parameter
Cross DIBR algorithms and synthesize N number of target image, reference picture and each target image are respectively constituted into stereo pairs, will be N number of vertical
Body image is to being sent to multi-view image Fusion Module；
N number of stereo pairs are carried out sub-pixel extraction by multi-view image Fusion Module, and fusion obtains the conjunction of N number of stereo pairs
Into image, screen display module is sent to；
Upper screen display module carries out upper screen and shows to composograph.
2. real-time Naked 3D Play System according to claim 1, it is characterised in that in the video input module, it is deep
One of them spent in the input port of view data and three RGB component input ports of reference image data shares a thing
Reason port.
3. real-time Naked 3D Play System according to claim 1, it is characterised in that the video input module includes opening
Dynamic control module, video read-write management module, reference picture cache module, depth image cache module, wherein：
Start control module, monitor the initialization completion signal of DDR memory, when initialization completion signal is effective, according to
Field sync signal determines start frame, then sends enabling signal to video read-write management module；
Video reads and writes management module, receives the enabling signal for starting control module, alternately receives reference image data and corresponding
Depth image, writes or reads the data package size of data every time according to DDR memory, according to respective rule of combination, control
Storage enables signal, and reference image data and depth image data are exported to reference picture cache module and depth image respectively
Cache module；
Reference picture cache module, the reference image data after caching combination, exports and gives DDR storage control modules；
Depth image cache module, the depth image data after caching combination, exports and gives DDR storage control modules；
Reference picture cache module and depth image cache module are alternately output in output data.
4. real-time Naked 3D Play System according to claim 1, it is characterised in that the DDR storage control modules bag
Include address generating module, read-write generation module, DDR controller control signal generation module and DDR controller, specific works
Flow is as follows：
When the first two field picture, i.e. the first frame reference image data is received, address generating module is according to advance in DDR memory
The first paragraph address space of the reference image data for marking is exported line by line writes initial address to DDR controller control signal generation mould
Block；Read-write generation module receives the first frame reference image data and controls to believe as write-in data output to DDR controller
Number generation module, while exporting write control signal to DDR controller control signal generation module；DDR controller control signal is produced
Raw module receives the initial address of writing of reference image data first paragraph address space, produces corresponding write address, together with receiving
Write control signal and the first frame reference image data be sent to DDR controller；Control of the DDR controller in write control signal
Under, the first frame reference image data is stored in DDR memory according to write address；
When the second two field picture, the i.e. multiimage of the first frame reference picture is received, do not write or read operation；
When the corresponding depth image of the 3rd two field picture, i.e. the first frame reference picture is received, address generating module is deposited according to DDR
The first paragraph address space of the depth image data marked in advance in reservoir is exported line by line writes initial address to DDR controller control
Signal generator module；Read-write generation module receives the first frame depth image data and is controlled as write-in data output to DDR
Device control signal generation module processed, while exporting write control signal to DDR controller control signal generation module；DDR controller
Control signal generation module receives the initial address of writing of depth image data first paragraph address space, produces corresponding write address,
DDR controller is sent to together with the write control signal for receiving and the first frame depth image data；DDR controller is writing control letter
Number control under, the first frame reference image data is stored in DDR memory according to write address；
When the 4th two field picture, the i.e. multiimage of the first frame depth image is received, address generating module is according to DDR memory
The first paragraph address space of middle reference image data and the first paragraph address space of depth image data are by row alternately output reference
The reading initial address of view data and depth image data is to DDR controller control signal generation module；Read-write produces mould
Block produces reference image data and the read control signal of depth image data to export to DDR controller control signal generation module；
The first paragraph address space of DDR controller control signal generation module reception reference image data and the first of depth image data
The reading initial address in sector address space, produces corresponding reading address, and DDR controls are sent to together with the read control signal for receiving
Device；DDR controller under the control of read control signal, according to reading address by the first frame reference image data and the first frame depth map
As data read out from DDR memory, export and split module to data；The reading process will be continued until that the first frame is joined
Examine view data and the first frame depth image data all reads and finishes；
When the 5th two field picture, i.e. the second frame reference picture is received, address generating module according to marking in advance in DDR memory
The second segment address space of reference image data export write initial address to DDR controller control signal generation module line by line；
Read-write generation module receives the second frame reference image data and is produced as write-in data output to DDR controller control signal
Raw module, while exporting write control signal to DDR controller control signal generation module；DDR controller control signal produces mould
Block receives the initial address of writing of reference image data second segment address space, corresponding write address is produced, together with writing for receiving
Control signal and the second frame reference image data are sent to DDR controller；DDR controller under the control of write control signal, root
The first frame reference image data is stored in DDR memory according to write address；
When the 6th two field picture, the i.e. multiimage of the second frame reference picture is received, do not write or read operation；
When the corresponding depth image of the 7th two field picture, i.e. the second frame reference picture is received, address generating module is deposited according to DDR
The second segment address space of the depth image data marked in advance in reservoir is exported line by line writes initial address to DDR controller control
Signal generator module；Read-write generation module receives the second frame depth image data and is controlled as write-in data output to DDR
Device control signal generation module processed, while exporting write control signal to DDR controller control signal generation module；DDR controller
Control signal generation module receives the initial address of writing of depth image data second segment address space, produces corresponding write address,
DDR controller is sent to together with the write control signal for receiving and the second frame depth image data；DDR controller is writing control letter
Number control under, the second frame reference image data is stored in DDR memory according to write address；
When the 8th two field picture, the i.e. multiimage of the second frame depth image is received, address generating module is according to DDR memory
The second segment address space of middle reference image data and the second segment address space of depth image data are by row alternately output reference
The reading initial address of view data and depth image data is to DDR controller control signal generation module；Read-write produces mould
Block produces reference image data and the read control signal of depth image data to export to DDR controller control signal generation module；
The second segment address space of DDR controller control signal generation module reception reference image data and the second of depth image data
The reading initial address in sector address space, produces corresponding reading address, and DDR controls are sent to together with the read control signal for receiving
Device；DDR controller under the control of read control signal, according to reading address by the second frame reference image data and the second frame depth map
As data read out from DDR memory, export and split module to data；The reading process will be continued until that the second frame is joined
Examine view data and the second frame depth image data all reads and finishes；
Follow-up each picture frame is circulated according to the first frame to the processing mode of the 8th frame, until image end of input.
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| CN105631888B (en) * | 2016-01-22 | 2019-12-13 | 上海厚安信息技术有限公司 | image data background removing processing system and method |
| CN108228492B (en) * | 2016-12-21 | 2020-11-17 | 深圳市中兴微电子技术有限公司 | Multi-channel DDR interleaving control method and device |
| CN107071301B (en) * | 2017-04-17 | 2019-11-22 | 宁波视睿迪光电有限公司 | A kind of storage method and read method of more mesh imaging sequences |
| CN107341004A (en) * | 2017-06-16 | 2017-11-10 | 深圳康得新智能显示科技有限公司 | Display methods and device, the terminal of starting-up interface |
| CN108933934A (en) * | 2018-08-07 | 2018-12-04 | 深圳市智之祺科技有限公司 | A kind of design method of naked eye 3D TV |
| CN111669571B (en) * | 2019-03-07 | 2023-12-19 | 阿里巴巴集团控股有限公司 | Multi-angle free view image data generation method and device, medium and equipment |
| WO2020181088A1 (en) | 2019-03-07 | 2020-09-10 | Alibaba Group Holding Limited | Method, apparatus, medium, and device for generating multi-angle free-respective image data |
| CN111508447A (en) * | 2020-04-27 | 2020-08-07 | 上海济丽信息技术有限公司 | Image time sequence control circuit of grating type naked eye 3D liquid crystal screen based on FPGA |
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| CN104202590B (en) * | 2014-06-19 | 2016-09-28 | 杭州立体世界科技有限公司 | High definition bore hole Portable stereoscopic video player control circuit and conversion method |
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