CN105023912B - Semiconductor wafer and its method of testing - Google Patents
Semiconductor wafer and its method of testing Download PDFInfo
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- CN105023912B CN105023912B CN201410172035.3A CN201410172035A CN105023912B CN 105023912 B CN105023912 B CN 105023912B CN 201410172035 A CN201410172035 A CN 201410172035A CN 105023912 B CN105023912 B CN 105023912B
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Abstract
The present invention provides a kind of semiconductor wafer and its method of testing, wherein, semiconductor wafer has a grained region and a cutting zone, and including crystal grain and test circuit.Crystal grain is formed in the grained region in semiconductor wafer, and crystal grain includes main circuit.Test circuit is arranged on the cutting zone of semiconductor wafer, and is electrically connected to crystal grain to test main circuit.
Description
Technical field
The present invention is mainly a kind of semiconductor wafer, particularly has partly leading for the brilliant Off-chip test circuit for testing crystal grain
Body chip.
Background technology
At present, in the technique of conventional semiconductor wafer, the integrated circuit being formed in crystal grain (or chip) needs to survey
Try its feature, process integrity, equipment energy characteristic and reliability etc..Fig. 1 shows the top view of a conventional semiconductor wafer 10,
Its semiconductor wafer 10 includes the grained region 14 that multiple crystal grain 12 are formed on semiconductor wafer 10, and on semiconductor wafer 10
Other regions be then defined as cutting zone 16.In addition, in traditional semiconductor wafer 10, electricity is integrated in crystal grain to test
The test circuit 18 on road is also formed in the crystal grain in grained region 14.It can increase however, test circuit 18 is inserted into crystal grain
Add the size of crystal grain, in other words, the scope that grained region is provided to main integrated circuit relative reduces.This
Outside, it is contemplated that the problem of the size of crystal grain, the test function of test circuit needs to be reduced.
Furthermore the test circuit 18 for conventional semiconductor wafer 10 can be used as test interface (e.g., conductive welding pad, conduction
Projection) to be supplied to external test facility, therefore external test facility can obtain information or the test result of test to judge
Whether the crystal grain tested is normal.However, attempt illegal steal information user may using this test interface come from
Integrated circuit steal information in crystal grain, it is quite dangerous.Therefore, it is necessary to a kind of improved test circuit and method.
The content of the invention
For above mentioned problem, the present invention provides a kind of semiconductor wafer, has a grained region and a cutting zone, and
Above-mentioned semiconductor wafer includes a crystal grain and a test circuit.Above-mentioned crystal grain is formed at the above-mentioned crystal grain of above-mentioned semiconductor wafer
Region, and there is a main circuit.Above-mentioned test circuit is arranged at the above-mentioned cutting zone of above-mentioned semiconductor wafer, and is electrically connected to
Above-mentioned crystal grain is to test above-mentioned main circuit.In some embodiments of the invention, above-mentioned test circuit can be divided into two parts, wherein
The test circuit of a part is arranged in above-mentioned cutting zone, and the test circuit of another part is then arranged at above-mentioned grained region
In.
In certain embodiments, semiconductor wafer further includes a seal ring and a trap (well).Above-mentioned seal ring is arranged at
Crystal grain periphery is stated, and above-mentioned trap is formed under above-mentioned seal ring.Above-mentioned test circuit is electrically connected to above-mentioned crystal grain by above-mentioned trap.
In certain embodiments, when testing above-mentioned main circuit, above-mentioned test circuit more transmits a test data to above-mentioned
Main circuit.A response data is transmitted when above-mentioned main circuit receives above-mentioned test data to above-mentioned test circuit, it is then, above-mentioned
Test circuit judges whether above-mentioned response data is same as above-mentioned test data and connects reliability to detect it.
In some embodiments of the invention, above-mentioned crystal grain further includes a decoding circuit and is connected to above-mentioned main circuit and above-mentioned
Between test circuit.Above-mentioned test data is more encoded and is sent to the above-mentioned test data after coding by above-mentioned test circuit
Decoding circuit is stated, above-mentioned decoding circuit decodes the above-mentioned test data after above-mentioned coding.Above-mentioned main circuit is according to above-mentioned decoding
The above-mentioned test data of circuit transmits above-mentioned response data.
In some embodiments of the invention, above-mentioned crystal grain has more a nonvolatile memory fuse to store in decision
State the numerical value of a function of main circuit.Above-mentioned test circuit provides a high voltage to above-mentioned nonvolatile memory fuse to perform
One brush division operation or a write operation.
The present invention more provides a kind of method of testing, suitable for the semiconductor with a grained region and a cutting zone
Chip.Above-mentioned method of testing includes：A crystal grain is formed in the above-mentioned grained region of above-mentioned semiconductor wafer, wherein above-mentioned crystal grain
Including a main circuit；A test circuit is formed in the above-mentioned cutting zone of above-mentioned semiconductor wafer；And the above-mentioned test of electrical connection
Circuit is to above-mentioned crystal grain to test above-mentioned main circuit.
In some embodiments of the invention, above-mentioned method of testing further includes：A seal ring is formed in above-mentioned crystal grain periphery；And
Form the above-mentioned main circuit that above-mentioned test circuit is electrically connected to above-mentioned crystal grain by a trap.In addition, above-mentioned trap is formed at above-mentioned seal ring
Lower section.
In some embodiments of the invention, above-mentioned method of testing further includes：Utilize the test number of above-mentioned test circuit transmission one
According to extremely above-mentioned main circuit；A response data from above-mentioned main circuit is received by above-mentioned test circuit；And judge above-mentioned time
Answer whether data are same as above-mentioned test data.In addition, the above-mentioned main circuit of above-mentioned crystal grain produces according to above-mentioned test data
State response data.
In some embodiments of the invention, above-mentioned crystal grain further includes a decoding circuit and is connected to above-mentioned main circuit and above-mentioned
Between test circuit.In this embodiment, above-mentioned method of testing further includes：Above-mentioned test data is encoded；After transmission coding
Above-mentioned test data is to above-mentioned decoding circuit；And by above-mentioned decoding circuit by the above-mentioned test data solution after above-mentioned coding
Code.In addition, above-mentioned main circuit transmits above-mentioned response data according to the above-mentioned test data of above-mentioned decoding circuit.
In some embodiments of the invention, above-mentioned crystal grain has more a nonvolatile memory fuse to store in decision
State the numerical value of a function of main circuit.In this embodiment, above-mentioned method of testing further includes：One is provided using above-mentioned test circuit
High voltage is to above-mentioned nonvolatile memory fuse to perform one brush division operation or a write operation.
By the semiconductor wafer and its method of testing of the present invention, the information security of main circuit in crystal grain is improved, is made
The user for attempting illegal steal information can not access the information in crystal grain using test circuit.
Brief description of the drawings
From read it is described further below and with institute's accompanying drawings citing, can more completely understand that disclosed herein such as
Under：
Fig. 1 shows the top view of the conventional semiconductor wafer 10 including multiple crystal grain and test circuit.
Fig. 2 be according to one embodiment of the invention include multiple crystal grain and test circuit semiconductor wafer on regard
Figure.
Fig. 3 shows the schematic diagram of the crystal grain and a test circuit according to one embodiment of the invention.
Fig. 4 A are according to the crystal grain of one embodiment of the invention and the schematic diagram of test circuit.
Fig. 4 B show the fragmentary cross-sectional view of the semiconductor wafer according to one embodiment of the invention.
Drawing reference numeral explanation：
10th, 100~semiconductor wafer
12nd, 120~crystal grain
14th, 140~grained region
16th, 160~cutting zone
18th, 180~test circuit
122~main circuit
124~decoding circuit
126~seal ring
DNW~deep N-well
Ls~line of cut
NW1, NW2~N-type well
N+~N+ diffusion regions
PSUB~p-type substrate
Embodiment
Institute's accompanying drawings are coordinated to illustrate embodiments of the invention below.It will be understood that description of the invention offer is different
Embodiment illustrates the technical characteristic of different embodiments of the present invention.Wherein, each element in embodiment is configured to simplify
It is bright to be used, and it is not used to the limitation present invention.In addition, the parameter in embodiment may be reused, it is repeated to simplify
Relevance that is bright, being not meant as between different embodiments.
Fig. 2 be according to one embodiment of the invention include multiple crystal grain and test circuit semiconductor wafer on regard
Figure.In this embodiment, semiconductor wafer 100 includes multiple crystal grain 120 and multiple test circuits 180.Crystal grain 120 is distributed in
In each grained region 140 on semiconductor wafer 100, and test circuit 180 is distributed in cutting zone 160.In addition, test electricity
Road 180 is individually arranged at the corresponding side of crystal grain 120, and test circuit 180 is electrically connected to corresponding crystal grain 120 to test crystal grain
120 main circuits therein.
In one embodiment, when testing the main circuit in crystal grain 120, test circuit 180 can pass through the road of its electrical connection
Main circuit is tested in footpath.For example, test circuit 180 can be led to by the connecting path and the main circuit in crystal grain 120
News, test circuit 180 and responding to judge the test result of crystal grain 120 according to main circuit.It will be understood that test circuit 180
Different command, data, external bias signal can be provided and/or are that its combination (is all referred to as " surveys below according to the purpose of test
Trial signal ") to the main circuit of crystal grain 120.In addition, the main circuit in crystal grain 120 can have a dedicated bus to make as test
With this dedicated bus receives the above-mentioned test signal for carrying out self testing circuit 180.In addition, the main circuit of crystal grain 120 can have typically
Data/address bus, after the synchronization between the main circuit of crystal grain 120 and test circuit 180 is established, this general data bus also may be used
The above-mentioned test signal for carrying out self testing circuit 180 is received as test use.In semiconductor wafer process, surveyed in crystal grain 120
After examination, those crystal grain 120 independent element can be divided into by removing cutting zone 160.Due to being formed at cutting area
The test circuit 180 in domain 160 is removed in the lump in this program, therefore the user for attempting illegal steal information can not then use
Test circuit 180 accesses the information in crystal grain 120.The test of crystal grain will be further illustrated in the following paragraphs.
In an embodiment of the present invention, test circuit 180 can transmit test data to the main circuit of crystal grain 120 come the company of test
Connect reliability.When the main circuit of crystal grain 120 receives test data, main circuit can transmit response data to test circuit 180.
Finally, test circuit 180 judges whether connection is normal according to the response data of the main circuit of crystal grain 120.For example, inspection is worked as
When surveying connection reliability, test circuit 180 can determine whether response data is same as test data.When response data and test data
When identical, test circuit 180 then can determine whether that this is connected as normally.When response data and test data differ, test circuit
180 can determine whether that this is connected as mistake.In certain embodiments, avoid attempting illegal steal information for safety reasons
User enters test pattern, carrys out the data of self testing circuit 180 and can be encoded, and the main circuit in crystal grain 120 will can be connect
The data of receipts decode and judge whether the data come from source trusty.In addition, received when the main circuit in crystal grain 120
It is synchronous by establishing when data come from source trusty.
It will be understood that there can be outside test equipment in certain embodiments.In this embodiment, test circuit 180
Test equipment of one output end to outside can be provided, and outside test equipment can then collect test information from test circuit 180.
In certain embodiments, test circuit can provide test equipment of the input to outside, and outside test equipment is then controllable
Test circuit 180 processed is tested.
In order to lift the information security of main circuit in crystal grain, the present invention more provides a solution code system.Fig. 3 is shown according to this
Invent the schematic diagram of the crystal grain and a test circuit described in an embodiment.In an embodiment of the present invention, crystal grain 120 includes
Main circuit 122 and decoding circuit 124.Decoding circuit 124 is connected between main circuit 122 and test circuit 180.In order to test
Main circuit 122, test circuit 180 is by test data/instruction encoding and transmits test data/instruction after encoding to decoding circuit
124.Then, test data/instruction decoding that decoding circuit 124 will be encoded, and provide decoded test data/instruction extremely
Main circuit 122.When main circuit 122 receives decoded test data/instruction, then response data is transmitted to test circuit
180.Finally, test circuit 180 can determine the result of test according to the response data of main circuit 122.It will be understood that in the present invention
In some embodiments, decoding circuit 124 can be also included in main circuit 122.Due to main circuit 122 and test circuit 180 it
Between communication by decoding circuit 124 and have encoding and decoding mechanism, the user for attempting illegal steal information can not be light
Correct data/commands easily in access main circuit, so that enhancing the security of main circuit.
In some embodiments of the invention, crystal grain may include nonvolatile memory fuse.This nonvolatile memory melts
Silk is used for storing the numerical value for determining main circuit function in crystal grain 120, and those numerical value in nonvolatile memory fuse are
It is set during test.Therefore, in order to ensure nonvolatile memory fuse is tampered after crystal grain cutting process, this is non-easily
The operation of erasing of the property lost memory fuse is only provided by test circuit 180.For example, test circuit 180 can provide a high electricity
Nonvolatile memory fuse is depressed into perform operation of erasing.Due between nonvolatile memory fuse and test circuit 180
Communication channel be removed after crystal grain cutting process, therefore the content of nonvolatile memory fuse can be protected.
, can shape in order to avoid causing the stress and pollution that crystal grain 120 cut by crystal grain in some embodiments of the invention
Into seal ring around crystal grain 120, as shown in Fig. 4 A, Fig. 4 B.Fig. 4 A are the crystal grain and survey according to one embodiment of the invention
Try the schematic diagram of circuit.In this embodiment, seal ring 126 can be formed by metal level, oxide layer, diffusion layer or its combination.By
The periphery of crystal grain 120 is arranged in seal ring 126, if such as Fig. 2 of test circuit 180 is arranged at outside grained region 160 cutting zone
160, test circuit 180 will be difficult to the main circuit that is electrically connected to crystal grain 120.It should be noted that though metal level or diffusion layer can be made
It is ditch circulation passage or the access path between the main circuit 122 of crystal grain 120 and test circuit 180, but only terminates in seal ring 126
When destroying to form opening.However, the opening of seal ring 126 is likely to result in the pollution of crystal grain 120, and opening is easily attempted not
Observed by the user of method steal information, so that increasing the risk that its information is stolen.
In order to solve the above problems, one embodiment of the invention provides main circuit and test circuit of the well as crystal grain 120
Communication channel between 180.For example, Fig. 4 B show the cut-away section of the semiconductor wafer according to Fig. 4 A embodiment
Figure.Due to main circuit 122 from test circuit 180 as its effect or the different of function may have different structures, in order to
Simplify explanation, only main circuit 122 and test circuit 180 are represented using square in Fig. 4 B.As shown in Figure 4 B, semiconductor wafer
Including p-type substrate P SUB, deep N-well DNW, N-type well NW1, N type well NW2 and the N+ diffusions being formed in N-type well NW1, NW2
Area N+.The main circuit of crystal grain 120 is connected to N-type well NW1 N+ diffusion regions N+, and test circuit 180 is connected to NW2 N+ diffusions
Area N+.Because deep N-well DNW is connected between N-type well NW1, NW2, thus can realize between crystal grain 120 and test circuit 180
Communication channel.In this embodiment, test circuit 180 can transmit number via N-type well NW2, deep N types well DNW and N-type well NW1
According to or instruction to crystal grain 120 main circuit.In addition, when the main circuit of crystal grain 120 receive data or instruction can be via N-type well
NW1, deep N-well DNW and N-type well NW2 are responded to test circuit 180.Due to deep N-well DNW compare seal ring 126 be formed at it is relatively low
Layer, therefore opening can need not be formed in seal ring 126, and can establish between the main circuit of crystal grain 120 and test circuit 180
Communication channel.It will be understood that between main circuit 122 and test circuit 180 connection can by the random layer of crystal grain 120 come
Complete, such as metal level (schema is not shown).Due to metal level more upper strata and compare trap can be obvious, in order to increase safety
Property, under preferred embodiment, trap NW1, DNW, NW2 are connected through to realize between main circuit 122 and test circuit 180.
In addition, after the test of crystal grain 120 terminates, semiconductor wafer cuts out crystal grain along dotted line Ls in cutting process
120, and test circuit 180 will be removed.Deep N-well is connected through between the main circuit and test circuit 180 of crystal grain 120
DNW (Deep N Well) is formed, and deep N-well DNW has been broken after cutting process.Therefore, the main circuit of crystal grain 120 with
Between test circuit 180 be connected to cutting process after be not easy to be found.
Although the present invention and its advantage have been specified in, it should be appreciated that to being defined in the patent enclosed not departing from the present invention
In the spirit and scope of scope, a variety of changes, alternatives and modifications can be done.Also, the scope of this application is not used to limit explanation
Flow, machine, manufacture, the structure of matter, instrument, the method and steps of the specific embodiment of middle narration.Therefore, the patent model enclosed
Enclose to include the category of flow, machine, manufacture, the structure of matter, instrument, method or step.In addition, each claim is formed
The combination of different embodiments and different claims and embodiment, within the scope of the present invention.
Claims (6)
- A kind of 1. semiconductor wafer, it is characterised in that there is a grained region and a cutting zone, including：One crystal grain, the grained region of the semiconductor wafer is formed at, and there is a main circuit；AndOne test circuit, is arranged at the cutting zone of the semiconductor wafer, and is electrically connected to the crystal grain to test State main circuit；Wherein, the test circuit more transmits a test data to the main circuit, when the main circuit receives the test A response data to the test circuit, and the test circuit is transmitted during data and judges whether the response data is same as The test data；Wherein, the crystal grain further includes a decoding circuit and is connected between the main circuit and the test circuit, the survey The test data is more encoded and the test data after coding is sent into the decoding circuit, the decoding by examination circuit Circuit decodes the test data after the coding, and the main circuit is according to the test data of the decoding circuit Transmit the response data；Wherein, it is correct in main circuit make it that the user for attempting illegal steal information can not access easily for the decoding circuit Data/commands, so that enhancing the security of main circuit.
- 2. semiconductor wafer as claimed in claim 1, it is characterised in that further include：One seal ring, it is arranged at the crystal grain periphery；AndOne trap, it is formed under the seal ring；Wherein described test circuit is electrically connected to the crystal grain by the trap.
- 3. semiconductor wafer as claimed in claim 1, it is characterised in that the crystal grain melts with more a nonvolatile memory Silk is to store the numerical value for the function of determining the main circuit, and the test circuit one high voltage of offer is to described non-volatile Property memory fuse is to perform one brush division operation or a write operation.
- 4. a kind of method of testing, it is characterised in that suitable for brilliant with the semiconductor of a grained region and a cutting zone Piece, including：A crystal grain is formed in the grained region of the semiconductor wafer, wherein the crystal grain includes a main circuit；A test circuit is formed in the cutting zone of the semiconductor wafer；AndThe test circuit is electrically connected to the crystal grain to test the main circuit；A test data is transmitted to the main circuit using the test circuit；A response data from the main circuit is received by the test circuit；AndJudge whether the response data is same as the test data；Wherein, the main circuit of the crystal grain produces the response data according to the test data；Wherein, the crystal grain further includes a decoding circuit and is connected between the main circuit and the test circuit, and described Method of testing further includes：The test data is encoded；The test data after coding is transmitted to the decoding circuit；AndThe test data after the coding is decoded by the decoding circuit；Wherein, the main circuit transmits the response data according to the test data of the decoding circuit；Wherein, it is correct in main circuit make it that the user for attempting illegal steal information can not access easily for the decoding circuit Data/commands, so that enhancing the security of main circuit.
- 5. method of testing as claimed in claim 4, it is characterised in that further include：A seal ring is formed in crystal grain periphery；AndForm the main circuit that the test circuit is electrically connected to the crystal grain by a trap；Wherein described trap is formed at the lower section of the seal ring.
- 6. method of testing as claimed in claim 4, it is characterised in that the crystal grain has more a nonvolatile memory fuse To store the numerical value for the function of determining the main circuit, and the method for testing further includes：Carried using the test circuit For a high voltage to the nonvolatile memory fuse to perform one brush division operation or a write operation.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410172035.3A CN105023912B (en) | 2014-04-25 | 2014-04-25 | Semiconductor wafer and its method of testing |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410172035.3A CN105023912B (en) | 2014-04-25 | 2014-04-25 | Semiconductor wafer and its method of testing |
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| CN105023912A CN105023912A (en) | 2015-11-04 |
| CN105023912B true CN105023912B (en) | 2017-12-26 |
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| CN201410172035.3A Active CN105023912B (en) | 2014-04-25 | 2014-04-25 | Semiconductor wafer and its method of testing |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106981476B (en) * | 2017-03-30 | 2019-03-05 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and forming method thereof |
| WO2020043169A1 (en) * | 2018-08-31 | 2020-03-05 | Changxin Memory Technologies, Inc. | Wafer structure, die fabrication method and chip |
| CN113410209B (en) * | 2021-06-09 | 2023-07-18 | 合肥中感微电子有限公司 | Trimming circuit |
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| TW201030827A (en) * | 2009-02-06 | 2010-08-16 | United Microelectronics Corp | Die seal ring |
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| CN103311228A (en) * | 2012-03-15 | 2013-09-18 | 英飞凌科技股份有限公司 | Die, wafer and method of processing a wafer |
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| JP2001318128A (en) * | 2000-05-08 | 2001-11-16 | Nec Microsystems Ltd | Semiconductor device having self-test function and its testing method |
| US9048201B2 (en) * | 2011-06-23 | 2015-06-02 | Broadcom Corporation | Sacrificial wafer probe pads through seal ring for electrical connection to circuit inside an integrated circuit |
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| CN1177188A (en) * | 1996-09-05 | 1998-03-25 | 冲电气工业株式会社 | Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and head circuit for semiconductor memory circuit |
| CN1879006A (en) * | 2004-10-07 | 2006-12-13 | 雅马哈株式会社 | Geomagnetic sensor and geomagnetic sensor correction method, temperature sensor and temperature sensor correction method, geomagnetism detection device |
| TW201030827A (en) * | 2009-02-06 | 2010-08-16 | United Microelectronics Corp | Die seal ring |
| CN102737705A (en) * | 2011-03-30 | 2012-10-17 | 索尼公司 | Storage media device and recording apparatus |
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