CN105005450B - Method for writing data, memory storage apparatus and memorizer control circuit unit - Google Patents

Method for writing data, memory storage apparatus and memorizer control circuit unit Download PDF

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Publication number
CN105005450B
CN105005450B CN201410173227.6A CN201410173227A CN105005450B CN 105005450 B CN105005450 B CN 105005450B CN 201410173227 A CN201410173227 A CN 201410173227A CN 105005450 B CN105005450 B CN 105005450B
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data
instance
erased cell
cell
check
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CN105005450A (en
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梁鸣仁
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

A kind of method for writing data of present invention offer, memory storage apparatus and memorizer control circuit unit.The method includes：Write instruction is received, wherein this write instruction instruction writes data into a logical address, and this logical address belongs to a logical program unit；When entity erased cell belonging to this logical program unit mapped entity program unit is first kind entity erased cell, according to the first code check by this data and the check code programming corresponding to this data so far entity program unit；And when this entity erased cell is the second class entity erased cell, this data and the check code corresponding to this data are programmed into so far entity program unit according to the second code check, wherein the first code check is higher than the second code check.Thereby, the service life of the higher entity erased cell of bit error rate can be extended.

Description

Method for writing data, memory storage apparatus and memorizer control circuit unit
Technical field
The invention relates to a kind of data writing mechanisms, and non-volatile for duplicative in particular to one kind Method for writing data, memory storage apparatus and the memorizer control circuit unit of memory module.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small, and without characteristics such as mechanical structures, so loaded on above-mentioned illustrated various in being very suitable for In portable multimedia device.
In general, the service life of each physical blocks in reproducible nonvolatile memorizer module is and reality The number of erasing of body block is related.A physical blocks be repeated erase after, store the data in this physical blocks Error bit can gradually increase.When the error bit number of data is more than the quantity that can correctly be corrected (for example, entity area The number of erasing of block is more than one to erase the number upper limit) when, this physical blocks, which is often rejected, not to be had to.
Invention content
A kind of method for writing data of present invention offer, memory storage apparatus and memorizer control circuit unit, can be in reality When the bit error rate of body erased cell increases, it is changed to erase list using this entity come lasting in such a way that reliability is higher Member, rather than directly given up and do not had to.
A kind of method for writing data of present invention offer can be made carbon copies for controlling reproducible nonvolatile memorizer module Formula non-volatile memory module includes multiple entity erased cells, and each entity erased cell includes multiple entity programs Change unit, and the method for writing data includes：Write instruction is received, one data are written at most for wherein write instruction instruction At least one of a logic unit, wherein at least one of the logic unit maps to the entity program list First instance programmed cell in member, and first instance programmed cell belongs to the first reality in the entity erased cell Body erased cell；Judge that first instance erased cell belongs to first kind entity erased cell or the second class entity erased cell, First bit error rate of middle first kind entity erased cell is less than the second bit error rate of the second class entity erased cell；When When first instance erased cell belongs to first kind entity erased cell, according to the first code check (code rate) by data with it is right It should be programmed to first instance programmed cell in a check code of data；And when first instance erased cell belongs to the second class reality When body erased cell, data and the check code corresponding to data are programmed to first instance sequencing list according to the second code check Member, wherein the first code check is higher than the second code check.
In one example of the present invention embodiment, the judgement first instance erased cell belongs to first kind entity and erases list Member or the step of the second class entity erased cell include：Judge whether the bit error rate assessed value of first instance erased cell accords with Close Sharp criteria；If the bit error rate assessed value of first instance erased cell does not meet Sharp criteria, judgement first instance is smeared Except unit belongs to first kind entity erased cell；And if the bit error rate assessed value of first instance erased cell meets threshold Condition, judgement first instance erased cell belong to the second class entity erased cell.
In one example of the present invention embodiment, the method for writing data further includes：According to first instance erased cell Number information of erasing, write-in number information, reading times information, error bit number information, wrong bitrate information, data deposit At least one or at least combination for putting temporal information and temperature information, to determine the ratio of first instance erased cell Special error rate assessed value.
In one example of the present invention embodiment, the first code check of the foundation is by data and corresponding to the check code of data It is written to the step of first instance programmed cell and includes：Data are divided at least one first data segment and generate at least 1 the One check code section, wherein each first check code section corresponds to one of described first data segment.The foundation Data are written with the check code corresponding to data to the step of first instance programmed cell two code checks：By data point At at least one second data segment and at least one second check code section is generated, wherein each second check code section corresponds to institute State one of second data segment.One data length of wherein each first data segment is identical to each second number It is shorter than each second check code section according to a data length of a data length of section, and each first check code section A data length.
It is described wherein according to the first code check by data and corresponding to the school of data in one example of the present invention embodiment It tests code and is written to the step of first instance programmed cell and include：Data are divided at least one first data segment and are generated at least One first check code section, wherein each first check code section corresponds to one of described first data segment.It is described according to Data are written with the check code corresponding to data to the step of first instance programmed cell according to the second code check and include：It will count According to being divided at least one second data segment and generating at least one second check code section, wherein each second check code section corresponds to In one of described second data segment.One data length of wherein each first data segment is longer than each described second One data length of data segment, and a data length of each first check code section is identical to each second verification One data length of code section.
In one example of the present invention embodiment, the second code check of the foundation is by data and corresponding to the check code of data It is written to the step of first instance programmed cell and includes：Judge whether the data length of data is more than N number of basic management unit Data length, wherein N is positive integer, and the data length of N+1 basic management unit is equal to first instance sequencing list The amount of capacity of member；When the data length of data is no more than the data length of N number of basic management unit, only in accordance with the second code check Data and the check code corresponding to data are written to first instance programmed cell；And when the data length of data is more than N When the data length of a basic management unit, the check code of the data of first part and first part is written according to the second code check It is written to the entity program to first instance programmed cell and by the check code of the data of second part and second part Change the second instance programmed cell in unit.
In one example of the present invention embodiment, the second instance programmed cell belong to first instance erased cell or The second instance erased cell of the second class entity erased cell is also belonged in entity erased cell described in person.
In one example of the present invention embodiment, the data length of the data of the first part meets N number of basic management The data length of unit, and the method for writing data further includes：At least one first inactive bit is written to first instance In programmed cell full part is write to fill up the not check code of the data by first part and first part；And it will at least One second inactive bit is written into second instance programmed cell to fill up the not data by second part and second part Check code writes full part.
The present invention separately provides a kind of memory storage apparatus, and the memory storage apparatus includes connecting interface unit, can Manifolding formula non-volatile memory module and memorizer control circuit unit.Connecting interface unit is being electrically connected to host system System.Reproducible nonvolatile memorizer module includes multiple entity erased cells, and each entity erased cell packet Include multiple entity program units.It is non-volatile with duplicative that memorizer control circuit unit is electrically connected to connecting interface unit Memory module.To receive write instruction, wherein write instruction instruction writes data into wherein memorizer control circuit unit To at least one of multiple logic units, wherein at least one of the logic unit maps to the entity program Change the first instance programmed cell in unit, and first instance programmed cell belong in the entity erased cell the One entity erased cell.Memorizer control circuit unit is also erased to judge that first instance erased cell belongs to first kind entity Unit or the second class entity erased cell, wherein the first bit error rate of first kind entity erased cell are less than the second class entity Second bit error rate of erased cell.When first instance erased cell belongs to first kind entity erased cell, memory control Data and the check code corresponding to data are also programmed to first instance sequencing by circuit unit processed to the first code check of foundation Unit.When first instance erased cell belongs to the second class entity erased cell, memorizer control circuit unit is also to foundation Data and the check code corresponding to data are programmed to first instance programmed cell by the second code check, wherein the first code check is higher than Second code check.
In one example of the present invention embodiment, the memorizer control circuit unit judges first instance erased cell category Include in the operation of first kind entity erased cell or the second class entity erased cell：Judge the bit of first instance erased cell Whether error rate assessed value meets Sharp criteria；If the bit error rate assessed value of first instance erased cell does not meet door sill protector Part, judgement first instance erased cell belong to first kind entity erased cell；And if the bit of first instance erased cell is wrong Accidentally rate assessed value meets Sharp criteria, and judgement first instance erased cell belongs to the second class entity erased cell.
In one example of the present invention embodiment, the memorizer control circuit unit according to first instance also erasing Number information of erasing, write-in number information, reading times information, error bit number information, wrong bitrate information, the number of unit According at least one or at least combination of resting period information and temperature information, to determine first instance erased cell Bit error rate assessed value.
In one example of the present invention embodiment, the memorizer control circuit unit according to the first code check by data with It is written to the operation of first instance programmed cell corresponding to the check code of data and includes：Data are divided at least one first data Section and generation at least one first check code section, wherein each first check code section corresponds to its of first data segment One of.Data and the check code corresponding to data are written to the according to the second code check for the memorizer control circuit unit The operation of one entity program unit includes：Data are divided at least one second data segment and generate at least one second check code Section, wherein each second check code section corresponds to one of described second data segment.Wherein each first number A data length of each second data segment, and each first check code section are identical to according to a data length of section A data length be shorter than a data length of each second check code section.
In one example of the present invention embodiment, the memorizer control circuit unit according to the first code check by data with It is written to the operation of first instance programmed cell corresponding to the check code of data and includes：Data are divided at least one first data Section and generation at least one first check code section, wherein each first check code section corresponds to its of first data segment One of.Data and the check code corresponding to data are written to the according to the second code check for the memorizer control circuit unit The operation of one entity program unit includes：Data are divided at least one second data segment and generate at least one second check code Section, wherein each second check code section corresponds to one of described second data segment.Wherein each first number It is longer than a data length of each second data segment according to a data length of section, and each first check code section One data length is identical to a data length of each second check code section.
In one example of the present invention embodiment, the memorizer control circuit unit according to the second code check by data with It is written to the operation of first instance programmed cell corresponding to the check code of data and includes：Judge whether the data length of data surpasses The data length of N number of basic management unit is crossed, wherein N is positive integer, and the data length of N+1 basic management unit is equal to The amount of capacity of first instance programmed cell；When the data length of data is no more than the data length of N number of basic management unit When, data and the check code corresponding to data are written to first instance programmed cell only in accordance with the second code check；And when number According to data length be more than the data length of N number of basic management unit when, according to the second code check by the data of first part and the The check code of a part is written to first instance programmed cell and by the check code of the data of second part and second part It is written to the second instance programmed cell in the entity program unit.
In one example of the present invention embodiment, a data length of the data of the first part meets N number of basic pipe Manage the data length of unit.The memorizer control circuit unit is also being written at least one first inactive bit to first real In body programmed cell full part is write to fill up the not check code of the data by first part and first part.The storage Device control circuit unit also to will at least one second inactive bit be written into second instance programmed cell with fill up not by The data of second part and the check code of second part write full part.
The present invention separately provides a kind of memorizer control circuit unit, and the memorizer control circuit unit is for controlling and can answer Write formula non-volatile memory module.Wherein reproducible nonvolatile memorizer module includes multiple entity erased cells, often The one entity erased cell includes multiple entity program units, and memorizer control circuit unit include host interface, Memory interface, error checking and correcting circuit and memory management circuitry.Host interface is being electrically connected to host system.It deposits Memory interface is being electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host and connects Mouth, memory interface and error checking and correcting circuit.Wherein memory management circuitry is to receive write instruction, wherein being written Instruction instruction writes data at least one in multiple logic units, wherein in the logic unit at least within One of map to first instance programmed cell in the entity program unit, and first instance programmed cell belongs to A first instance erased cell in the entity erased cell.Memorizer control circuit unit is also judging that first instance is smeared Except unit belongs to first kind entity erased cell or the second class entity erased cell, wherein the first of first kind entity erased cell Bit error rate is less than the second bit error rate of the second class entity erased cell.When first instance erased cell belongs to the first kind When entity erased cell, memory management circuitry is also to send the first command serial, wherein the first command serial indicates foundation Data and the check code corresponding to data are programmed to first instance programmed cell by the first code check.When first instance erased cell When belonging to the second class entity erased cell, memory management circuitry is also to send the second command serial, wherein second strings of commands Data and the check code corresponding to data are programmed to first instance programmed cell by row instruction according to the second code check, wherein first Code check is higher than the second code check.
In one example of the present invention embodiment, the memory management circuitry judges that first instance erased cell belongs to The operation of a kind of entity erased cell or the second class entity erased cell includes：Judge the bit-errors of first instance erased cell Whether rate assessed value meets Sharp criteria；If the bit error rate assessed value of first instance erased cell does not meet Sharp criteria, Judgement first instance erased cell belongs to first kind entity erased cell；And if the bit error rate of first instance erased cell Assessed value meets Sharp criteria, and judgement first instance erased cell belongs to the second class entity erased cell.
In one example of the present invention embodiment, the memory management circuitry is also to according to first instance erased cell Number information of erasing, write-in number information, reading times information, error bit number information, wrong bitrate information, data deposit At least one or at least combination for putting temporal information and temperature information, to determine the ratio of first instance erased cell Special error rate assessed value.
In one example of the present invention embodiment, the operation that the memory management circuitry sends the first command serial is also wrapped It includes：Data are divided at least one first data segment and control error checking and generate at least one first check code with correcting circuit Section, wherein each first check code section corresponds to one of described first data segment.Wherein memory management circuitry The operation for sending the second command serial further includes：Data are divided at least one second data segment and control error checking and correction Circuit generates at least one second check code section, wherein each second check code section corresponds to second data segment wherein One of.One data length of wherein each first data segment is identical to a data length of each second data segment, And a data length of each first check code section is shorter than a data length of each second check code section.
In one example of the present invention embodiment, the operation that the memory management circuitry sends the first command serial is also wrapped It includes：Data are divided at least one first data segment and control error checking and generate at least one first check code with correcting circuit Section, wherein each first check code section corresponds to one of described first data segment.Wherein memory management circuitry The operation for sending the second command serial further includes：Data are divided at least one second data segment and control error checking and correction Circuit generates at least one second check code section, wherein each second check code section corresponds to second data segment wherein One of.One data length of wherein each first data segment is longer than a data length of each second data segment, and And a data length of each first check code section is identical to a data length of each second check code section.
In one example of the present invention embodiment, the memory management circuitry sends the operation packet of the second command serial It includes：Judge data data length whether be more than N number of basic management unit data length, wherein N is positive integer, and N+1 The data length of a basic management unit is equal to the amount of capacity of first instance programmed cell.When the data length of data does not surpass When crossing the data length of N number of basic management unit, the second command serial is sent, wherein the instruction of the second command serial is according to second code Rate and only data are written with corresponding to the check codes of data to first instance programmed cell.When the data length of data is more than When the data length of N number of basic management unit, the second command serial is sent, wherein the instruction of the second command serial is according to the second code check The check code of the data of first part and first part need to be written to first instance programmed cell and by second part The check code of data and second part is written to the second instance programmed cell in the entity program unit.
In one example of the present invention embodiment, the data length of the data of the first part meets N number of basic management The data length of unit.Second command serial also indicates at least one first inactive bit and need to be written into first instance sequencing list Full part is write to fill up the not check code of the data by first part and first part, and at least one second invalid in member It is written into second instance programmed cell than special procuring to fill up the check code of the not data by second part and second part Write full part.
Based on above-mentioned, method for writing data, memory storage apparatus and memorizer control circuit unit proposed by the present invention, Can be first kind entity erased cell or the second class according to the entity erased cell in reproducible nonvolatile memorizer module Entity erased cell, and adaptively according to the first code check or higher than the first code check the second code check come by data with correspond to this The check code of data programs the entity program unit of so far entity erased cell.Thereby, even if the bit of entity erased cell Error rate is more than preset permissible range, this entity erased cell still can be used for a prolonged period, without being directly rejected.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make Carefully it is described as follows.
Description of the drawings
Figure 1A shows the host system and memory storage apparatus of one example of the present invention embodiment；
Figure 1B shows showing for the computer of one example of the present invention embodiment, input/output device and memory storage apparatus It is intended to；
Fig. 1 C show the host system of one example of the present invention embodiment and the schematic diagram of memory storage apparatus；
Fig. 2 shows the schematic block diagrams of memory storage apparatus shown in figure 1A；
Fig. 3 shows the schematic block diagram of the memorizer control circuit unit of one example of the present invention embodiment；
Fig. 4 shows the example signal of the management reproducible nonvolatile memorizer module of one example of the present invention embodiment Figure；
Fig. 5 show one example of the present invention embodiment according to the first code check by data with corresponding to this data check code extremely The example schematic of entity program unit；
Fig. 6 shows that one example of the present invention embodiment writes data and the check code corresponding to this data according to the second code check Enter to the example schematic of entity program unit；
Fig. 7 shows another example of the present invention embodiment according to the second code check by data and corresponding to the check code of this data It is written to the example schematic of entity program unit；
Fig. 8 shows another example of the present invention embodiment according to the second code check by data and corresponding to the check code of this data It is written to the example schematic of entity program unit；
Fig. 9 shows the flow chart of the method for writing data of one example of the present invention embodiment；
Figure 10 shows the flow chart of the method for writing data of another example of the present invention embodiment.
Reference sign：
1000：Host system；
1100：Computer；
1102：Microprocessor；
1104：Random access memory；
1106：Input/output device；
1108：System bus；
1110：Data transmission interface；
1202：Mouse；
1204：Keyboard；
1206：Display；
1208：Printer；
1212：USB flash disk；
1214：Memory card；
1216：Solid state disk；
1310：Digital camera；
1312：SD card；
1314：Mmc card；
1316：Memory stick；
1318：CF cards；
1320：Embedded storage device；
100：Memory storage apparatus；
102：Connecting interface unit；
104：Memorizer control circuit unit；
106：Reproducible nonvolatile memorizer module；
304 (0)~304 (R)：Entity erased cell；
202：Memory management circuitry；
204：Host interface；
206：Memory interface；
252：Buffer storage；
254：Electric power management circuit；
256：Error checking and correcting circuit；
402：Memory block；
406：System area；
410 (0)~410 (D)：Logical address；
501,601,701,801：Data；
510(0),610(0),710(0),810(0)：Logical program unit；
512(0),612(0),712(0),812(0),812(1)：Entity program unit；
501_1~501_4,601_1~601_4,701_1~701_8,801_1~801_5：Data segment；
502_1~502_4,602_1~602_4,702_1~702_8,802_1~802_5：Check code section；
S902,S904,S906,S908：Each step of method for writing data；
S1002,S1004,S1006,S1008,S1010,S1012：Each step of method for writing data.
Specific implementation mode
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is used together with host system, so that host System can write data into memory storage apparatus or be read from memory storage apparatus data.
Figure 1A shows the host system and memory storage apparatus of one example of the present invention embodiment；Figure 1B shows the present invention The computer of an exemplary embodiment, input/output device and memory storage apparatus schematic diagram；Fig. 1 C show the one of the present invention The host system of exemplary embodiment and the schematic diagram of memory storage apparatus.
Figure 1A is please referred to, host system 1000 generally comprises computer 1100 and input/output (input/output, I/O) Device 1106.Computer 1100 includes microprocessor 1102, random access memory (random accessmemory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes mouse 1202, the key such as Figure 1B Disk 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Fig. 2 1106, input/output device 1106 can further include other devices.
In embodiments of the present invention, memory storage apparatus 100 is by data transmission interface 1110 and host system 1000 other elements electrical connection.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106 Operation can write data into memory storage apparatus 100 or read data from memory storage apparatus 100.For example, storage Device storage device 100 can be USB flash disk 1212 as shown in Figure 2, memory card 1214 or solid state disk (Solid State Drive, SSD) 1216 equal type nonvolatile storage device.
In general, host system 1000 is that can substantially coordinate with memory storage apparatus 100 to store appointing for data Meaning system.Although in this exemplary embodiment, host system 1000 is explained with computer system, however, of the invention another Host system 1000 can be digital camera, video camera, communication device, audio player or video playing in one exemplary embodiment The systems such as device.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage dress 100 are set as its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF cards 1318 or insertion Formula storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 include embedded multi-media card (Embedded MMC, eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host system.
Fig. 2 shows the schematic block diagrams of memory storage apparatus shown in figure 1A.
Fig. 2 is please referred to, memory storage apparatus 100 includes connecting interface unit 102, memorizer control circuit unit 104 With reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connecting interface unit 102 is compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, even Connection interface unit 102 can also be to meet parallel advanced technology annex (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) Standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, ultrahigh speed two generations (Ultra High Speed-II, UHS-II) interface standard, safe digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form driving electrical interface (Integrated Device Electronics, IDE) standard or Other suitable standards.In this exemplary embodiment, connecting interface unit 102 can be encapsulated with memorizer control circuit unit 104 In a chip, or it is laid in outside a chip comprising memorizer control circuit unit 104.
Memorizer control circuit unit 104 is executing in the form of hardware or multiple logic gates of form of firmware implementation or control System instruction, and data are carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host system 1000 The operations such as be written, read and erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and to The data that host system 1000 is written.Reproducible nonvolatile memorizer module 106 has entity erased cell 304 (0)~304 (R).For example, entity erased cell 304 (0)~304 (R) can belong to the same memory crystal grain (die) or belong to In different memory crystal grains.Each entity erased cell is respectively provided with a plurality of entity program units, and belongs to same The entity program unit of a entity erased cell can be written independently and simultaneously be erased.For example, each entity is erased Unit is made of 128 entity program units.However, it is necessary to be appreciated that, the invention is not limited thereto, and each entity is smeared Except unit be can be by 64 entity program units, 256 entity program units or any other a entity program unit It is formed.
More specifically, each entity erased cell includes a plurality of character line and a plurality of bit line, each character line There are one storage units with the configuration of each bit line infall.Each storage unit can store one or more bits.Same In one entity erased cell, all storage units can be erased together.In this exemplary embodiment, entity erased cell is The least unit erased.That is, each entity erased cell contains the storage unit of minimal amount being erased together.For example, Entity erased cell is physical blocks.On the other hand, the storage unit on the same character line can form one or more entity journeys Sequence unit.If each storage unit can store 2 or more bits, the entity program unit on the same character line It can be classified as lower entity program unit and upper entity program unit.In general, the write-in of lower entity program unit Speed can be more than the writing speed of upper entity program unit.In this exemplary embodiment, entity program unit is sequencing Minimum unit.That is, entity program unit is the minimum unit that data are written.For example, entity program unit is physical page Face or entity fan (sector).In this exemplary embodiment, entity program unit is physical page, and each entity Programmed cell includes data bit area and redundancy ratio special zone.Data bit area is fanned comprising multiple entities, to store user Data, and redundancy ratio special zone is to the data (for example, check code) of storage system.In this exemplary embodiment, each number Include that 32 entities are fanned, and the size of entity fan is 512 bytes (byte, B) according to bit area.However, in other examples reality It applies in example, also may include 8,16 in data bit area or number more or fewer entities fan, the present invention are not intended to limit reality The size and number of body fan.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module, i.e. at least two bit can be stored in a storage unit.However, this Invent without being limited thereto, reproducible nonvolatile memorizer module 106 can also be single-order storage unit (Single Level Cell, SLC) NAND type flash memory module, Complex Order storage unit (Trinary Level Cell, TLC) NAND type be fast Flash memory module, other flash memory modules or other memory modules with the same characteristics.
Fig. 3 shows the schematic block diagram of the memorizer control circuit unit of one example of the present invention embodiment.
Fig. 3 is please referred to, memorizer control circuit unit 104 includes memory management circuitry 202, host interface 204 and deposits Memory interface 206.
Memory management circuitry 202 to control memory control circuit unit 104 integrated operation.Specifically, it deposits Reservoir, which manages circuit 202, has multiple control instructions, and when memory storage apparatus 100 operates, these control instruction meetings It is performed the operations such as to carry out the write-in of data, read and erase.When illustrating the operation of memory management circuitry 202 below, etc. It is same as illustrating the operation of memorizer control circuit unit 104, below and repeat no more.
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with form of firmware.For example, Memory management circuitry 202 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 100 operates, these control instructions can be by microprocessor Unit is executed the operations such as to carry out the write-in of data, read and erase.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also procedure code form The specific region of reproducible nonvolatile memorizer module 106 is stored in (for example, being exclusively used in storing in memory module 106 The system area of system data) in.In addition, memory management circuitry 202 has microprocessor unit (not shown), read-only memory (not shown) and random access memory (not shown).In particular, this read-only memory has boot code (boot code), and And when memorizer control circuit unit 104 is enabled, microprocessor unit, which can first carry out this boot code, will be stored in and can answer Write the random access memory that the control instruction in formula non-volatile memory module 106 is loaded into memory management circuitry 202 In.Later, microprocessor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the operations.
In addition, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also a hardware Form carrys out implementation.For example, memory management circuitry 202 include microcontroller, memory management unit, memory writing unit, Memory reading unit, memory erased cell and data processing unit.Memory management unit, is deposited memory writing unit Reservoir reading unit, memory erased cell and data processing unit are electrically connected to microcontroller.Wherein, memory management list Member is managing the entity erased cell of reproducible nonvolatile memorizer module 106；Memory writing unit is to pair can Manifolding formula non-volatile memory module 106 assigns write instruction to write data into type nonvolatile mould In block 106；Memory reading unit to reproducible nonvolatile memorizer module 106 assigning reading instruction with from can answer It writes in formula non-volatile memory module 106 and reads data；Memory erased cell is to duplicative non-volatile memories Device module 106 assigns instruction of erasing so that data to be erased from reproducible nonvolatile memorizer module 106；And data processing Unit to handle be intended to be written data to reproducible nonvolatile memorizer module 106 and from duplicative it is non-volatile The data read in memory module 106.
Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identify host system 1000 The instruction transmitted and data.That is, the instruction that is transmitted of host system 1000 and data can by host interface 204 come It is sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is compatible with SATA standard.However, must It is appreciated that the invention is not limited thereto, host interface 204 can also be to be compatible with PATA standards, IEEE1394 standards, PCI Express standards, USB standard, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS marks Standard, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative Memory module 106.It can be via storage to the data of reproducible nonvolatile memorizer module 106 that is, being intended to be written Device interface 206 is converted to the 106 receptible format of institute of reproducible nonvolatile memorizer module.
In one example of the present invention embodiment, memorizer control circuit unit 104 further includes buffer storage 252, electricity Power management circuits 254 and error checking and correcting circuit 256.
Buffer storage 252 is electrically connected to memory management circuitry 202 and is configured to temporarily store come from host system 1000 data and the data for instructing or coming from reproducible nonvolatile memorizer module 106.
Electric power management circuit 254 is electrically connected to memory management circuitry 202 and to control memory storage device 100 power supply.
Error checking is electrically connected to memory management circuitry 202 and to execute error checking with correcting circuit 256 With correction program to ensure the correctness of data.Specifically, it is received from host system 1000 when memory management circuitry 202 When to write instruction, error checking generates corresponding check code with the data that correcting circuit 256 can be this corresponding write instruction, and And memory management circuitry 202 data of this corresponding write instruction can be written with corresponding check code it is non-volatile to duplicative In property memory module 106.For example, this check code includes error correcting code (error correcting code, ECC code) With error-detecting code (error detecting code, EDC code) at least one.In addition, this check code can be with Including the code that arbitrarily can be used for verifying the correctness of data, the present invention does not limit.Later, work as memory management Circuit 202 can read the corresponding verification of this data simultaneously when reading data from reproducible nonvolatile memorizer module 106 Code, and error checking can execute error checking and correction journey according to this check code with correcting circuit 256 to read data Sequence.
Fig. 4 shows the example signal of the management reproducible nonvolatile memorizer module of one example of the present invention embodiment Figure.
It will be appreciated that being described herein the behaviour of the entity erased cell of reproducible nonvolatile memorizer module 106 When making, it is concept in logic to carry out application entity erased cell with the words such as " extraction ", " grouping ", " division ", " association ".Namely It says, the physical location of the entity erased cell of reproducible nonvolatile memorizer module 106 is not changed, but right in logic The entity erased cell of reproducible nonvolatile memorizer module 106 is operated.
Fig. 4 is please referred to, memory management circuitry 202 can smear the entity of reproducible nonvolatile memorizer module 106 Except unit 304 (0)~304 (R) is logically divided into multiple regions, for example, memory block 402 and system area 406.
The entity erased cell of memory block 402 is to store the data from host system 1000.Meeting in memory block 402 Store valid data and invalid data.For example, when host system will delete a valid data, deleted data may be also It is stored in memory block 402, but invalid data can be marked as.The entity erased cell for not storing valid data is also claimed For the entity erased cell that leaves unused.The also referred to as idle entity program list of entity program unit of valid data is not stored Member.For example, idle entity erased cell will be become by being erased later entity erased cell.If memory block 402 or system area When having the damage of entity erased cell in 406, the entity that the entity erased cell in memory block 402 can also be used to replace damage is smeared Except unit.If there is no entity erased cell of the available entity erased cell to replace damage in memory block 402, then store Whole memory storage device 100 can be declared as write protection (write protect) state by device management circuit 202, and nothing Data are written in method again.
The entity erased cell of system area 406 is to record system data, and wherein this system data includes about storage The manufacturer of device chip and model, the entity program of the entity erased cell number of memory chip, each entity erased cell Unit number etc..
Memory block 402 and the quantity of the entity erased cell of system area 406 can according to different memory specifications and It is different.Further, it is necessary to be appreciated that, in the operation of memory storage apparatus 100, entity erased cell is associated with to memory block 402 can dynamically change with the grouping relationship of system area 406.For example, when in system area 406 entity erased cell damage and by When the entity erased cell substitution of memory block 402, then the entity erased cell originally in memory block 402 can be associated to system area 406。
Memory management circuitry 202 can configure logical address 410 (0)~410 (D) to map to part in memory block 402 Entity erased cell 304 (0)~304 (A).Host system 1000 is to be deposited by logical address 410 (0)~410 (D) to access Data in storage area 402.In this exemplary embodiment, a logical address is to map to an entity fan, multiple logical addresses A logical program unit can be formed, and multiple logical program units can form a logic erased cell.One is patrolled It can map to one or more entity program units, and a logic erased cell can be mapped to collect programmed cell One or more entity erased cells.
Memory management circuitry 202 can receive the write instruction from host system 1000.This write instruction is indicated one Data are written to one or more logic units.In this exemplary embodiment, a logic unit refer to logical address 410 (0)~ A logical address (also referred to as the first logical address) in 410 (D).First logical address belongs to one or more first logic journeys Sequence unit, and the first logical program unit maps to one or more first instance programmed cells of memory block 402.So And in another exemplary embodiment, a logic unit may also mean that a logical program unit (for example, the first logic Programmed cell).It is writing data into before first instance programmed cell, memory management circuitry 202 can judge first Entity erased cell (also referred to as first instance erased cell) belonging to entity program unit is first kind entity erased cell Or the second class entity program unit.Wherein, first kind entity erased cell bit error rate (bit error rate, The bit error rate of a kind of entity erased cell is also referred to as the first bit error rate) the second class entity program unit can be less than Bit error rate (also referred to as the second bit error rate).The bit error rate of entity erased cell is referred to storing and be smeared in this entity After being read except the data in unit, error bit ratio shared in the data read out.In an exemplary embodiment, Also the second class entity program unit can be known as high error rate entity program unit.
In an exemplary embodiment, memory management circuitry 202 can judge the bit error rate of first instance erased cell Whether assessed value meets Sharp criteria.If the bit error rate assessed value of first instance erased cell does not meet Sharp criteria, deposit Reservoir management circuit 202 can judge that first instance erased cell belongs to first kind entity erased cell.The list if first instance is erased The bit error rate assessed value of member meets Sharp criteria, then memory management circuitry 202 can judge first instance erased cell category In the second class entity erased cell.For example, in an exemplary embodiment, the bit error rate assessed value of an entity erased cell It is " 0 " or " 1 " respectively with two states.Only when the bit error rate assessed value of an entity erased cell is " 1 ", Memory management circuitry 202 can judge that the bit error rate assessed value of this entity erased cell meets Sharp criteria.
In addition, in another exemplary embodiment, the bit error rate assessed value of an entity erased cell can then have Two or more states, and each state is related with the bit error rate of this entity erased cell.In an exemplary embodiment In, bit error rate assessed value can be any one numerical value in 0~100.The bit error rate of one entity erased cell is commented Valuation is higher, indicates that the bit error rate of this entity erased cell is higher.The bit error rate assessment of one entity erased cell Value is lower, indicates that the bit error rate of this entity erased cell is lower.Only when the bit error rate of entity erased cell is assessed When value reaches threshold value (for example, 70), memory management circuitry 202 can judge the bit error rate of this entity erased cell Assessed value meets Sharp criteria.In addition, bit error rate assessed value can also be to be indicated in the form of arbitrary, and it is not limited to It states.
In general, the number of erasing of the bit error rate of entity erased cell and entity erased cell, write-in number and Reading times are proportionate (positive correlation).Wherein, the number of erasing of entity erased cell, write-in number and Reading times refer respectively to the number that entity erased cell is erased, is written and read.One entity erased cell is smeared Except at least one of number, write-in number and reading times are higher, then the data quilt in this entity erased cell is stored The quantity for the error bit for being included when reading may be more.Wherein, but with erase number for entity erased cell ratio The influence of special error rate is maximum.In addition, in some cases, the bit error rate of entity erased cell may also can be smeared with entity Except the data resting period of unit and/or temperature are related.The data resting period of entity erased cell refers to that data are stored In entity erased cell how long, and can take in the resting period of each data in an entity erased cell The maximum or average value, and it is without being limited thereto.In addition, each entity in reproducible nonvolatile memorizer module 106 is smeared Except the temperature of unit identical may can also be different, but there would generally be narrow difference.
When an entity erased cell number of erasing, write-in number and reading times at least one be more than one preset Number, an entity erased cell the data resting period be more than a preset time and/or the temperature of an entity erased cell When beyond a preset temperature range, stores the data in this entity erased cell and be read out included error bit number And/or wrong bitrate can be sharply increased, and have very high probability that can be examined with correcting circuit 256 more than error checking The maximum quantity for the error bit surveyed and/or corrected.Therefore, in an exemplary embodiment, memory management circuitry 202 can root According to the number information of erasing of an entity erased cell, write-in number information, reading times information, error bit number information, mistake At least one or at least combination of bit error rate information, data resting period information and temperature information, to determine The bit error rate assessed value of this entity erased cell.For example, in an exemplary embodiment, according to number information of erasing, storage Whether device management circuit 202 can judge the number of erasing of first instance erased cell more than a preset times.This preset times example It is preset in this way by manufacturer or by user's sets itself.For example, this preset times can be for 3000 times or more or more It is few.When the number of erasing of first instance erased cell is more than this preset times, memory management circuitry 202 can be by first instance The bit error rate assessed value of erased cell is set as " 1 " or corresponding any number.Conversely, when first instance erased cell When number of erasing is not above this preset times, then memory management circuitry 202 can be wrong by the bit of first instance erased cell Accidentally rate assessed value is set as " 0 " or corresponding any number.
In other words, for a completely new reproducible nonvolatile memorizer module, this duplicative is non-easily All entity erased cells all can be first kind entity erased cell in the property lost memory module.However, as this can make carbon copies The usage time of formula non-volatile memory module increases, and will be had in this reproducible nonvolatile memorizer module more next More entity erased cell can because be performed erase, be written and/or the number of read operation increases and it is real as the second class Body erased cell.Alternatively, according to time data memory increase and temperature change, the first kind entity erased cell of part may also The second class entity erased cell can be changed into.In other words, the factor of any bit error rate that can influence entity erased cell, all Can be used as judging an entity erased cell be first kind entity erased cell or the second class entity erased cell according to According to.
Memory management circuitry 202 can note down the entity erased cell for being determined to be the second class entity erased cell In a table.When memory management circuitry 202 is intended to the first instance program write data into first instance erased cell is belonged to When changing unit, memory management circuitry 202 can inquire this table, to learn that first instance erased cell is that first kind entity is smeared Except unit or the second class entity erased cell.In addition, memory management circuitry 202 can also be in a manner of subregion or grouping, By the entity erased cell for being determined to be the second class entity erased cell be associated in memory block 402 a high error rate area or One high error rate group, the present invention do not limit.
It is first kind entity erased cell or the second class entity erased cell, memory pipe according to first instance erased cell Managing circuit 202 can be selectively according to one first code check (code rate) or one second code check come by this data and corresponding to this The check code programming (programming) of data is to first instance programmed cell, wherein the first code check is higher than the second code check.Example Such as, when first instance erased cell is first kind entity erased cell, memory management circuitry 202 can be come according to the first code check This data and the check code corresponding to this data are programmed to first instance programmed cell.When first instance erased cell is When two class entity erased cells, then memory management circuitry 202 by this data and can correspond to this data according to the second code check Check code be programmed to first instance programmed cell.In an exemplary embodiment, programming is also referred to as written.Namely It says, a data is programmed to an entity program unit, be equal to and a data are written to an entity program list Member.
Specifically, the data that memory management circuitry 202 can be intended to be written are divided into one or more data segments and control It checks and generates one or more check code sections with correcting circuit 256, wherein each check code section corresponds to a data segment.? This, a data segment is the unit for generating a check code section, and a check code section is for its corresponding number It is verified and/or is corrected according to section.As an example it is assumed that k is the data length of a data segment, and n-k corresponds to this The data length of the check code section of data segment, then the ratio (that is, k/n) of k and n can be described as code check.If in particular, the number to be written According to data length meet the data length of a data segment, then itself is a data segments for this data, and correspond to this The check code of data just corresponds to the check code section of this data segment.If the data length for the data to be written meets multiple data The summation of the data length of section, then this data is divided into multiple data segments, and can be wrapped corresponding to the check code of this data Include multiple check code sections corresponding to these data segments.
In this exemplary embodiment, when first instance erased cell is first kind entity erased cell, memory management Circuit 202 is to be intended to write according to the data length (that is, first code check) of the data length of preset data segment and check code section The data entered are written with corresponding check code to first instance programmed cell.
Fig. 5 show one example of the present invention embodiment according to the first code check by data with corresponding to this data check code extremely The example schematic of entity program unit.
Please refer to Fig. 5, it is assumed that data 501 are written to logical address the write instruction instruction from host system 1000 410(0).For example, the data length of data 501 is 4KB (1KB=1024bytes).Assuming that logical address 410 (0) belongs to logic Programmed cell 510 (0), then memory management circuitry 202 can be by the write-in of data 501 to logical program unit 510 (0).It patrols It collects programmed cell 510 (0) and maps to entity program unit 512 (0).When the entity belonging to entity program unit 512 (0) When erased cell 304 (0) is first kind entity erased cell, based on the data length of data 501, memory management circuitry 202 Data 501 can be divided for data segment 501_1~501_4.For example, the data length of each data segment 501_1~501_4 is 1KB.It checks and will produce check code section 502_1~502_4 corresponding to data segment 501_1~501_4 with correcting circuit 256.Example Such as, the data length of each check code section 502_1~502_4 is 70B (1B=1bytes).That is, when a data Length is that the data segment of 1KB is read out, this data segment can be verified according to data length is the check code section of 70B And/or correction.Memory management circuitry 202 can be according to a preset rules by data segment 501_1~501_4 and check code section 502_ 1~502_4 is written to entity program unit 512 (0).For example, in this exemplary embodiment, each storage check code section Physical address range is to continue in the physical address range (as shown in Figure 5) for storing the data segment corresponding to this check code section.So And in another exemplary embodiment, all data segments can also be to be stored separately with check code section.For example, will own Data segment be stored in the physical address ranges of storage user's data, and all check code sections are stored in storage redundancy The physical address range of data.
On the other hand, it in this exemplary embodiment, when first instance erased cell is the second class entity erased cell, deposits Reservoir management circuit 202 can increase the data length of the check code section corresponding to each data segment, with according to preset data The data length of section and the data length (that is, second code check) of longer check code section are come the data for being intended to write-in and corresponding school Code is tested to be written to first instance programmed cell.
Fig. 6 shows that one example of the present invention embodiment writes data and the check code corresponding to this data according to the second code check Enter to the example schematic of entity program unit.
Please refer to Fig. 6, it is assumed that data 601 are written to logical address the write instruction instruction from host system 1000 410(1).For example, the data length of data 501 is 4KB.Assuming that logical address 410 (1) belongs to logical program unit 610 (0), then memory management circuitry 202 can be by the write-in of data 601 to logical program unit 610 (0).Logical program unit 610 (0) map to entity program unit 612 (0).When the entity erased cell 304 belonging to entity program unit 612 (0) (1) when being the second class entity erased cell, based on the data length of data 601, memory management circuitry 202 can be by data 601 It is divided into data segment 601_1~601_4.For example, the data length of each data segment 601_1~601_4 is 1KB.Inspection and school Positive circuit 256 will produce check code section 602_1~602_4 corresponding to data segment 601_1~601_4.For example, each is verified The data length of code section 602_1~602_4 is 140B.That is, in this exemplary embodiment, the number of each check code section Be according to length Fig. 5 exemplary embodiment in 2 times of data length of each check code section, and it is without being limited thereto.For example, this times Number can also be 3 times, 4 times or more.Memory management circuitry 202 according to above-mentioned preset rules by data segment 601_1~ 601_4 and check code section 602_1~602_4 is written to entity program unit 612 (0).That is, when a data length That the data segment of 1KB is read out, this data segment can by according to data length be the check code section of 140B carry out verification and/ Or correction.Thereby, even if the entity erased cell for storing data is the second class entity erased cell, in read data More error bits can be found and/or correct.For example, in the exemplary embodiment of Fig. 5,1 data length is 1KB There are about the error bits of 40bits to be found in data segment, and in this exemplary embodiment, 1 data length is 1KB There may be the error bit of 80bits that can be found in data segment.
However, in another exemplary embodiment, when first instance erased cell is the second class entity erased cell, storage Device management circuit 202 does not go to change the data length of check code section, but removes to reduce the data length of each data segment, with root It is intended to write-in according to the data length (that is, second code check) of data length and the preset check code section of shorter data segment Data are written with corresponding check code to first instance programmed cell.
Fig. 7 shows another example of the present invention embodiment according to the second code check by data and corresponding to the check code of this data It is written to the example schematic of entity program unit.
Please refer to Fig. 7, it is assumed that data 701 are written to logical address the write instruction instruction from host system 1000 410(2).For example, the data length of data 701 is 4KB.Assuming that logical address 410 (2) belongs to logical program unit 710 (0), then memory management circuitry 202 can be by the write-in of data 701 to logical program unit 710 (0).Logical program unit 710 (0) map to entity program unit 712 (0).When the entity erased cell 304 belonging to entity program unit 712 (0) (2) when being the second class entity erased cell, based on the data length of data 701, memory management circuitry 202 can be by data 701 It is divided into data segment 701_1~701_8.For example, the data length of each data segment 701_1~701_8 is 512B.Namely It says, in this exemplary embodiment, the data length of each data segment is each data segment in the exemplary embodiment of Fig. 5 1/2 times of data length, and it is without being limited thereto.For example, this multiple can also be 1/3 times, 1/4 times or less.It checks and corrects Circuit 256 will produce check code section 702_1~702_8 corresponding to data segment 701_1~701_8.For example, each check code The data length of section 702_1~702_8 is 70B.Memory management circuitry 202 is according to above-mentioned preset rules by data segment 701_1 ~701_8 and check code section 702_1~702_8 is written to entity program unit 712 (0).That is, when a data are long Degree is that the data segment of 512B is read out, this data segment can be verified according to data length is the check code section of 70B And/or correction.Thereby, even if being the second class entity erased cell, read number for storing the entity erased cell of data More error bits can be found and/or correct in.For example, in the exemplary embodiment of Fig. 5,1 data length is There are about the error bits of 40bits to be found in the data segment of 1KB, and in this exemplary embodiment, 1 data length is There may be the error bit of 40bits that can be found in the data segment of 512B.And so on, it is 1KB in the summation of data length 2 data segments in, it is possible to have the error bit of 80bits that can be found.
If it is noted that according to the definition (that is, k/n) of above-mentioned code check, first yard in the exemplary embodiment of Fig. 5 Rate can be indicated with 1024/ (1024+70), and the second code check in the exemplary embodiment of Fig. 6 can be with 1024/ (1024+ 140) it indicates, and the second code check in the exemplary embodiment of Fig. 7 can be indicated with 512/ (512+70).Namely It says, when the bit error rate of an entity erased cell is improved to when can not carry out error detection using preset error detection mechanism, leads to It crosses and the data for being intended to be written so far entity erased cell is encoded using lower code check, this entity erased cell still may be used To be continuing with, without the entity erased cell for being regarded as not using or damaging at once.
It is noted that in the exemplary embodiment of Fig. 5, it is only necessary to which an entity program unit can be complete Store data of the data length no more than the amount of capacity of a logical program unit and the check code corresponding to this data.Example Such as, it is assumed that the amount of capacity of entity program unit 512 (0) is 8KB, as long as then the data length of data 501 is no more than 8KB, Then data 501 can be completely written to entity program unit 512 (0) with the check code corresponding to data 501.In root Data are written according to the second code check and corresponding in another embodiment of the check code of this data, it is assumed that entity program unit The amount of capacity of 512 (0) is 16KB, if then the data length of data 501 be no more than 16KB, then data 501 with corresponding to number It can be completely written to entity program unit 512 (0) according to 501 check code.In addition, the appearance of entity program unit Amount size can also be 32KB or bigger, and without being limited thereto.However, in the exemplary embodiment of Fig. 6 and Fig. 7, to be written The data length of data is constant, but the data length for corresponding to the check code of this data increases, therefore, in certain examples In, even if the data length for the data to be written is not above the amount of capacity of a logical program unit, but this data Data length with corresponding to this data check code data length summation it is possible to can be more than an entity program The amount of capacity of unit.In the case, memory management circuitry 202 would generally use two or more entity programs The check code for changing unit to store data with correspond to this data.That is, being intended to a part (also referred to as first for the data of write-in Part) write-in is to first instance programmed cell, and the another part (also referred to as second part) for being intended to the data of write-in is write Enter to a second instance programmed cell.For example, it is assumed that the amount of capacity of first instance programmed cell is 8KB, then in a model In example embodiment, it is the data of 7KB and corresponding number that first instance programmed cell, which can at most be used to storage data length, It is 980B (that is, 7 × 140 or 14 × 70) check code according to length.If the data length for the data to be written is 8KB, this number It can be written into first instance programmed cell according to first part's data that middle data length is 7KB, and data in this data Length, which is the second part data of 1KB, can then be written into second instance programmed cell.For example, second instance programmed cell Can belong to any one reality that the second class entity erased cell is also belonged in above-mentioned first instance erased cell, memory block 402 Body erased cell or arbitrary entity erased cell, the present invention do not limit.
In an exemplary embodiment, memory management circuitry 202 is using a specific data length as a basic pipe Unit is managed, and is write data into reproducible nonvolatile memorizer module 106 according to this basic management unit.Example Such as, the data length of a basic management unit is 4KB, and without being limited thereto.The amount of capacity of one entity program unit can To be the data length for meeting one or more basic management units.For example, the amount of capacity when entity program unit is 8KB When, the amount of capacity of this entity program unit meets the data length of 2 basic management units.When entity program unit When amount of capacity is 16KB, the amount of capacity of this entity program unit meets the data length of 4 basic management units, with this Analogize.By taking amount of capacity is the entity program unit of 8KB as an example, when the number for being intended to be written the so far data of entity program unit According to an of length no more than basic management unit data length when, memory management circuitry 202 is with a basic management list So far entity program unit is written in this data by position.When the data length for the data to be written is more than a basic management list Position data length and no more than 2 basic management units data length when, memory management circuitry 202 is with two bases So far entity program unit is written in this data by this management unit.
In this exemplary embodiment, it is assumed that the amount of capacity of an entity program unit meets N+1 basic management list The data length of position, wherein N is positive integer.For example, N can be 1,3 or 5, and it is without being limited thereto.When first instance programmed cell When being the second class entity erased cell, whether memory management circuitry 202 can judge the data length for the data to be written more than N The data length of a basic management unit, wherein N are depending on the amount of capacity of first instance programmed cell.For example, when real When the amount of capacity of body programmed cell is 8KB, indicate that the amount of capacity of this entity program unit meets 2 basic management lists The data length of position, therefore N is 1.When the amount of capacity of entity program unit is 16KB, this entity program unit is indicated Amount of capacity meets the data length of 4 basic management units, therefore N is 3, and so on.When first instance erased cell is When two class entity erased cells and the data length for the data to be written are no more than the data length of N number of basic management unit, deposit Reservoir management circuit 202 can be intended to the data of write-in only in accordance with the second code check and the check code corresponding to this data is written to the One entity program unit.Conversely, when first instance erased cell is the second class entity erased cell and the data to be written When data length is more than the data length of N number of basic management unit, memory management circuitry 202 can be intended to write according to the second code check One first part of the data entered and a first part of the check code corresponding to this data are written to first instance sequencing list Member, and the second code check of foundation is intended to one second of a second part of the data of write-in and the check code corresponding to this data Divide write-in to second instance programmed cell.For example, second instance programmed cell can belong to above-mentioned first instance to erase Any one entity erased cell or arbitrary entity that the second class entity erased cell is also belonged in unit, memory block 402 are smeared Except unit, the present invention does not limit.
Fig. 8 shows another example of the present invention embodiment according to the second code check by data and corresponding to the check code of this data It is written to the example schematic of entity program unit.
Please refer to Fig. 8, it is assumed that data 801 are written to logical address the write instruction instruction from host system 1000 410(3).For example, the data length of data 801 is 5KB.Assuming that logical address 410 (3) belongs to logical program unit 810 (0), then memory management circuitry 202 can be by the write-in of data 801 to logical program unit 810 (0).Logical program unit 810 (0) map to entity program unit 812 (0).When the entity erased cell 304 belonging to entity program unit 812 (0) (3) when being the second class entity erased cell, based on the data length of data 801, memory management circuitry 202 can be by data 801 It is divided into data segment 801_1~801_5.For example, the data length of each data segment 801_1~801_5 is 1KB.Inspection and school Positive circuit 256 will produce check code section 802_1~802_5 corresponding to data segment 801_1~801_5.For example, each is verified The data length of code section 802_1~802_5 is 140B.In addition, data 801 can also be in a manner of the exemplary embodiment of Fig. 7 It is divided into more data segments (for example, 10 data lengths are the data segments etc. of 512B), and each check code section Data length can be set to the data length (for example, 70B) of preset check code section, and the present invention does not limit.Storage Device management circuit 202 can judge data 801 data length whether be more than N number of basic management unit data length.Here, false If the amount of capacity of entity program unit 812 (0) is 8KB, therefore N is 1.Memory management circuitry 202 can judge data 801 Data length (for example, 5KB) whether more than a basic management unit data length (for example, 4KB).When the number of data 801 When being more than the data length of a basic management unit according to length, memory management circuitry 202 can be by data segment 801_1~801_ 4 are written with check code section 802_1~802_4 corresponding to data segment 801_1~801_4 to entity program unit 812 (0), And data segment 801_5 and the check code section 802_5 corresponding to data segment 801_5 are written to entity program unit 812 (1), wherein the data length of data segment 801_1~801_4 meets the data length of a basic management unit.Although herein Second instance programmed cell is to also belong to the entity program unit of entity erased cell 304 (3) in exemplary embodiment For 812 (1), still, in another exemplary embodiment, second instance programmed cell can also be to belong in memory block 402 Also belong to any one entity erased cell of the second class entity erased cell or arbitrary entity erased cell.That is, After by the write-in to entity program unit 812 (0) and 812 (1) of data 801, logical program unit 810 (0) is mapping To entity program unit 812 (0) and 812 (1).If in addition, the amount of capacity of entity program unit 812 (0) be 16KB or Person is more, then only needs N being set as 3 or corresponding numerical value.
In addition, in the exemplary embodiment of Fig. 5 to Fig. 8, when memory management circuitry 202 is by data segment and check code section When write-in is to first instance programmed cell, one or more the first inactive bits can be written together for memory management circuitry 202 To not writing full part by data segment and check code section in first instance programmed cell.Similarly, when memory management electricity When being written data segment and check code section to second instance programmed cell, memory management circuitry 202 can together will on road 202 One or more second inactive bits are written into second instance programmed cell does not write full portion by data segment and check code section Point.First inactive bit and the second inactive bit can be arbitrary invalid data.
Fig. 9 shows the flow chart of the method for writing data of one example of the present invention embodiment.
Fig. 9 is please referred to, in step S902, receives write instruction, wherein this write instruction instruction writes data at most At least one in a logic unit, wherein at least one in the logic unit maps to first instance program Change unit, and first instance programmed cell belongs to first instance erased cell.
In step S904, judge that first instance erased cell is that first kind entity erased cell or the second class entity are erased Unit.
When first instance erased cell is first kind entity erased cell, in step S906, come according to the first code check This data and the check code corresponding to this data are programmed into so far first instance programmed cell.
When first instance erased cell is the second class entity erased cell, in step S908, come according to the second code check By this data, so far first instance programmed cell, wherein this first code check are higher than with this check code programming corresponding to this data This second code check.
Figure 10 shows the flow chart of the method for writing data of another example of the present invention embodiment.
Please refer to Figure 10, in step S1002, receive write instruction, wherein this write instruction instruction write data into At least one in multiple logic units, wherein at least one in the logic unit maps to first instance journey Sequence unit, and first instance programmed cell belongs to first instance erased cell.
In step S1004, judge that first instance erased cell is that first kind entity erased cell or the second class entity are smeared Except unit.
When first instance erased cell is first kind entity erased cell, in step S1006, come according to the first code check So far first instance programmed cell is written into this data and the check code corresponding to this data.
When first instance erased cell is the second class entity erased cell, in step S1008, the number of this data is judged According to length whether be more than N number of basic management unit data length, wherein N is positive integer, and N+1 basic management unit Data length is equal to the amount of capacity of first instance programmed cell.
When the data length of this data is not above the data length of N number of basic management unit, in step S1010, This data and the check code corresponding to this data are written to first instance programmed cell only in accordance with the second code check.
When the data length of this data is more than the data length of N number of basic management unit, in step S1012, foundation This check code of this data of first part and first part is written to first instance programmed cell and is incited somebody to action by the second code check This data of second part and this check code of second part are written to second instance programmed cell.
However, each step has been described in detail as above in Fig. 9 and Figure 10, just do not repeating herein.It is worth noting that, Fig. 9 It can be implemented as multiple procedure codes or circuit with each step in Figure 10, the present invention is simultaneously not subject to the limits.In addition, Fig. 9 and Figure 10 Method can arrange in pairs or groups above example use, can also be used alone, the present invention is simultaneously not subject to the limits.In particular, in this example reality It applies in example, write-in or reading of data and/or check code performed by memory management circuitry 202 etc. are non-easily for duplicative The various operations of the property lost memory module 106, e.g. by sending an at least command serial (command sequence) extremely Reproducible nonvolatile memorizer module 106 is completed, and wherein each command serial includes at least one instruction.It can make carbon copies Formula non-volatile memory module 106 can execute corresponding operation according to received command serial.
In addition, in another exemplary embodiment, above-mentioned judgment step can also be applied to entity program unit or entity Fan.For example, can judge that first instance programmed cell is first kind reality according to the mode referred in above-mentioned each exemplary embodiment Body programmed cell or the second class entity program unit, and determined according to the first code check or second code according to judging result Data are written with corresponding check code to first instance programmed cell rate.In particular, in the same entity erased cell Different entity program units or entity fan may also have different bit error rates, and therefore, such practice may be more The memory behaviour in service of closing to reality.
In conclusion method for writing data proposed by the present invention, memory storage apparatus and memorizer control circuit unit, Can be first kind entity erased cell or the second class according to the entity erased cell in reproducible nonvolatile memorizer module Entity erased cell, and adaptively according to the first code check or higher than the first code check the second code check come by data with correspond to this The check code write-in of data is so far in entity erased cell.Thereby, even if the bit error rate of a certain entity erased cell is more than Preset permissible range, this entity erased cell still can be used for a prolonged period, without being directly rejected.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (24)

1. a kind of method for writing data, for controlling a reproducible nonvolatile memorizer module, the duplicative is non-volatile Property memory module includes multiple entity erased cells, and each of entity erased cell includes multiple entity program units, It is characterized in that, and the method for writing data include：
Receive a write instruction, wherein write instruction instruction by a data be written into multiple logic units at least within it One, wherein in those logic units this at least one map to the first instance journey in those entity program units Sequence unit, and the first instance programmed cell belongs to the first instance erased cell in those entity erased cells；
Judge that the first instance erased cell belongs to a first kind entity erased cell or one second class entity erased cell；
When the first instance erased cell belongs to the first kind entity erased cell, according to one first code check by the data with It is programmed to the first instance programmed cell corresponding to a check code of the data；And
When the first instance erased cell belongs to the second class entity erased cell, according to one second code check by the data with It is programmed to the first instance programmed cell corresponding to the check code of the data, wherein first code check is higher than the second code Rate,
The data and the check code corresponding to the data are wherein programmed to the first instance program according to second code check Change unit the step of include：
When the data length of the data is no more than the data length of N number of basic management unit, according to second code check by the number It is programmed to the first instance programmed cell according to the check code corresponding to the data；And
It, will according to second code check when the data length of the data is more than the data length of N number of basic management unit The data of one first part and the check code of a first part are programmed to the first instance programmed cell and by one the The data of two parts are programmed to the second instance journey in those entity program units with the check code of a second part Sequence unit.
2. method for writing data according to claim 1, which is characterized in that judge that the first instance erased cell belongs to this The step of first kind entity erased cell or the second class entity erased cell includes：
Judge whether a bit error rate assessed value of the first instance erased cell meets a Sharp criteria；
If the bit error rate assessed value of the first instance erased cell does not meet the Sharp criteria, judge that the first instance is smeared Except unit belongs to the first kind entity erased cell；And
If the bit error rate assessed value of the first instance erased cell meets the Sharp criteria, judge that the first instance is erased Unit belongs to the second class entity erased cell.
3. method for writing data according to claim 2, which is characterized in that further include：
It erases a number information, write-in number information, a reading times information, one wrong according to the one of the first instance erased cell Errored bit number information, a wrong bitrate information, a data resting period information and a temperature information at least one or At least combination, to determine the bit error rate assessed value of the first instance erased cell.
4. method for writing data according to claim 1, which is characterized in that
The data and the check code corresponding to the data are programmed to the first instance sequencing list according to first code check Member step include：
The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,
The data and the check code corresponding to the data are wherein programmed to the first instance program according to second code check Change unit the step of include：
The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,
One data length of wherein each at least one first data segment is identical to a number of each at least one second data segment It is shorter than each at least one second check code section according to a data length of length, and each at least one first check code section One data length.
5. method for writing data according to claim 1, which is characterized in that
The data and the check code corresponding to the data are programmed to the first instance sequencing list according to first code check Member step include：
The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,
The data and the check code corresponding to the data are wherein programmed to the first instance program according to second code check Change unit the step of include：
The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,
One data length of wherein each at least one first data segment is longer than a data of each at least one second data segment Length, and a data length of each at least one first check code section is identical to each at least one second check code section One data length.
6. method for writing data according to claim 1, which is characterized in that according to second code check by the data with it is right Should include the step of the check code of the data is programmed to the first instance programmed cell：
Judge the data the data length whether be more than N number of basic management unit the data length, wherein N is just whole Number, and a data length of N+1 basic management unit is equal to an amount of capacity of the first instance programmed cell.
7. method for writing data according to claim 6, which is characterized in that the second instance programmed cell belong to this The second instance that the second class entity erased cell is also belonged in one entity erased cell or those entity erased cells is smeared Except unit.
8. method for writing data according to claim 5, which is characterized in that a data of the data of the first part are long Degree meets the data length of N number of basic management unit, and the method for writing data further includes：
At least one first inactive bit is programmed in the first instance programmed cell to fill up not being somebody's turn to do by the first part Data and the check code of the first part write full part；And
At least one second inactive bit is programmed in the second instance programmed cell to fill up not being somebody's turn to do by the second part Data and the check code of the second part write full part.
9. a kind of memory storage apparatus, which is characterized in that including：
One connecting interface unit, to be electrically connected to a host system；
One reproducible nonvolatile memorizer module, including multiple entity erased cells, and each of entity is erased list Member includes multiple entity program units；And
One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould Block,
To receive a write instruction, one data are written the wherein memorizer control circuit unit for wherein write instruction instruction To at least one of multiple logic units, wherein in those logic units this at least one map to those entities A first instance programmed cell in programmed cell, and the first instance programmed cell belongs to those entities and erases list A first instance erased cell in member,
The memorizer control circuit unit is also judging that the first instance erased cell belongs to a first kind entity erased cell Or one second class entity erased cell, wherein one first bit error rate of the first kind entity erased cell are less than second class One second bit error rate of entity erased cell,
When the first instance erased cell belongs to the first kind entity erased cell, the memorizer control circuit unit also to The data and the check code corresponding to the data are programmed to the first instance programmed cell according to one first code check,
When the first instance erased cell belongs to the second class entity erased cell, the memorizer control circuit unit also to The data and the check code corresponding to the data are programmed to the first instance programmed cell according to one second code check, In first code check be higher than second code check,
Wherein the memorizer control circuit unit according to second code check by the data with corresponding to the data the check code The operation for being programmed to the first instance programmed cell includes：
When the data length of the data is no more than the data length of N number of basic management unit, according to second code check by the number It is programmed to the first instance programmed cell according to the check code corresponding to the data；And
It, will according to second code check when the data length of the data is more than the data length of N number of basic management unit The data of one first part and the check code of a first part are programmed to the first instance programmed cell and by one the The data of two parts are programmed to the second instance journey in those entity program units with the check code of a second part Sequence unit.
10. memory storage apparatus according to claim 9, which is characterized in that the memorizer control circuit unit judges The first instance erased cell belongs to the first kind entity erased cell or the operation of the second class entity erased cell includes：
Judge whether a bit error rate assessed value of the first instance erased cell meets a Sharp criteria；
If the bit error rate assessed value of the first instance erased cell does not meet the Sharp criteria, judge that the first instance is smeared Except unit belongs to the first kind entity erased cell；And
If the bit error rate assessed value of the first instance erased cell meets the Sharp criteria, judge that the first instance is erased Unit belongs to the second class entity erased cell.
11. memory storage apparatus according to claim 10, which is characterized in that the memorizer control circuit unit is also used With according to the one of the first instance erased cell erase number information, one write-in number information, a reading times information, a mistake Bit number information, a wrong bitrate information, a data resting period information and a temperature information at least one or extremely Few combination, to determine the bit error rate assessed value of the first instance erased cell.
12. memory storage apparatus according to claim 9, which is characterized in that
The memorizer control circuit unit programs the data and the check code corresponding to the data according to first code check Operation to the first instance programmed cell includes：
The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,
Wherein the memorizer control circuit unit according to second code check by the data with corresponding to the data the check code The operation for being programmed to the first instance programmed cell includes：
The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,
One data length of wherein each at least one first data segment is identical to a number of each at least one second data segment It is shorter than each at least one second check code section according to a data length of length, and each at least one first check code section One data length.
13. memory storage apparatus according to claim 9, which is characterized in that
The memorizer control circuit unit programs the data and the check code corresponding to the data according to first code check Operation to the first instance programmed cell includes：
The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,
Wherein the memorizer control circuit unit according to second code check by the data with corresponding to the data the check code The operation for being programmed to the first instance programmed cell includes：
The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,
One data length of wherein each at least one first data segment is longer than a data of each at least one second data segment Length, and a data length of each at least one first check code section is identical to each at least one second check code section One data length.
14. memory storage apparatus according to claim 9, which is characterized in that the memorizer control circuit unit foundation The data are programmed to the operation of the first instance programmed cell by second code check with the check code corresponding to the data Including：
Judge the data the data length whether be more than N number of basic management unit the data length, wherein N is just whole Number, and a data length of N+1 basic management unit is equal to an amount of capacity of the first instance programmed cell.
15. memory storage apparatus according to claim 14, which is characterized in that the second instance programmed cell belongs to One second that the second class entity erased cell is also belonged in the first instance erased cell or those entity erased cells is real Body erased cell.
16. memory storage apparatus according to claim 14, which is characterized in that a number of the data of the first part Meet the data length of N number of basic management unit according to length,
The memorizer control circuit unit will be also being at least programmed to the first instance programmed cell by one first inactive bit In full part write with the check code for filling up the not data by the first part and the first part,
The memorizer control circuit unit will be also being at least programmed to the second instance programmed cell by one second inactive bit In full part write with the check code for filling up the not data by the second part and the second part.
17. a kind of memorizer control circuit unit, which is characterized in that for controlling a type nonvolatile mould Block, the wherein reproducible nonvolatile memorizer module include multiple entity erased cells, each of entity erased cell Including multiple entity program units, and the memorizer control circuit unit includes：
One host interface, to be electrically connected to a host system；
One memory interface, to be electrically connected to the reproducible nonvolatile memorizer module；
One error checking and correcting circuit；And
One memory management circuitry is electrically connected to the host interface, the memory interface and the error checking and correcting circuit,
To receive a write instruction, one data are written at most the wherein memory management circuitry for wherein write instruction instruction At least one in a logic unit, wherein in those logic units this at least one map to those entity journeys A first instance programmed cell in sequence unit, and the first instance programmed cell belongs to those entity erased cells In a first instance erased cell,
The memorizer control circuit unit is also judging that the first instance erased cell belongs to a first kind entity erased cell Or one second class entity erased cell, wherein one first bit error rate of the first kind entity erased cell are less than second class One second bit error rate of entity erased cell,
When the first instance erased cell belongs to the first kind entity erased cell, the memory management circuitry is also sending The instruction of one first command serial, wherein first command serial is according to one first code check by the data and corresponding to the one of the data Check code is programmed to the first instance programmed cell,
When the first instance erased cell belongs to the second class entity erased cell, the memory management circuitry is also sending The instruction of one second command serial, wherein second command serial by the data and corresponds to being somebody's turn to do for the data according to one second code check Check code is programmed to the first instance programmed cell, and wherein first code check is higher than second code check,
The operation that the memory management circuitry sends second command serial includes：
When the data length of the data is no more than the data length of N number of basic management unit, second command serial is sent, In second command serial instruction according to second code check and only the data are programmed to the check code for corresponding to the data The first instance programmed cell,
When the data length of the data is more than the data length of N number of basic management unit, second strings of commands is sent The instruction of row, wherein second command serial is according to second code check by the school of the data of a first part and a first part It tests code and is programmed to the first instance programmed cell and by the check code of the data of a second part and a second part The second instance programmed cell being programmed in those entity program units.
18. memorizer control circuit unit according to claim 17, which is characterized in that the memory management circuitry judges The first instance erased cell belongs to the first kind entity erased cell or the operation of the second class entity erased cell includes：
Judge whether a bit error rate assessed value of the first instance erased cell meets a Sharp criteria；
If the bit error rate assessed value of the first instance erased cell does not meet the Sharp criteria, judge that the first instance is smeared Except unit belongs to the first kind entity erased cell；And
If the bit error rate assessed value of the first instance erased cell meets the Sharp criteria, judge that the first instance is erased Unit belongs to the second class entity erased cell.
19. memorizer control circuit unit according to claim 18, which is characterized in that the memory management circuitry is also used With according to the one of the first instance erased cell erase number information, one write-in number information, a reading times information, a mistake Bit number information, a wrong bitrate information, a data resting period information and a temperature information at least one or extremely Few combination, to determine the bit error rate assessed value of the first instance erased cell.
20. memorizer control circuit unit according to claim 17, which is characterized in that
The operation that the memory management circuitry sends first command serial further includes：
The data are divided at least one first data segment and control the error checking and generate at least one first school with correcting circuit Code section is tested, wherein each at least one first check code section corresponds at least one of one first data segment,
The operation that wherein memory management circuitry sends second command serial further includes：
The data are divided at least one second data segment and control the error checking and generate at least one second school with correcting circuit Code section is tested, wherein each at least one second check code section corresponds at least one of one second data segment,
One data length of wherein each at least one first data segment is identical to a number of each at least one second data segment It is shorter than each at least one second check code section according to a data length of length, and each at least one first check code section One data length.
21. memorizer control circuit unit according to claim 17, which is characterized in that
The operation that the memory management circuitry sends first command serial further includes：
The data are divided at least one first data segment and control the error checking and generate at least one first school with correcting circuit Code section is tested, wherein each at least one first check code section corresponds at least one of one first data segment,
The operation that wherein memory management circuitry sends second command serial further includes：
The data are divided at least one second data segment and control the error checking and generate at least one second school with correcting circuit Code section is tested, wherein each at least one second check code section corresponds at least one of one second data segment,
One data length of wherein each at least one first data segment is longer than a data of each at least one second data segment Length, and a data length of each at least one first check code section is identical to each at least one second check code section One data length.
22. memorizer control circuit unit according to claim 17, which is characterized in that the memory management circuitry is sent The operation of second command serial includes：
Judge the data the data length whether be more than N number of basic management unit the data length, wherein N is just whole Number, and a data length of N+1 basic management unit is equal to an amount of capacity of the first instance programmed cell.
23. memorizer control circuit unit according to claim 22, which is characterized in that the second instance programmed cell Belong to and also belongs to the one of the second class entity erased cell in the first instance erased cell or those entity erased cells Two entity erased cells.
24. memorizer control circuit unit according to claim 22, which is characterized in that the data of the first part One data length meets the data length of N number of basic management unit,
Second command serial also indicate at least one first inactive bit need to be programmed in the first instance programmed cell with It fills up not data by the first part and the check code of the first part writes full part, and at least one second nothing Effect is programmed in the second instance programmed cell than special procuring to fill up not data by the second part and this second The check code divided writes full part.
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