CN106843744B

CN106843744B - Data programming method and memory storage device

Info

Publication number: CN106843744B
Application number: CN201510881474.6A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2015-12-03
Filing date: 2015-12-03
Publication date: 2020-05-26
Anticipated expiration: 2035-12-03
Also published as: CN106843744A

Abstract

The invention provides a data programming method and a memory storage device. The method comprises the following steps: programming a plurality of first type entity units in the rewritable nonvolatile memory module to store first data; encoding the first data to produce encoded data; receiving second data; and after the first data is coded, programming at least one of a plurality of second type entity units corresponding to the first type entity unit in the rewritable nonvolatile memory module to store at least one part of second data. The invention can improve the correction capability of errors in paired entity units in a multi-channel programming procedure.

Description

Data programming method and memory storage device

Technical Field

The present invention relates to a memory management mechanism, and more particularly, to a data programming method and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

As the performance of memory chips continues to increase, some memory devices support multi-channel (multi-channel) access. However, although the data access efficiency can be improved by increasing the number of channels that can be accessed in parallel, if the amount of data written in parallel at a time is too large or the number of channels used is too large, the data that is stored in the memory may be too erroneous to be completely corrected. In particular, data belonging to a pair of pages (page) in the memory is most likely to affect data in a lower page (lower page) by programming an upper page (upper page). Conventionally, dummy data can be padded to the corresponding upper page at the same time as programming the lower page, thereby protecting the data in the entire pair of pages. However, such a mechanism also results in a waste of storage space. Therefore, how to maintain the correctness of the data belonging to the paired pages in the memory device supporting the multi-channel access is one of the issues to be studied by those skilled in the art.

Disclosure of Invention

An exemplary embodiment of the present invention provides a data programming method and a memory storage device, which can maintain the correctness of data belonging to paired physical cells in a multi-channel programming procedure by using encoded data with limited error correction capability.

An exemplary embodiment of the present invention provides a data programming method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, wherein the entity units are corresponding to a plurality of channels, wherein the entity units include a plurality of first type entity units and a plurality of second type entity units corresponding to the first type entity units, the data programming method including: programming a plurality of physical units in the first type of physical units to store first data; encoding the first data to produce encoded data; receiving second data; and after encoding the first data, programming at least one entity unit in the second class of entity units to store at least a part of the second data.

In an exemplary embodiment of the present invention, the encoded data is used to correct errors in the physical cells storing the first data caused by programming the physical cells in the second type of physical cells.

In an exemplary embodiment of the present invention, the step of programming the physical cells in the second type of physical cells includes: executing a first programming procedure to store a first portion of the second data, wherein the first programming procedure includes programming physical units of a first portion of the physical units of the second type via at least one first channel of the channels, wherein the physical units of the first portion of the physical units of the second type correspond to physical units of a first portion of the physical units to store the first data, wherein a first number of the first channels is less than a total number of available channels of the channels; and after executing the first programming procedure, executing a second programming procedure to store a second portion of the second data, wherein the second programming procedure includes programming a second portion of the physical units of the second class of physical units via at least one second channel of the channels, wherein the second portion of the physical units of the second class of physical units corresponds to a second portion of the physical units used to store the first data, wherein a second number of the second channel is less than the total number of the available channels.

In an example embodiment of the present invention, the available channel refers to a plurality of channels that can be used in parallel by default corresponding to the second data among the channels when the second data is received.

In an exemplary embodiment of the present invention, the encoded data is used to correct a first error in data stored in a first part of the physical units for storing the first data or a second error in data stored in a second part of the physical units for storing the first data, wherein a total number of error bits of the first error is smaller than or equal to a maximum value of a total number of error bits that can be corrected by the encoded data, and wherein a total number of error bits of the second error is smaller than or equal to the maximum value of the total number of error bits that can be corrected by the encoded data.

In an exemplary embodiment of the present invention, the first error is generated corresponding to the first program, and the second error is generated corresponding to the second program.

In an exemplary embodiment of the present invention, the step of encoding the first data to generate the encoded data includes: encoding a first portion of the first data to generate first encoded data, wherein the first portion of the first data is data of the first data stored in a plurality of physical units of the first type corresponding to at least a third one of the channels; and encoding a second part of the first data to generate second encoded data, wherein the second part of the first data is stored in a plurality of physical units of the first type of physical units corresponding to at least a fourth channel of the channels, and the first encoded data and the second encoded data are independent of each other.

In an exemplary embodiment of the present invention, the data programming method further includes: and judging whether a specific operation instruction is received, wherein the step of encoding the first data is executed in response to the specific operation instruction being received.

In an exemplary embodiment of the present invention, the specific operation instruction includes a flush clear instruction.

In an exemplary embodiment of the present invention, the data programming method further includes: if the specific operation instruction is not received, the first data is not encoded before the entity unit in the second type entity unit is programmed.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units, wherein the entity units are corresponding to a plurality of channels, and the entity units comprise a plurality of first-type entity units and a plurality of second-type entity units corresponding to the first-type entity units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is configured to send a first write command sequence to instruct programming of a plurality of physical units of the first type of physical units to store first data, wherein the memory control circuit unit is further configured to encode the first data to generate encoded data, wherein the memory control circuit unit is further configured to receive second data, and wherein after encoding the first data, the memory control circuit unit is further configured to send a second write command sequence to instruct programming of at least one physical unit of the second type of physical units to store at least a portion of the second data.

In an exemplary embodiment of the invention, the second write command sequence instructs to execute a first programming procedure to store a first portion of the second data and to execute a second programming procedure to store a second portion of the second data after executing the first programming procedure, wherein the first programming procedure includes programming physical cells of a first portion of the second type of physical cells via at least one first channel of the channels, wherein the physical cells of the first portion of the second type of physical cells correspond to the physical cells of the first portion of the physical cells to store the first data, wherein a first number of the first channels is smaller than a total number of available channels of the channels, wherein the second programming procedure includes programming physical cells of a second portion of the second type of physical cells via at least one second channel of the channels, wherein a second number of the second portion of the physical units in the second class of physical units corresponds to a second portion of the physical units used to store the first data, wherein the second number of the second channels is less than the total number of the available channels.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit encoding the first data to generate the encoded data includes: encoding a first portion of the first data to generate first encoded data, wherein the first portion of the first data is data of the first data stored in a plurality of physical units of the first type corresponding to at least a third one of the channels; and encoding a second part of the first data to generate second encoded data, wherein the second part of the first data is stored in a plurality of physical units of the first type of physical units corresponding to at least a fourth channel of the channels, and the first encoded data and the second encoded data are independent of each other.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to determine whether a specific operation command is received, wherein the memory control circuit unit performs an operation of encoding the first data in response to receiving the specific operation command.

In an exemplary embodiment of the invention, if the specific operation command is not received, the memory control circuit unit does not encode the first data before programming the physical cells in the second type of physical cells.

Another exemplary embodiment of the present invention provides a data programming method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, wherein the entity units are corresponding to a plurality of channels, wherein the entity units include a plurality of first type entity units and a plurality of second type entity units corresponding to the first type entity units, the data programming method including: programming a plurality of physical units in the first type of physical units to store first data; receiving second data; after storing the first data, performing a first programming procedure to store a first portion of the second data, wherein the first programming procedure includes programming a first portion of the physical units of the second class of physical units via at least one first channel of the channels, wherein the first portion of the physical units of the second class of physical units corresponds to a first portion of the physical units used to store the first data, wherein a first number of the first channels is less than a total number of available channels of the channels; and after executing the first programming procedure, executing a second programming procedure to store a second portion of the second data, wherein the second programming procedure includes programming a second portion of the physical units of the second class of physical units via at least one second channel of the channels, wherein the second portion of the physical units of the second class of physical units corresponds to a second portion of the physical units used to store the first data, wherein a second number of the second channel is less than the total number of the available channels.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units, wherein the entity units are corresponding to a plurality of channels, and the entity units comprise a plurality of first-type entity units and a plurality of second-type entity units corresponding to the first-type entity units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is configured to send a first write command sequence to instruct a plurality of entity units in the first type of entity units to be programmed to store first data, wherein the memory control circuit unit is further configured to receive second data, wherein after storing the first data, the memory control circuit unit is further configured to send a second write command sequence to instruct a first programming program to be executed to store a first part of the second data and after executing the first programming program, execute a second programming program to store a second part of the second data, wherein the first programming program comprises entity units of a first part of the second type of entity units programmed through at least one first channel of the channels, wherein the first portion of the physical units of the second class of physical units corresponds to a first portion of the physical units for storing the first data, wherein the first number of the first channels is less than a total number of available ones of the channels, wherein the second programming procedure comprises programming a second portion of the physical units of the second class via at least a second one of the channels, wherein the second portion of the physical units of the second class corresponds to a second portion of the physical units for storing the first data, wherein the second number of the second channels is less than the total number of the available channels.

Based on the above, the first data stored in the first type entity units corresponding to the plurality of channels is encoded. Therefore, when the multichannel programming procedure for the corresponding second type entity unit is executed, the correctness of the data belonging to the paired entity units can be maintained.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5A is a schematic diagram illustrating an array of memory cells according to an exemplary embodiment of the present invention;

FIG. 5B is a schematic diagram of an array of memory cells according to another exemplary embodiment of the invention;

FIG. 6A is a diagram illustrating a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

FIG. 6B is a diagram illustrating the use of physical elements in accordance with an exemplary embodiment of the present invention;

FIG. 7 is a schematic block diagram illustrating memory control circuitry in accordance with an exemplary embodiment of the present invention;

FIG. 8 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating programming of a first type of physical unit and encoding of first data according to an example embodiment of the invention;

FIG. 10 is a schematic diagram illustrating programming of a second type of physical unit according to an exemplary embodiment of the present invention;

FIGS. 11 and 12 are schematic diagrams illustrating a data programming procedure according to an exemplary embodiment of the present invention;

FIG. 13 is a schematic diagram illustrating a data programming procedure according to another exemplary embodiment of the present invention;

FIG. 14 is a flowchart illustrating a data programming method according to an exemplary embodiment of the present invention;

FIG. 15 is a flowchart illustrating a data programming method according to another exemplary embodiment of the present invention;

FIG. 16 is a flowchart illustrating a data programming method according to another exemplary embodiment of the present invention;

fig. 17 is a flowchart illustrating a data programming method according to another exemplary embodiment of the present invention.

Reference numerals:

10. 30: memory storage device

11. 31: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main board

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network adapter

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded storage device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

510: memory cell array

502. 522: memory cell

504. 524: bit line

506: character line

508: shared source line

512: select gate drain transistor

514: selective gate source transistor

524(1) to 524 (4): bit line group

526(1) to 526 (8): character line layer

601(1) to 601 (M): memory plane

602(1) -602 (M): channel with a plurality of channels

610(0) to 610(a), 610(B) to 610(C), 610(D) to 610(E), 810(0) to 810 (E): entity unit of the first kind

620(0) to 620(a), 620(B) to 620(C), 620(D) to 620 (E): entity unit of the second kind

702: memory management circuit

704: host interface

706: memory interface

708: error checking and correcting circuit

710: buffer memory

712: power management circuit

801(1) -810 (r): position of

820. 902, 1102(0), 1102(1), 1310(0), 1310 (1): encoding data

1001. 1002, 1201, 1301(0), 1301(1), 1302(0), 1302 (1): programmed program

S1401: step (programming a plurality of physical units of the first type of physical units to store the first data)

S1402: step (encoding the first data to generate encoded data and receiving the second data)

S1403: step (programming at least one entity unit of a plurality of entity units of a second type corresponding to the entity unit of the first type to store at least a part of the second data)

S1501: step (programming a plurality of physical units of the first type of physical units to store the first data)

S1502: step (encoding the first data to generate encoded data and receiving the second data)

S1503: step (executing a first programming procedure to store a first portion of data of a second portion of data, wherein the first programming procedure includes programming a first portion of the second type of physical units via at least one first channel, wherein the first portion of the second type of physical units corresponds to a first portion of the first type of physical units storing the first data, wherein a first number of the first channel is less than a total number of the plurality of available channels)

S1504: step (executing a second programming procedure to store a second portion of the second data, wherein the second programming procedure includes programming a second portion of the second plurality of physical units via at least one second channel, wherein the second portion of the second plurality of physical units corresponds to a second portion of the first plurality of physical units storing the first data, wherein a second number of the second channel is less than the total number of the available channels)

S1601: step (programming a plurality of physical units of the first type of physical units to store the first data)

S1602: step (encoding a first portion of the first data stored in a plurality of physical units of the first type corresponding to the at least one third channel to generate first encoded data)

S1603: step (encoding a second portion of the first data stored in a plurality of physical units of the first type corresponding to at least a fourth channel to generate second encoded data, wherein the first encoded data and the second encoded data are independent of each other)

S1604: step (programming at least one entity unit of a plurality of entity units of a second type corresponding to the entity unit of the first type to store at least a part of the second data)

S1701: step (programming a plurality of physical units of the first type of physical units to store the first data)

S1702: step (judging whether a specific operation instruction is received)

S1703: step (encoding the first data to generate encoded data)

S1704: step (programming at least one entity unit of a plurality of entity units of a second type corresponding to the entity unit of the first type to store at least a part of the second data)

Detailed Description

Generally, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 can store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 can be electrically connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 can be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon) based on various wireless communication technologies. The motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-chip package storage devices (eMCP) 342 to electrically connect the memory module directly to the embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-P Package) interface standard, the Multi-Media storage Card (Multi-Media storage Card, Multimedia storage Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The following describes the memory cell arrays in different exemplary embodiments with two-dimensional arrays and three-dimensional arrays, respectively. It is noted, however, that the following exemplary embodiments are only examples of memory cell arrays, and in other exemplary embodiments, the arrangement of the memory cell arrays may be adjusted to meet practical requirements.

FIG. 5A is a schematic diagram of an array of memory cells according to an exemplary embodiment of the invention.

Referring to fig. 5A, a memory cell array 510 includes a plurality of memory cells 502 for storing data, a plurality of Select Gate Drain (SGD) transistors 512 and a plurality of Select Gate Source (SGS) transistors 514, and a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 connecting the memory cells. Memory cells 502 are arranged in an array at the intersections of bit lines 504 and word lines 506.

FIG. 5B is a schematic diagram of an array of memory cells according to another exemplary embodiment of the invention.

Referring to FIG. 5B, in the present exemplary embodiment, the memory cell array includes a plurality of memory cells 522 for storing data, a plurality of bit line sets 524(1) -524 (4), and a plurality of word line layers 526(1) -526 (8). The sets of bits 524(1) -524 (4) are independent of each other (e.g., are separated from each other) and are arranged along a first direction (e.g., the X-axis). Each of the sets of bit lines 524(1) -524 (4) includes a plurality of bit lines 524 that are independent of (e.g., separate from) each other. The bit lines 524 included in the bit line groups 524(1) -524 (4) are arranged along a third direction (e.g., Y-axis) and extend toward a second direction (e.g., Z-axis). The word line layers 526(1) -526 (8) are independent of each other (e.g., separate from each other) and stacked in the second direction. In the exemplary embodiment, each of the word line layers 526(1) - (526), (8) may be considered a word line plane. Memory cell 522 is disposed at each intersection between each bit line 524 and word line layer 526(1) -526 (8) in bit line groups 524(1) -524 (4). However, in another exemplary embodiment, a group of bit lines may include more or fewer bit lines, and a word line layer may pass more or fewer groups of bit lines.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits based on a change in voltage (hereinafter also referred to as threshold voltage). When a write command sequence or a read command sequence is received from the memory control circuit unit 404, a control circuit (not shown) in the rewritable nonvolatile memory module 406 controls voltages applied to a word line (or a word line layer) and a bit line (or a bit line group) to change a threshold voltage of at least one memory cell or detect a storage state (state) of the memory cell. For example, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage (or programming voltage) to the control gate of a memory cell, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, the memory cells in the rewritable nonvolatile memory module 406 can have multiple storage states. The read voltage is applied to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

The memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming units, and the physical programming units form a plurality of physical erasing units. Specifically, memory cells on the same word line or the same word line layer constitute one or more physical program units. For example, if the rewritable nonvolatile memory module 406 is an MLC NAND flash memory module, the memory cells at the intersections of the same word line (or word line layer) and multiple bit lines constitute 2 physical programming units. Alternatively, if the rewritable nonvolatile memory module 406 is a TLC NAND flash memory module, the memory cells on the intersection of the same word line (or word line layer) and multiple bit lines constitute 3 physical programming units.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or more or less physical fans may be included in the data bit region, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of erased memory cells. For example, the physical erase unit is a physical block (block).

In an exemplary embodiment where a memory cell can store multiple bits (e.g., MLC or TLC NAND flash memory module), physical program cells belonging to the same word line (or the same word line layer) can be categorized into at least a first type of physical program cell and a second type of physical program cell. For example, in an MLC NAND flash memory module, the Least Significant Bit (LSB) of a memory cell belongs to the first type of physical program unit, and the Most Significant Bit (MSB) of the memory cell belongs to the second type of physical program unit. Generally, the writing speed of the first type of physical program cells is faster than that of the second type of physical program cells. In addition, the reliability of the first type of physical program cells is generally higher than that of the second type of physical program cells. In an example embodiment, the first type of physical programming unit is also referred to as a fast page (fast page) or a lower physical programming unit, and the second type of physical programming unit is also referred to as a slow page (slow page) or an upper physical programming unit.

In the exemplary embodiment, the rewritable nonvolatile memory module 406 has a plurality of memory planes (planes). Such memory planes belong to one or more memory dies (die). In the exemplary embodiment, one memory plane is programmed as one device. However, in another exemplary embodiment, a plurality of memory planes may be programmed as one device. Each memory plane may include one or more arrays of memory cells. For example, each memory cell array may be the memory cell array 510 of FIG. 5A, the memory cell array of FIG. 5B, or other types of memory cell arrays.

FIG. 6A is a diagram illustrating a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. It should be noted that the example embodiment is exemplified by MLC NAND flash, but the related operations can also be applied to other types of flash (e.g. TLC NAND flash).

Referring to FIG. 6A, the rewritable nonvolatile memory module 406 includes M memory planes 601(1) -601 (M). Each of the memory planes 601(1) -601 (M) includes a plurality of memory cells. In the memory planes 601(1) -601 (M), the memory cells belonging to the same memory plane are programmed into a plurality of physical units. For example, the physical units belonging to the same memory plane include a plurality of first type physical units and a plurality of second type physical units corresponding to the first type physical units. For example, the memory plane 601(1) includes first type entity units 610(0) -610 (a) and second type entity units 620(0) -620 (a), and the memory plane 601(2) includes first type entity units 610(B) -610 (C) and second type entity units 620(B) -620 (C); by analogy, the memory plane 601(M) includes first type entity units 610(D) -610 (E) and second type entity units 620(D) -620 (E). Wherein, the first type entity unit 610(0) corresponds to the second type entity unit 620(0), and the first type entity unit 610(1) corresponds to the second type entity unit 620 (1); by analogy, the first type entity element 610(E) corresponds to the second type entity element 620 (E).

In the present exemplary embodiment, the physical unit refers to a physical programming unit. Thus, the first type entity unit is referred to as the first type entity programming unit, and the second type entity unit is referred to as the second type entity programming unit. In addition, a first type entity unit and a second type entity unit corresponding to each other refer to entity units belonging to the same word line (or the same word line layer). For example, the first type entity unit 610(0) and the second type entity unit 620(0) belong to the same word line (or the same word line layer), and the first type entity unit 610(1) and the second type entity unit 620(1) belong to the same word line (or the same word line layer); by analogy, the first type entity unit 610(E) and the second type entity unit 620(E) belong to the same word line (or the same word line layer). However, in another exemplary embodiment, a physical unit may be formed by any number of memory cells on the same bit line (or bit line layer).

In the exemplary embodiment, among a set of corresponding physical units, the first type of physical unit is used (e.g., programmed) first; the second type of physical unit is then used (e.g., programmed).

FIG. 6B is a diagram illustrating the use of physical units according to an exemplary embodiment of the present invention.

Referring to fig. 6B, taking the memory plane 601(1) in fig. 6A as an example, the numbers 1 to 12 represent the use sequence (or programming sequence) of the physical units for storing data. During the process of programming the entity units to store data, the first type entity units 610(0) to 610(2) labeled as 1 to 3 are programmed in sequence; after programming the first type entity units 610(2), the second type entity units 620(0) - (620) (2) labeled 4-6 are programmed in sequence; after programming the second type entity units 620(2), the first type entity units 610(3) -610 (5) labeled as 7-9 are programmed in sequence; after programming the first type entity units 610(5), the second type entity units 620(3) -620 (5), labeled 10-12, are programmed in sequence.

It should be noted that the numbers 1-12 in the example embodiment of FIG. 6B are only an example, and in another example embodiment, the order of the physical units in each memory plane may be adjusted according to practical requirements. For example, in another exemplary embodiment of fig. 6B, the order of the entity units may be sequentially programmed into a first type entity unit 610(0), a second type entity unit 620(0), a first type entity unit 610(1), a second type entity unit 620(1), a first type entity unit 610(2), a second type entity unit 620(2), a first type entity unit 610(3), a second type entity unit 620(3), a first type entity unit 610(4), a second type entity unit 620(4), a first type entity unit 610(5), a second type entity unit 620(5), and the like, according to the requirement of the business. In addition, the example embodiment of fig. 6B is exemplified by storing data to physical units belonging to the same memory plane (i.e. the memory planes 601(1)), but in another example embodiment, data may be stored to physical units in a plurality of memory planes in an interleaving or parallel manner, as long as the order of use of the physical units in each memory plane meets the default specification.

In an exemplary embodiment, in a programming operation for programming physical cells in a plurality of memory planes in parallel, the physical cells programmed in parallel in each memory plane are (or can only be) one of the first type of physical cells and the second type of physical cells. Taking fig. 6A as an example, assuming that all the physical cells can be used, in a programming procedure, a portion of the first type physical cells in each memory plane are first programmed in parallel; then, in the next program procedure, part of the second type physical cells in each memory plane are programmed in parallel. However, in another exemplary embodiment, the physical cells programmed in parallel in the plurality of memory planes may include both the first type of physical cells and the second type of physical cells.

In the exemplary embodiment, the memory control circuit unit 404 (or a control circuit (not shown) in the rewritable nonvolatile memory module 406) accesses the physical units (or memory cells) in the memory planes 601(1) to 601(M) through the channels 602(1) to 602 (M). For example, channel 602(1) is used to access physical units in memory plane 601(1), channel 602(2) is used to access physical units in memory plane 601 (2); by analogy, channel 602(M) is used to access physical units in memory plane 601 (M).

In an exemplary embodiment, the physical units belonging to the memory plane 601(1) (e.g., the first type physical units 610(0) -610 (a) and the second type physical units 620(0) -620 (a)) can also be regarded as physical units corresponding to the channels 602(1), and the physical units belonging to the memory plane 601(2) (e.g., the first type physical units 610(B) -610 (C) and the second type physical units 620(B) -620 (C)) can also be regarded as physical units corresponding to the channels 602 (2)); similarly, the physical units belonging to the memory plane 601(M), such as the first type physical units 610(D) -610 (E) and the second type physical units 620(D) -620 (E), can also be regarded as the physical units corresponding to the channel 602 (M).

In the present exemplary embodiment, at least two of channels 602(1) -602 (M) support parallel (inline) data reads or writes. For example, when a data is to be stored, the data can be written in parallel to physical cells belonging to multiple memory planes. For example, the first type entity units 610(0) and 610(B) may be programmed in parallel to store the data. Alternatively, the second type entity units 620(0), (620 (B), and 620(D) may be programmed in parallel to store certain data. In addition, when a certain read command is received from the host system 11, data can be read out in parallel from physical units belonging to multiple memory planes. For example, data may also be read from the first type entity units 610(0), (610B), and 610(D) in parallel. Therefore, the access efficiency or the access speed of the data can be improved.

FIG. 7 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 7, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706 and an error checking and correcting circuit 708.

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 702 or any circuit component included in the memory control circuit unit 404 is described below, the operation of the memory control circuit unit 404 is equivalently described.

In the present exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 702 can also be stored in a specific area of the rewritable non-volatile memory module 406 (e.g. a system area dedicated to storing system data in the memory module) by using a program code pattern. In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware format. For example, the memory management circuit 702 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The cell management circuit is used for managing the memory cells or the group of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or scripts for instructing the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations. In an example embodiment, the memory management circuit 702 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the exemplary embodiment, host interface 704 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 706 is electrically connected to the memory management circuit 702 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 wants to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions are generated by, for example, the memory management circuit 702 and transferred to the rewritable non-volatile memory module 406 via the memory interface 706. These sequences of instructions may include one or more signals, or data on a bus. These signals or data may include script or program code. For example, the read command sequence includes the read identification code, the memory address, and other information.

The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 708 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further buffers the memory 710 and the power management circuit 712.

The buffer memory 710 is electrically connected to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is electrically connected to the memory management circuit 702 and is used for controlling the power of the memory storage device 10.

In the exemplary embodiment, the basic unit of the error checking and correcting circuit 708 executing the encoding process is a frame (frame). A frame includes a plurality of data bits. In the present exemplary embodiment, one frame includes 256 bits. However, in another exemplary embodiment, a frame may include more or fewer bits.

In the exemplary embodiment, the error checking and correcting circuit 708 can perform single-frame (single-frame) coding on the data stored in the same physical unit, or perform multi-frame (multi-frame) coding on the data stored in a plurality of physical units. The single-frame coding and the multi-frame coding may respectively adopt at least one of coding algorithms such as a low density parity check code (LDPC), a BCH code, a convolutional code (convolutional code), and a turbo code (turbo). Alternatively, in an exemplary embodiment, the multi-frame coding may also employ a Reed-Solomon code (RS codes) algorithm. In addition, in another exemplary embodiment, more unlisted coding algorithms may be used, and are not described herein. Depending on the encoding algorithm employed, the error checking and correction circuit 708 may encode the data to be protected to produce a corresponding error correction code and/or error check code. For convenience of explanation, the error correction code and/or the error check code generated through encoding will be collectively referred to as encoded data hereinafter.

FIG. 8 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention.

Referring to fig. 8, taking the example of encoding the data stored in the entity units 810(0) to 810(E) to generate the corresponding encoded data 820, at least a portion of the data stored in each of the entity units 810(0) to 810(E) can be regarded as a frame. In multi-frame coding, data in physical units 810(0) -810 (E) are coded based on the position of each bit (or byte). For example, bit b at position 801(1)₁₁、b₂₁、…、b_p1Will be encoded as bit b in the encoded data 820_o1Bit b at position 801(2)₁₂、b₂₂、…、b_p2Will be encoded as bit b in the encoded data 820_o2(ii) a By analogy, bit b at position 801(r)_1r、b_2r、…、b_prWill be encoded as bit b in the encoded data 820_or. The data read from physical units 810(0) -810 (E) may then be decoded based on encoded data 820 in an attempt to correct errors that may be present in the read data.

In addition, in another exemplary embodiment of fig. 8, the data used for generating the encoded data 820 may also include redundant bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the entity units 810(0) -810 (E). Take the data stored in the physical unit 810(0) as an example, wherein the redundant bits are generated by performing single frame encoding on the data bits stored in the physical unit 810(0), for example.

In the present example embodiment, the memory management circuit 702 instructs a plurality of physical units of a first type belonging to one or more memory planes to be programmed to store a certain data (hereinafter also referred to as a first data). The error checking and correcting circuit 708 encodes the first data to generate encoded data and the memory management circuit 702 receives the second data. After encoding the first data, the memory management circuit 702 may instruct at least one of the plurality of second type entity units corresponding to the first type entity unit programmed with the first data to store at least a portion of the second data. Therefore, even if the data in the first type entity unit is influenced by the sudden condition of power failure and the like in the process of programming the second type entity unit corresponding to the first type entity unit stored with the data, the error in the influenced first type entity unit can be corrected according to the encoded data generated in advance.

FIG. 9 is a schematic diagram illustrating programming of a first type of entity cell and encoding of first data according to an example embodiment of the invention.

Referring to FIG. 9, it is assumed that the rewritable nonvolatile memory module 406 has 4 memory planes 601(1) - (601) (4) and can access the physical units in the memory planes 601(1) - (601) (4) through the channels 602(1) - (602) (4), respectively. However, in another example implementation, the rewritable nonvolatile memory module 406 may have more or fewer memory planes, and more or fewer channels may be used to access these memory planes.

In the exemplary embodiment, the memory management circuit 702 programs the first type entity units 610(0) -610 (11) to store the first data, and the error checking and correcting circuit 708 performs multi-frame coding to encode the first data to generate the encoded data 902. The related encoding operations are described in detail above, and are not repeated herein. The encoded data 902 is stored in the rewritable non-volatile memory module 406. Then, if the data stored in the first type entity units 610(0) - (610) (11) is affected during the process of programming any of the second type entity units 620(0) - (620) (11) corresponding to the first type entity units 610(0) - (610) (11), the error checking and correcting circuit 708 may attempt to correct the errors in the data stored in the first type entity units 610(0) - (610) (11) by using the encoded data 902.

It is noted that in another exemplary embodiment of fig. 9, the number of the first type entity units used to generate the encoded data 902 may be more or less, and the first type entity units used to generate the encoded data 902 may be distributed in more or less memory planes. For example, in an example embodiment, the plurality of physical units of the first type used to generate encoded data 902 may only be located in one memory plane.

In an exemplary embodiment, the operation of encoding the first data may be performed at any time to protect the data stored in the first type entity unit. In another exemplary embodiment, the memory management circuit 702 determines whether a predefined operation command (hereinafter also referred to as a specific operation command) is received from the host system 11. In an exemplary embodiment, the specific operation instruction is a flush instruction. However, in another exemplary embodiment, other types of operation instructions can be used as the specific operation instruction. If the specific operation command is received, the memory management circuit 702 instructs the error checking and correcting circuit 708 to perform the operation of encoding the first data. In other words, in an exemplary embodiment, the operation of encoding the first data is performed in response to the specific operation instruction. If the specific operation command is not received, the operation of encoding the first data may not be executed before programming the second type entity unit corresponding to the first type entity unit storing the first data. For example, in another exemplary embodiment of FIG. 9, if the specific operation command is not received, after the first type entity units 610(0) - (610) (11) are programmed, the first data does not need to be encoded, and a part of the second data can be directly stored in any one of the second type entity units 620(0) - (620) (11).

In the present exemplary embodiment, the first data may be user data or system data, and the second data may also be user data or system data. The user data refers to data to be stored as instructed by a write command from the host system 11, and the system data refers to management data (e.g., various management tables such as a logical-physical mapping table) of the rewritable nonvolatile memory module 406.

Under some conditions (e.g., when the host system 11 is going to be powered off, rebooted or cleaned up the memory), the host system 11 will issue a flush command to the memory storage device 10 to instruct the memory storage device 10 to store important data in real time. Generally, after receiving the dump clear command, if the second type entity unit corresponding to a certain first type entity unit does not store data, the padding data (dummy data) is written into the empty second type entity unit to protect the corresponding first type entity unit from data loss due to sudden power failure. Here, padding data refers to data having no specific meaning (e.g., a series of bits 0) or invalid data. However, according to the above exemplary embodiments, after the data stored in the first type entity unit is encoded, any data may be continuously written into the corresponding second type entity unit. Thereafter, even if a programming failure occurs, the error in the first type entity unit can be corrected by using the encoded data generated in advance at any time point. In other words, in an exemplary embodiment, even if the dump clear command is received, the padding data may not be written into the second type physical unit corresponding to the first type physical unit that needs to be protected, thereby prolonging the service life of the memory storage device.

In an exemplary embodiment, the encoded data generated by encoding the first data is used to correct a predetermined number of error bits. As used herein, a default number refers to the number of bits that can be corrected by the encoded data up to a few bits in error. The greater the error correction capability of the encoded data, the greater the predetermined number. The smaller the predetermined number is, the weaker the error correction capability of the encoded data is. For example, this default number may be expressed as a capacity of N physical units. In the exemplary embodiment, each physical unit is configured to store 256 bytes (bytes) of data, so the default number can be expressed as 256 × N bytes. However, in another exemplary embodiment, the default number may be expressed in other ways.

In an exemplary embodiment, when programming physical units of the second type corresponding to physical units of the first type 610(0) - (610) (11), the total number of channels (or memory planes) that can be accessed in parallel in a programming process is limited to less than one channel total. The total number of channels is related to the error correction capability of the encoded data. For example, the total number of channels may be positively correlated to the predetermined number. That is, the greater the error correction capability of the encoded data corresponding to the data already stored in the first type entity unit (i.e., the first data), the greater the total number of channels can be set; the less error correction capability of the encoded data corresponding to the first data, the smaller the total number of channels can be set. By limiting the total number of channels (or memory planes) that can be accessed in parallel while programming the second type of physical cells, the number of first type of physical cells that may be affected during the same programming procedure is reduced and it is ensured that the total number of bits that may subsequently need to be corrected in the first type of physical cells is not greater than the predetermined number.

FIG. 10 is a schematic diagram illustrating programming of a second type of physical unit according to an exemplary embodiment of the invention.

Referring to fig. 9 and 10, assuming that the encoded data 902 can be used to correct 512 bytes (i.e., the total capacity of two physical units) of error bits at most, the memory management circuit 702 limits each programming process to programming at most two physical units of the second type in two memory planes in parallel via two channels. For example, the memory management circuit 702 instructs the rewritable nonvolatile memory module 406 to execute the program 1001 to store a part of the second data. In the programming process 1001, the second type entity units 620(0) and 620(3) are programmed in parallel via channels 602(1) and 602 (2). In particular, the number of channels (e.g., channels 602(1) and 602(2)) used in parallel in the programming 1001 is less than the total number of available channels in channels 602(1) -602 (4). Herein, each available channel refers to a channel that is preset to be used for writing at least a part of the second data in parallel among the channels 602(1) -602 (4) when the second data (or the second data to be stored) is received. For example, if channels 602(1) - (602) (4) are all idle (idle) when the second data is received, each of channels 602(1) - (602) (4) may be considered as an available channel. Alternatively, when the second data is received, if channels 602(1) - (602) (3) are all idle and channel 602(4) is busy (busy) (or the performance of memory storage device 10 is not sufficient to support accessing data via 4 channels at the same time), each of channels 602(1) - (602) (3) may be considered as an available channel. In other words, in the programming process 1001, even though more channels can be used to perform data write operations on more memory planes in parallel, only the channels 602(1) and 602(2) are used in parallel.

After the programming process 1001 is completed, the memory management circuit 702 instructs the rewritable nonvolatile memory module 406 to continue to execute the programming process 1002 to store another part of the second data. In the programming process 1002, the second type entity units 620(6) and 620(9) are programmed in parallel via channels 602(3) and 602 (4). In particular, the number of channels (e.g., channels 602(3) and 602(4)) used in parallel in the program 1002 is less than the total number of available channels in the channels 602(1) -602 (4) when the second data is received. Then, if there is some data in the second data that has not been stored, at least one program procedure can be executed sequentially, wherein each program procedure can program two entity units of the second type (e.g. entity units 620(1) and 620(4)) in two memory planes in parallel until entity units 620(0) to 620(11) of the second type are fully written.

It should be noted that in the exemplary embodiment of fig. 10, even if the other part of the second data is received, the memory management circuit 702 only executes the program 1001 first. After the program 1001 is completed, the program 1002 for storing the other portion of the second data is executed.

In another exemplary embodiment of fig. 10, if a power failure occurs in any one of the above programming procedures for the second type entity units, which may cause a failure or an abnormal halt of the programming procedures for any two second type entity units, a large number of errors may occur in the data in the corresponding first type entity unit. After the power-up is performed again or at any time, the error checking and correcting circuit 708 performs a decoding process on the data stored in the first type of physical unit based on the encoded data generated in advance. In the decoding operation, the data stored in the first type entity unit is read out and the error therein can be corrected. For example, for a failure or abnormal termination of the programmed program 1001, a decoding process based on the decoded data 902 may be performed. Thus, there is a high probability that errors generated in the first type entity units 610(0), 610(3) can be completely corrected. Alternatively, for a failure or abnormal termination of the programmed program 1002, another decoding process based on the decoded data 902 may be performed. Thus, there is a great chance that errors generated in the first type entity units 610(6) and 610(9) can be completely corrected.

In an exemplary embodiment, if the program procedure is executed in parallel using all available channels for storing the second data, although the program procedure may be executed more efficiently, it may be possible that too many first type entity units are affected in the same program procedure and the affected error bits may not be corrected completely. For example, in another exemplary embodiment of fig. 9 and 10, if the

programming procedures

1001 and 1002 are executed in parallel and a power failure occurs during the

programming procedures

1001 and 1002, a large number of errors may occur in the data stored in the first type entity units 610(0), 610(3), 610(6), and 610 (9). In this case, since the total number of bits to be corrected exceeds the predetermined number (i.e., the total capacity of two physical units), the data stored in the first type physical units 610(0), 610(3), 610(6), and 610(9) may be considered invalid or damaged. Thus, in the example embodiment of fig. 10, after encoding the first data stored in the first type of entity unit, the protection capability for the data in the first type of entity unit can be further increased by sequentially performing the program procedure (e.g., sequentially performing the program procedures 1001 and 1002) for the corresponding second type of entity unit using a portion of the available channels.

In addition to the above-mentioned reduction of the total number of channels/memory planes used in parallel in a one-time programming process, in another exemplary embodiment, a similar effect can be achieved by enhancing the error correction capability of the encoded data.

Fig. 11 and 12 are schematic diagrams illustrating a data programming procedure according to an exemplary embodiment of the invention.

Referring to FIG. 11, in the exemplary embodiment, the memory management circuit 702 programs the first type entity units 610(0) -610 (11) to store the first data, and the error checking and correcting circuit 708 performs an encoding process including multi-frame encoding to encode the first data to generate corresponding encoded data. In contrast to the example embodiment of fig. 9, in the present example embodiment, the error correction capability of the encoded data generated by encoding the first data is stronger. In addition, the operation of encoding the first data in the present exemplary embodiment may be performed in response to the specific operation instruction or may be performed at any time point.

In the exemplary embodiment, the error checking and correcting circuit 708 encodes the data (i.e., a portion of the first data) stored in the first type entity units 610(0) - (610) to 5 to generate the encoded data 1102(0) and encodes the data (i.e., another portion of the first data) stored in the first type entity units 610(6) - (610) (11) to generate the encoded data 1102 (1).

In the present exemplary embodiment, the encoded data 1102(0) and 1102(1) are independent of each other. Here, the coded data 1102(0) and 1102(1) are independent of each other, meaning that the coded data 1102(0) and 1102(1) can be used to decode different data, respectively. For example, coded data 1102(0) may be used to decode data stored in first type entity units 610(0) - (610) (5), while coded data 1102(1) may be used to decode data stored in first type entity units 610(6) - (610) (11). In the present exemplary embodiment, the encoded data 1102(0) and 1102(1) can be used to correct the predetermined number (e.g., 512 bytes) of error bits, respectively. In other words, coded data 1102(0) and 1102(1) are summed to correct the erroneous bits of up to 1024 bytes. However, in another exemplary embodiment, the encoded data 1102(0) and 1102(1) may be used to correct more or less error bits, respectively.

Referring to fig. 12, after the first type entity units 610(0) - (610) (11) are programmed, the memory management circuit 702 instructs the rewritable nonvolatile memory module 406 to execute the program 1201 to store at least a portion of the second data. In particular, with respect to the example embodiment of fig. 10, more available channels may be used in parallel to program more physical units of the second type in the programming procedure 1201. For example, when the second data is to be stored, the channels 602(1) - (602) (4) are all idle, and the second type entity units 620(0), (620) (3), (620) (6), and 620(9) can be programmed in parallel via the channels 602(1) - (602) (4).

In an exemplary embodiment, if the operation of the program 1201 fails or is aborted, the error checking and correcting circuit 708 performs a corresponding decoding process on the data stored in the first type entity units 610(0) - (610), (5) and 610(6) - (610), (11), respectively, based on the encoded data 1102(0) and 1102 (1). For example, based on the encoded data 1102(0), errors generated in the first type entity units 610(0) - (610) (5) corresponding to the second type entity units 620(0) and 620(3) programmed in the program 1201 can be corrected; based on the encoded data 1102(1), errors generated in the first type entity units 610(6) -610 (9) corresponding to the second type entity units 620(6) and 620(9) programmed in the programming procedure 1201 can also be corrected.

More specifically, if the procedure 1201 fails or is aborted (e.g., a power failure occurs in the procedure 1201), there is a high probability that a large number of errors will occur in the first type entity units 610(0), (610), (3), (610), (6), and 610(9) simultaneously. Even if the first data stored in the first type entity units 610(0), 610(3), 610(6), and 610(9) are all single-frame encoded (i.e. the encoding process performed by using one entity unit as the basic unit) in advance after the memory storage device 10 is powered on or turned on again, these errors that occur in large numbers cannot be completely corrected by the corresponding single-frame decoding process (i.e. the decoding process performed by using the data in one entity unit as the basic unit). However, in the example embodiment of FIG. 12, the encoded data 1102(0) and the encoded data 1102(1) can be used to correct 512 bytes of erroneous bits (i.e., the amount of data in two physical units), respectively. Therefore, with the encoded data 1102(0), there is a high probability that errors in the first type entity units 610(0) and 610(3) can be completely corrected; with the encoded data 1102(1), there is a high probability that errors in the first type entity units 610(6), 610(9) can be completely corrected.

In other words, compared to the example embodiments of fig. 9 and 10, in the present example embodiment, the error correction capability for protecting the encoded data of the first data stored in the first type of physical unit is stronger, and more memory space is used to store the encoded data; however, since more channels/memory planes are used in a programming process, the writing efficiency or writing speed for data can be improved.

In an exemplary embodiment, whether to improve the error correction capability of the encoded data may also be determined according to whether the specific operation command (e.g., a load clear command) is received. For example, in an exemplary embodiment, the error correction capability of encoded data 902 of FIG. 9 is referred to as a first error correction capability and the combined error correction capabilities of encoded data 1102(0) and 1102(1) of FIG. 11 are referred to as a second error correction capability. For example, the first error correction capability corresponds to correcting at most a first predetermined number of error bits, and the second error correction capability corresponds to correcting at most a second predetermined number of error bits, the second predetermined number being greater than the first predetermined number. In this exemplary embodiment, when the specific operation command is received, the first data may be encoded according to the specific operation command to generate encoded data with a second error correction capability; otherwise, if the specific operation instruction is not received, the first data can be encoded and the encoded data with the relatively poor first error correction capability can be generated.

In an exemplary embodiment, the operations of reducing the total number of channels/memory planes used in parallel in a programmed program and enhancing the error correction capability of encoded data, as mentioned in the above exemplary embodiments, may also be used in combination.

Fig. 13 is a schematic diagram illustrating a data programming procedure according to another exemplary embodiment of the present invention.

Referring to FIG. 13, in the exemplary embodiment, the example is a rewritable nonvolatile memory module 406 having 8 memory planes 601(1) -601 (8). After storing the first data in the first type entity units (shown in fig. 13) of the memory planes 601(1) -601 (8), a portion of the first data stored in the memory planes 601(1) -601 (4) can be encoded into encoded data 1310(0) and another portion of the first data stored in the memory planes 601(5) -601 (8) can be encoded into encoded data 1310 (1). In the present exemplary embodiment, the encoded data 1310(0) and the encoded data 1310(1) are respectively used to correct the predetermined number (e.g., 512 bytes) of error bits. However, in another example embodiment, both encoded data 1310(0) and encoded data 1310(1) may be used to correct more or fewer erroneous bits.

Then, when the second data is to be stored, if channels 602(1) -602 (8) are all available, program routines 1301(0) and 1301(1) are executed in parallel. For example, in the programming procedures 1301(0) and 1301(1), the second type entity units 620(0), 620(3), 620(12), and 620(15) are programmed in parallel via channels 602(1), 602(2), 602(5), and 602(6) to store a portion of the second data. After the program routines 1301(0), 1301(1) and 1301(1) are executed, the program routines 1302(0), 1302(1) are executed in parallel. For example, in the programming procedures 1302(0) and 1302(1), the second type entity units 620(6), 620(9), 620(18), and 620(21) are programmed in parallel via channels 602(3), 602(4), 602(7), and 602(8) to store another portion of the second data.

In an exemplary embodiment, if programming procedures 1301(0) and 1301(1) fail or abort (e.g., power down occurs during programming), then encoded data 1310(0) is used (e.g., after power up is resumed) to decode the portion of the first data stored in memory planes 601(1) -601 (4) to correct errors in memory planes 601(1) and 601(2) caused by programming second type entity units 620(0) and 620 (3); encoded data 1310(1) is used to decode the portion of the first data stored in memory planes 601(5) -601 (8) to correct errors in memory planes 601(5) and 601(6) caused by programming entity units 620(12) and 620(15) of the second type. Alternatively, if the programs 1302(0) and 1302(1) are in error (e.g., power down during programming), then the encoded data 1310(0) is used to decode the portion of the first data stored in the memory planes 601(1) -601 (4) to correct the errors in the memory planes 601(3) and 601(4) caused by programming the second type entity units 620(6) and 620 (9); encoded data 1310(1) is used to decode the portion of the first data stored in memory planes 601(5) -601 (8) to correct errors in memory planes 601(7) and 601(8) caused by programming entity units 620(18) and 620(21) of the second type.

More specifically, in an exemplary embodiment of the program routines 1301(0) and 1301(1) fail or abort, the encoded data 1310(0) can be used to correct a number of errors in the two first type entity units corresponding to the second type entity units 620(0) and 620(3) due to the program routines 1301(0) and 1301(1) failing or aborting, and the encoded data 1310(1) can be used to correct a number of errors in the two first type entity units corresponding to the second type entity units 620(12) and 620(15) due to the program routines 1301(0) and 1301(1) failing or aborting. In an exemplary embodiment of the program routines 1302(0) and 1302(1) failing or aborting, the encoded data 1310(0) is used to correct a plurality of errors in the two first type entity cells corresponding to the second type entity cells 620(6) and 620(9) due to the program routines 1302(0) and 1302(1) failing or aborting, and the encoded data 1310(1) is used to correct a plurality of errors in the two first type entity cells corresponding to the second type entity cells 620(18) and 620(21) due to the program routines 1302(0) and 1302(1) failing or aborting.

Fig. 14 is a flowchart illustrating a data programming method according to an exemplary embodiment of the present invention.

Referring to fig. 14, in step S1401, a plurality of entity units of a plurality of first type entity units in a rewritable nonvolatile memory module are programmed to store first data. In step S1402, the first data is encoded to generate encoded data and the second data is received. In step S1403, at least one entity unit of the plurality of second type entity units corresponding to the first type entity unit in the rewritable nonvolatile memory module is programmed to store at least a portion of the second data.

Fig. 15 is a flowchart illustrating a data programming method according to another exemplary embodiment of the present invention.

Referring to fig. 15, in step S1501, a plurality of entity units of a plurality of first type entity units are programmed to store first data. In step S1502, first data is encoded to generate encoded data and second data is received. In step S1503, the first program is executed to store a first portion of the second data. The first programming procedure includes programming a first portion of the second type entity units through at least one first channel, wherein the first portion of the second type entity units corresponds to a first portion of the first type entity units storing first data. Wherein the first number of the first channels is less than a total number of the plurality of available channels. In step S1504, a second program is executed to store a second portion of the second data. The second programming procedure includes programming a second part of the second type entity units through at least one second channel, wherein the second part of the second type entity units corresponds to a second part of the first type entity units storing the first data. Wherein the second number of second channels is also less than the total number of available channels. It should be noted that, in the present exemplary embodiment, the operation of step S1504 is executed after the operation of step S1503 is completed.

Fig. 16 is a flowchart illustrating a data programming method according to another exemplary embodiment of the present invention.

Referring to fig. 16, in step S1601, a plurality of entity units of a plurality of first type entity units are programmed to store first data. In step S1602, a first portion of the first data stored in a plurality of physical units of the first type corresponding to at least one first channel is encoded to generate first encoded data. In step S1603, a second portion of the first data stored in a plurality of physical units corresponding to at least one second channel in the first type of physical unit is encoded to generate second encoded data. Wherein the first encoded data and the second encoded data are independent of each other. In step S1604, at least one entity cell of the plurality of entity cells of the second type corresponding to the entity cell of the first type is programmed to store at least a portion of the second data.

Referring to fig. 17, in step S1701, a plurality of first type physical units are programmed to store first data. In step S1702, it is determined whether a specific operation instruction is received. For example, the specific operation instruction may be a flush clear instruction. In addition, second data is also received. If the specific operation command is received, in step S1703, the first data is encoded to generate encoded data. In step S1704, at least one entity unit of the plurality of entity units of the second type corresponding to the entity unit of the first type is programmed to store at least a portion of the second data. If the specific operation command is not received, the step S1704 is directly performed after the second data is received without encoding the first data.

However, the steps in fig. 14 to 17 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 14 to fig. 17 can be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the methods of fig. 14 to 17 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, in an exemplary embodiment, first data stored to a first type entity unit corresponding to a plurality of channels is encoded. For example, the operation of encoding the first data may be performed in response to a particular operation instruction. In another exemplary embodiment, after storing the first data, if the corresponding second type entity unit is needed to store the data, the correctness of the data belonging to the paired entity unit in the multi-channel programming procedure can be maintained by adjusting the total number of channels that can be used in parallel in the programming procedure and/or adjusting the error correction capability of the encoded data corresponding to the first data.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data programming method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, wherein the physical units are corresponding to a plurality of channels, wherein the physical units include a plurality of first type physical units and a plurality of second type physical units corresponding to the first type physical units, the data programming method comprising:

programming a plurality of entity units in the first class of entity units to store first data;

performing multi-frame encoding to encode the first data of the plurality of physical units dispersedly stored in the first type of physical units to generate encoded data;

receiving second data; and

after encoding the first data, at least one entity unit in the second class entity units is programmed to store at least one part of the second data.

2. The method of claim 1, wherein the encoded data is used to correct errors in the physical cells storing the first data caused by programming the at least one of the second type of physical cells.

3. The data programming method of claim 1, wherein the step of programming the at least one of the second type of physical units comprises:

executing a first programming procedure to store a first portion of the second data, wherein the first programming procedure includes programming physical units of a first portion of the second types of physical units through at least one first channel of the channels, wherein the physical units of the first portion of the second types of physical units correspond to physical units of the first portion of the physical units for storing the first data, and wherein a first number of the at least one first channel is less than a total number of available channels of the channels; and

after the first programming procedure is executed, executing a second programming procedure to store a second portion of the second data, wherein the second programming procedure includes programming a second portion of the physical units of the second class of physical units via at least one second channel of the channels, wherein the second portion of the physical units of the second class of physical units corresponds to the second portion of the physical units used to store the first data, and wherein a second number of the at least one second channel is less than the total number of the available channels.

4. The data programming method of claim 3, wherein the available channels are channels that can be used in parallel by default corresponding to the second data when the second data is received.

5. The data programming method of claim 3, wherein the encoded data is used to correct a first error in data stored in the physical units for storing the first portion of the physical units of the first data or correct a second error in data stored in the physical units for storing the second portion of the physical units of the first data,

wherein the total number of erroneous bits of the first error is less than or equal to the maximum of the total number of erroneous bits that the encoded data can correct,

wherein a total number of erroneous bits of the second error is less than or equal to the maximum value of the total number of erroneous bits that the encoded data can correct.

6. The method of claim 5, wherein the first error is generated in response to the first programming procedure, and wherein the second error is generated in response to the second programming procedure.

7. The method of claim 1, wherein the step of performing the multi-frame coding to encode the first data of the plurality of physical units dispersedly stored in the first type of physical units to generate the encoded data comprises:

encoding a first part of the first data to generate first encoded data, wherein the first part of the first data is data stored in a plurality of physical units corresponding to at least one third channel of the channels in the first type of physical units in the first data; and

encoding a second part of the first data to generate second encoded data, wherein the second part of the first data is data of the first data stored in a plurality of physical units corresponding to at least a fourth channel of the channels,

wherein the first encoded data and the second encoded data are independent of each other.

8. The method of claim 1, further comprising:

it is determined whether a specific operation instruction is received,

wherein the step of executing the multi-frame code to encode the first data of the plurality of physical units dispersedly stored in the first type of physical units is executed in response to receiving the specific operation instruction.

9. The method of claim 8, wherein the specific operation command comprises a flush clear command.

10. The method of claim 8, further comprising:

if the specific operation command is not received, the first data is not encoded before the at least one entity unit in the second type entity units is programmed.

11. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the memory module comprises a plurality of entity units, wherein the entity units are corresponding to a plurality of channels, and the entity units comprise a plurality of first-class entity units and a plurality of second-class entity units corresponding to the first-class entity units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to send a first write command sequence to instruct a plurality of physical units of the first type of physical units to be programmed to store first data,

wherein the memory control circuit unit is further configured to perform multi-frame coding to encode the first data of the plurality of physical units dispersedly stored in the first type of physical units to generate encoded data,

wherein the memory control circuit unit is further to receive second data,

after encoding the first data, the memory control circuit unit is further configured to send a second write command sequence to instruct programming of at least one of the second type of physical units to store at least a portion of the second data.

12. The memory storage device of claim 11, wherein the encoded data is used to correct errors in the physical cells storing the first data caused by programming the at least one of the second type of physical cells.

13. The memory storage device of claim 11, wherein the second write command sequence instructs to perform a first programming procedure to store a first portion of the second data and to perform a second programming procedure to store a second portion of the second data after performing the first programming procedure,

wherein the first programming procedure includes programming physical units of a first portion of the second types of physical units via at least one first channel of the channels, wherein the physical units of the first portion of the second types of physical units correspond to physical units of a first portion of the physical units for storing the first data, wherein a first number of the at least one first channel is less than a total number of available channels of the channels,

wherein the second programming procedure includes programming physical units of a second portion of the second types of physical units via at least one second channel of the channels, wherein the physical units of the second portion of the second types of physical units correspond to physical units of a second portion of the physical units for storing the first data, wherein a second number of the at least one second channel is less than the total number of the available channels.

14. The memory storage device of claim 13, wherein the available channels are channels that can be used in parallel by default in response to the second data when the second data is received.

15. The memory storage device of claim 13, wherein the encoded data is used to correct a first error in data stored in the first portion of the physical units used to store the first data or to correct a second error in data stored in the second portion of the physical units used to store the first data,

16. The memory storage device of claim 15, wherein the first error is generated in response to the first program routine, and wherein the second error is generated in response to the second program routine.

17. The memory storage device of claim 11, wherein the operation of the memory control circuit unit performing the multi-frame coding to encode the first data of the plurality of physical units dispersedly stored in the first type of physical units to generate the encoded data comprises:

18. The memory storage device of claim 11, wherein the memory control circuit unit is further configured to determine whether a specific operation command is received,

the memory control circuit unit executes the multi-frame coding to code the operation of the plurality of physical units in which the first data is dispersedly stored in the first type of physical units in response to receiving the specific operation instruction.

19. The memory storage device of claim 18, wherein the particular operation instruction comprises a flush clear instruction.

20. The memory storage device of claim 18, wherein the memory control circuit unit does not encode the first data before programming the at least one of the second type of physical units if the specific operation command is not received.

21. A data programming method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, wherein the physical units are corresponding to a plurality of channels, wherein the physical units include a plurality of first type physical units and a plurality of second type physical units corresponding to the first type physical units, the data programming method comprising:

receiving second data;

after storing the first data, performing a first programming procedure to store a first portion of the second data, wherein the first programming procedure includes programming a first portion of the second type of physical units via at least one first channel of the channels, wherein the first portion of the second type of physical units corresponds to a first portion of the second type of physical units used to store the first data, wherein the first number of the at least one first channel is limited to be less than a total number of available channels of the channels; and

after the first programming procedure is executed, executing a second programming procedure to store a second part of the second data, wherein the second programming procedure comprises programming a second part of the physical units of the second class of physical units through at least one second channel with limited number in the channels, wherein the second part of the physical units of the second class of physical units corresponds to the physical units of the second part of the physical units for storing the first data, and the second number of the at least one second channel is limited to be less than the total number of the available channels.

22. The data programming method of claim 21, wherein the available channels are channels that can be used in parallel by default corresponding to the second data when the second data is received.

23. A memory storage device, comprising:

wherein the memory control circuit unit is further to receive second data,

wherein after storing the first data, the memory control circuit unit is further configured to send a second write command sequence to instruct execution of a first programming procedure to store a first portion of the second data and after execution of the first programming procedure, execute a second programming procedure to store a second portion of the second data,

wherein the first programming procedure includes programming a first portion of the physical units of the second type via at least one first channel of the channels, wherein the first portion of the physical units of the second type corresponds to a first portion of the physical units for storing the first data, wherein the first number of the at least one first channel is limited to be less than a total number of available channels of the channels,

wherein the second programming procedure includes programming a second portion of the physical units of the second class of physical units via at least one second channel of the channels, wherein the second portion of the physical units of the second class of physical units corresponds to a second portion of the physical units for storing the first data, wherein the second number of the at least one second channel is limited to be less than the total number of the available channels.

24. The memory storage device of claim 23, wherein the available channels are channels that can be used in parallel by default in response to the second data when the second data is received.