CN104951237A - High-speed storage device based on SATA interface solid state disk - Google Patents
High-speed storage device based on SATA interface solid state disk Download PDFInfo
- Publication number
- CN104951237A CN104951237A CN201410112045.8A CN201410112045A CN104951237A CN 104951237 A CN104951237 A CN 104951237A CN 201410112045 A CN201410112045 A CN 201410112045A CN 104951237 A CN104951237 A CN 104951237A
- Authority
- CN
- China
- Prior art keywords
- module
- data
- interface
- ide
- receives
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Power Sources (AREA)
Abstract
The invention relates to the technical field of data collection systems, in particular to a high-speed storage device based on an SATA interface solid state disk and aims at solving the problems that an existing storage device is low in speed, low in capacity and high in cost in the data storage process. The device is characterized by comprising a core processor, a power supply and power down protecting unit, a Flash configuration circuit, a cache module, an interface module and a transfer chip; the power supply and power down protecting unit, the Flash configuration circuit, the cache module, the interface module and the transfer chip are connected with the core processor respectively, and the SATA interface solid state disk is connected with the transfer chip. According to the device, by the adoption of the core processor, the power supply and power down protecting unit, the Flash configuration circuit, the cache module, the interface module, the transfer chip and the SATA interface solid state disk, the high-speed storage device based on the SATA interface solid state disk is established, and compared with an existing storage device, the device has the advantages of being high in storage speed, large in storage capacity, small in size, low in weight and high in reliability.
Description
Technical field
The present invention relates to data acquisition system (DAS) technical field, be specifically related to a kind of high-speed storage device based on SATA interface solid hard disk.
Background technology
In recent years, the requirement of data communication enterprise to embedded data acquisition storage system is more and more higher, is mainly manifested in the increase of acquisition channel quantity, the raising of signal sampling rate, the lifting of signal sampling precision.High speed, high precision analogue conversion chip is adopted to coordinate high speed processor can complete the lifting of sample rate and precision.And storage speed and capacity are the technological difficulties in data acquisition storage system always, storage medium in the past adopts Flash chip, electric board, CF card etc., and adopt common single-chip microcomputer as processor, which limits speed and the capacity of storage, current requirement cannot be met.Because SATA agreement is complicated, directly use core processor control SATA interface solid hard disk cost high, difficulty is large, and the construction cycle is long, also brings the reduction of reliability thus.
Summary of the invention
The object of the invention is to solve existing memory storage slow at data storage procedure medium velocity, capacity is low, the problem that cost is high, provides a kind of high-speed storage device based on SATA interface solid hard disk.
The present invention is achieved in that
Based on a high-speed storage device for SATA interface solid hard disk, comprise SATA interface solid hard disk, it also comprises core processor, power supply and power down protection unit, Flash configuration circuit, cache module, interface module and connect chip; Wherein, core processor is connected with host computer, power supply and power down protection unit, Flash configuration circuit, cache module, interface module and connect chip respectively, and SATA interface solid hard disk is connected with connect chip; Core processor receives the controling parameters of the input of high speed LVDS data and host computer transmission, the input of high speed LVDS data is converted to parallel data, then this parallel data is sent to connect chip; Core processor sends to connect chip and reads SATA interface solid hard disk data command, receives the data read from connect chip, these data are sent to cache module; Core processor receives the data in cache module, then these data is sent to interface module; Core processor also transmits control signal to power supply and power down protection unit; Power supply and power down protection unit receive the control signal from core processor, for core processor provides power supply and power down protection under the effect of this control signal; Flash configuration circuit loads code stream and embedded program when device starts to core processor; The data that cache module receives from core processor store, and after data storage completes, these data are sent to core processor; Interface module receives the data in core processor, and these data are sent to host computer; Connect chip receives the IDE parallel data after core processor process, and above-mentioned IDE parallel data is converted to SATA parallel data, then SATA parallel data is sent to SATA interface solid hard disk; Connect chip receives the reading SATA interface solid hard disk data command that core processor sends, and sends it to SATA interface solid hard disk; Connect chip receives the data that SATA interface solid hard disk sends, and sends to core processor after this SATA parallel data is converted to IDE parallel data; SATA interface solid hard disk receives the data of connect chip, stores data; SATA interface solid hard disk receives the reading SATA interface solid hard disk data command that connect chip sends, and the data of storage are sent to connect chip.
Core processor as above comprises LVDS receiver module, ide interface module, data management module, Embedded Soft Core Microblaze, CMD interface, CPU_FIFO module and SAVE_FIFO module; Wherein, LVDS receiver module is by SAVE_FIFO module and ide interface model calling; Data management module and ide interface model calling, data management module is also connected with power supply and power down protection unit; Ide interface module is connected with connect chip, and ide interface module is also connected with Embedded Soft Core Microblaze by CPU_FIFO module; Embedded Soft Core Microblaze is connected with data management module by CMD interface, and Embedded Soft Core Microblaze is also connected with cache module and interface module respectively; LVDS receiver module receives the high speed LVDS data from outside, and high speed LVDS data are converted to parallel data, then exports the parallel data after process to SAVE_FIFO module; SAVE_FIFO module receives the data after the conversion of LVD receiver module; SAVE_FIFO module also receives the reading SAVE_FIFO module control signal of ide interface module, and the parallel data after being changed by the LVD receiver module of reception under the control of this signal is sent to ide interface module; Ide interface module receives the storage control signal of data management module, sends and reads SAVE_FIFO module control signal, read the parallel data in SAVE_FIFO module, and parallel data is sent to connect chip to SAVE_FIFO module; Ide interface module receives the reading control signal that data management module sends, and under the control of this reading control signal, reads the IDE parallel data in connect chip, and this IDE parallel data is sent to CPU_FIFO module; Data management module receives the data storage command that CMD interface sends, and sends storage control signal to ide interface module; Data management module receives the data read command that CMD interface sends, and sends read control signal to ide interface module; In power-cut time, data management module transmits control signal to power supply and power down protection unit; Embedded Soft Core Microblaze receives the controling parameters sent from interface module, sends storage control signal or read control signal to CMD interface; After IDE parallel data is sent to CPU_FIFO module by ide interface module, Embedded Soft Core Microblaze sends to CPU_FIFO module and reads CPU_FIFO module data signal, read the data in CPU_FIFO module, data in CPU_FIFO module are sent to cache module, after storage completes, Embedded Soft Core Microblaze reads the data in cache module, and the data in the cache module of reading are sent to interface module; The storage control signal that CMD interface Embedded Soft Core Microblaze sends and reading control signal, be then sent to data management module by above-mentioned storage control signal or reading control signal; CPU_FIFO module receives the IDE parallel data that ide interface module sends, and it also receives the reading CPU_FIFO module data signal that Embedded Soft Core Microblaze sends, under this signal controls, send IDE parallel data to Embedded Soft Core Microblaze.
Core processor as above adopts Spartan6XC6SLX45FPGA to realize.
Power supply as above and power down protection unit are realized by four TPS54620 chip parallel connections.
Flash configuration circuit as above is realized by JS28F256P30 chip.
Cache module as above is realized by DDR3 chip.
Interface module as above is realized jointly by 88E1111 chip and RS422 chip.
Connect chip as above is realized by JMH330S chip.
The invention has the beneficial effects as follows:
The present invention includes core processor, power supply and power down protection unit, Flash configuration circuit, cache module, interface module, connect chip and SATA interface solid hard disk; construct the high-speed storage device based on SATA interface solid hard disk; compare existing memory storage, have that storage speed is fast, the large and small feature that light and reliability is high ingeniously of memory capacity.
Accompanying drawing explanation
Fig. 1 is the structure principle chart of a kind of high-speed storage device based on SATA interface solid hard disk of the present invention;
Fig. 2 is the structure principle chart of the core processor internal module in Fig. 1;
Embodiment
Below in conjunction with the drawings and specific embodiments, the high-speed storage device based on SATA interface solid hard disk of the present invention is described in detail:
As shown in Figure 1, a kind of high-speed storage device based on SATA interface solid hard disk, comprises core processor, power supply and power down protection unit, Flash configuration circuit, cache module, interface module, connect chip and SATA interface solid hard disk.Wherein, core processor is connected with the host computer of outside, power supply and power down protection unit, Flash configuration circuit, cache module, interface module and connect chip respectively, and SATA interface solid hard disk is connected with connect chip.Core processor receives the controling parameters that the outside high speed LVDS data sent input and host computer sends, and after the input of high speed LVDS data is converted to parallel data, this parallel data is sent to connect chip; Core processor sends to connect chip and reads SATA interface solid hard disk data command, receives the data read from connect chip, these data are sent to cache module; Core processor receives the data in cache module, then these data is sent to interface module; Core processor also transmits control signal to power supply and power down protection unit; Power supply and power down protection unit receive the control signal from core processor, for core processor provides power supply and power down protection under the effect of this control signal; Flash configuration circuit loads code stream and embedded program when device starts to core processor; The data that cache module receives from core processor store, and after data storage completes, these data are sent to core processor; Interface module receives the data in core processor, and these data are sent to host computer; Connect chip receives the parallel data after core processor process, comprise IDE bus data, address and control signal, and above-mentioned parallel data is converted to SATA parallel data, comprise SATA bus data, address and control signal, then SATA parallel data is sent to SATA interface solid hard disk; Connect chip receives the reading SATA interface solid hard disk data command that core processor sends, and sends it to SATA interface solid hard disk; Connect chip receives the data that SATA interface solid hard disk sends, and sends to core processor after this SATA parallel data is converted to IDE parallel data; SATA interface solid hard disk receives the data of connect chip, stores data; SATA interface solid hard disk receives the reading SATA interface solid hard disk data command that connect chip sends, and the data of storage are sent to connect chip.
As shown in Figure 2, core processor comprises LVDS receiver module, ide interface module, data management module, Embedded Soft Core Microblaze, CMD interface, CPU_FIFO module and SAVE_FIFO module.Wherein, LVDS receiver module is by SAVE_FIFO module and ide interface model calling; Data management module and ide interface model calling, data management module is also connected with power supply and power down protection unit; Ide interface module is connected with connect chip, and ide interface module is also connected with Embedded Soft Core Microblaze by CPU_FIFO module; Embedded Soft Core Microblaze is connected with data management module by CMD interface, and Embedded Soft Core Microblaze is also connected with cache module and interface module respectively.LVDS receiver module receives the high speed LVDS data from outside, and high speed LVDS data are converted to parallel data, then exports the parallel data after process to SAVE_FIFO module; SAVE_FIFO module receives the data after the conversion of LVD receiver module; SAVE_FIFO module also receives the reading SAVE_FIFO module control signal of ide interface module, and the parallel data after being changed by the LVD receiver module of reception under the control of this signal is sent to ide interface module; Ide interface module receives the storage control signal of data management module, sends and reads SAVE_FIFO module control signal, read the parallel data in SAVE_FIFO module, and parallel data is sent to connect chip to SAVE_FIFO module; Ide interface module receives the reading control signal that data management module sends, and under the control of this reading control signal, reads the IDE parallel data in connect chip, and this IDE parallel data is sent to CPU_FIFO module; Data management module receives the data storage command that CMD interface sends, and sends storage control signal to ide interface module; Data management module receives the data read command that CMD interface sends, and sends read control signal to ide interface module; In power-cut time, data management module transmits control signal to power supply and power down protection unit; Embedded Soft Core Microblaze receives the controling parameters sent from interface module, sends storage control signal or read control signal to CMD interface; After IDE parallel data is sent to CPU_FIFO module by ide interface module, Embedded Soft Core Microblaze sends to CPU_FIFO module and reads CPU_FIFO module data signal, read the data in CPU_FIFO module, data in CPU_FIFO module are sent to cache module, after storage completes, Embedded Soft Core Microblaze reads the data in cache module, and the data in the cache module of reading are sent to interface module; The storage control signal that CMD interface Embedded Soft Core Microblaze sends and reading control signal, be then sent to data management module by above-mentioned storage control signal or reading control signal; CPU_FIFO module receives the IDE parallel data that ide interface module sends, and it also receives the reading CPU_FIFO module data signal that Embedded Soft Core Microblaze sends, under this signal controls, send IDE parallel data to Embedded Soft Core Microblaze.
Core processor can adopt Spartan6XC6SLX45FPGA to realize.Power supply and power down protection unit are realized by prior art parallel connection by four TPS54620 chips.Flash configuration circuit can be realized by JS28F256P30 chip.Cache module can be realized by DDR3 chip.Interface module can be realized jointly by 88E1111 and RS422 chip.Connect chip can be realized by JMH330S chip.SATA interface solid hard disk can use any one in existing SATA interface solid hard disk.
During work, user arranges controling parameters by host computer interface, controling parameters to be passed to the Embedded Soft Core Microblaze in core processor by host computer by interface module, corresponding command routing to data management module, is controlled it and completes data storage and read functions by Embedded Soft Core Microblaze.When storing data, the LVDS receiver module of core processor inside is responsible for receiving LVDS data stream and being converted into parallel data, and parallel data enters ide interface module by SAVE_FIFO.Under data management module controls, ide interface module reads the data of SAVE_FIFO, and carries out high-speed data processing by connect chip control SATA interface solid hard disk; When reading the data, reading control signal is sent to data management module by Embedded Soft Core Microblaze, data management module is by ide interface module sense data be sent to CPU_FIFO from hard disk, Embedded Soft Core Microblaze reads the data in CPU_FIFO, by these data stored in cache module, by interface module, the data in cache module are sent to host computer subsequently.
The present invention includes core processor, power supply and power down protection unit, Flash configuration circuit, cache module, interface module, connect chip and SATA interface solid hard disk; construct the high-speed storage device based on SATA interface solid hard disk; solve existing memory storage slow at data storage procedure medium velocity; capacity is low; the problem that cost is high; compare existing memory storage, have that storage speed is fast, the large and small feature that light and reliability is high ingeniously of memory capacity.
Claims (8)
1. based on a high-speed storage device for SATA interface solid hard disk, comprise SATA interface solid hard disk, it is characterized in that: it also comprises core processor, power supply and power down protection unit, Flash configuration circuit, cache module, interface module and connect chip; Wherein, core processor is connected with host computer, power supply and power down protection unit, Flash configuration circuit, cache module, interface module and connect chip respectively, and SATA interface solid hard disk is connected with connect chip; Core processor receives the controling parameters of the input of high speed LVDS data and host computer transmission, the input of high speed LVDS data is converted to parallel data, then this parallel data is sent to connect chip; Core processor sends to connect chip and reads SATA interface solid hard disk data command, receives the data read from connect chip, these data are sent to cache module; Core processor receives the data in cache module, then these data is sent to interface module; Core processor also transmits control signal to power supply and power down protection unit; Power supply and power down protection unit receive the control signal from core processor, for core processor provides power supply and power down protection under the effect of this control signal; Flash configuration circuit loads code stream and embedded program when device starts to core processor; The data that cache module receives from core processor store, and after data storage completes, these data are sent to core processor; Interface module receives the data in core processor, and these data are sent to host computer; Connect chip receives the IDE parallel data after core processor process, and above-mentioned IDE parallel data is converted to SATA parallel data, then SATA parallel data is sent to SATA interface solid hard disk; Connect chip receives the reading SATA interface solid hard disk data command that core processor sends, and sends it to SATA interface solid hard disk; Connect chip receives the data that SATA interface solid hard disk sends, and sends to core processor after this SATA parallel data is converted to IDE parallel data; SATA interface solid hard disk receives the data of connect chip, stores data; SATA interface solid hard disk receives the reading SATA interface solid hard disk data command that connect chip sends, and the data of storage are sent to connect chip.
2. a kind of high-speed storage device based on SATA interface solid hard disk according to claim 1, is characterized in that: described core processor comprises LVDS receiver module, ide interface module, data management module, Embedded Soft Core Microblaze, CMD interface, CPU_FIFO module and SAVE_FIFO module; Wherein, LVDS receiver module is by SAVE_FIFO module and ide interface model calling; Data management module and ide interface model calling, data management module is also connected with power supply and power down protection unit; Ide interface module is connected with connect chip, and ide interface module is also connected with Embedded Soft Core Microblaze by CPU_FIFO module; Embedded Soft Core Microblaze is connected with data management module by CMD interface, and Embedded Soft Core Microblaze is also connected with cache module and interface module respectively; LVDS receiver module receives the high speed LVDS data from outside, and high speed LVDS data are converted to parallel data, then exports the parallel data after process to SAVE_FIFO module; SAVE_FIFO module receives the data after the conversion of LVD receiver module; SAVE_FIFO module also receives the reading SAVE_FIFO module control signal of ide interface module, and the parallel data after being changed by the LVD receiver module of reception under the control of this signal is sent to ide interface module; Ide interface module receives the storage control signal of data management module, sends and reads SAVE_FIFO module control signal, read the parallel data in SAVE_FIFO module, and parallel data is sent to connect chip to SAVE_FIFO module; Ide interface module receives the reading control signal that data management module sends, and under the control of this reading control signal, reads the IDE parallel data in connect chip, and this IDE parallel data is sent to CPU_FIFO module; Data management module receives the data storage command that CMD interface sends, and sends storage control signal to ide interface module; Data management module receives the data read command that CMD interface sends, and sends read control signal to ide interface module; In power-cut time, data management module transmits control signal to power supply and power down protection unit; Embedded Soft Core Microblaze receives the controling parameters sent from interface module, sends storage control signal or read control signal to CMD interface; After IDE parallel data is sent to CPU_FIFO module by ide interface module, Embedded Soft Core Microblaze sends to CPU_FIFO module and reads CPU_FIFO module data signal, read the data in CPU_FIFO module, data in CPU_FIFO module are sent to cache module, after storage completes, Embedded Soft Core Microblaze reads the data in cache module, and the data in the cache module of reading are sent to interface module; The storage control signal that CMD interface Embedded Soft Core Microblaze sends and reading control signal, be then sent to data management module by above-mentioned storage control signal or reading control signal; CPU_FIFO module receives the IDE parallel data that ide interface module sends, and it also receives the reading CPU_FIFO module data signal that Embedded Soft Core Microblaze sends, under this signal controls, send IDE parallel data to Embedded Soft Core Microblaze.
3. a kind of high-speed storage device based on SATA interface solid hard disk according to claim 1, is characterized in that: described core processor adopts Spartan6XC6SLX45FPGA to realize.
4. a kind of high-speed storage device based on SATA interface solid hard disk according to claim 1, is characterized in that: described power supply and power down protection unit are realized by four TPS54620 chip parallel connections.
5. the high-speed storage device based on SATA interface solid hard disk according to claim 1, is characterized in that: described Flash configuration circuit is realized by JS28F256P30 chip.
6. the high-speed storage device based on SATA interface solid hard disk according to claim 1, is characterized in that: described cache module is realized by DDR3 chip.
7. the high-speed storage device based on SATA interface solid hard disk according to claim 1, is characterized in that: described interface module is realized jointly by 88E1111 chip and RS422 chip.
8. the high-speed storage device based on SATA interface solid hard disk according to claim 1, is characterized in that: described connect chip is realized by JMH330S chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410112045.8A CN104951237B (en) | 2014-03-24 | 2014-03-24 | High-speed storage device based on SATA interface solid state hard disc |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410112045.8A CN104951237B (en) | 2014-03-24 | 2014-03-24 | High-speed storage device based on SATA interface solid state hard disc |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104951237A true CN104951237A (en) | 2015-09-30 |
| CN104951237B CN104951237B (en) | 2018-04-27 |
Family
ID=54165919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410112045.8A Expired - Fee Related CN104951237B (en) | 2014-03-24 | 2014-03-24 | High-speed storage device based on SATA interface solid state hard disc |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104951237B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107563229A (en) * | 2017-09-14 | 2018-01-09 | 苏州恒成芯兴电子技术有限公司 | A kind of power down protection module suitable for solid state hard disc |
| CN112445344A (en) * | 2019-08-29 | 2021-03-05 | 中核核电运行管理有限公司 | Acquisition control device based on Ethernet interface DCC keyboard |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050060481A1 (en) * | 2002-02-25 | 2005-03-17 | Solid Access Technologies L.L.C. | Control unit with PCI and SCSI buses and computing system with electronic semiconductor disk |
| CN101140502A (en) * | 2007-10-19 | 2008-03-12 | 华为技术有限公司 | Solid-state hard disk controller circuit and solid-state hard disk |
-
2014
- 2014-03-24 CN CN201410112045.8A patent/CN104951237B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050060481A1 (en) * | 2002-02-25 | 2005-03-17 | Solid Access Technologies L.L.C. | Control unit with PCI and SCSI buses and computing system with electronic semiconductor disk |
| CN101140502A (en) * | 2007-10-19 | 2008-03-12 | 华为技术有限公司 | Solid-state hard disk controller circuit and solid-state hard disk |
Non-Patent Citations (2)
| Title |
|---|
| 孙海波等: "基于SATA接口固态硬盘的高速存储系统设计", 《遥测遥控》 * |
| 王洁: "阵列雷达回波模拟器技术研究", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107563229A (en) * | 2017-09-14 | 2018-01-09 | 苏州恒成芯兴电子技术有限公司 | A kind of power down protection module suitable for solid state hard disc |
| CN112445344A (en) * | 2019-08-29 | 2021-03-05 | 中核核电运行管理有限公司 | Acquisition control device based on Ethernet interface DCC keyboard |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104951237B (en) | 2018-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101988260B1 (en) | EMBEDDED MULTIMEDIA CARD(eMMC), AND METHOD FOR OPERATING THE eMMC | |
| JP2013037517A5 (en) | ||
| CN104021107A (en) | Design method for system supporting non-volatile memory express peripheral component interface express solid state disc (NVMe PCIE SSD) | |
| CN204303350U (en) | A kind of multifunctional solid hard disk | |
| CN104731746A (en) | Equipment controller device | |
| CN104361143B (en) | A kind of portable data acquisition card and its method | |
| CN204166088U (en) | Local discharge signal harvester | |
| CN104571942B (en) | Data-storage system and non-signal analysis method | |
| CN107329929B (en) | Data transmission system and data transmission method based on SoC FPGA | |
| CN202584143U (en) | A read-only card reader with multiple interfaces | |
| CN104951237A (en) | High-speed storage device based on SATA interface solid state disk | |
| CN105573947B (en) | A kind of SD/MMC card control methods based on APB buses | |
| CN205068512U (en) | Wireless fingerprint attendance system | |
| CN103294411B (en) | There is the low speed load data load-on module of massive store | |
| KR20220064786A (en) | Ufs device, operating method of ufs device and system including the same | |
| CN104615565A (en) | SAS card device with transmission rate reaching 12Gb | |
| CN103838694A (en) | FPGA high-speed USB interface data reading method | |
| CN102841878B (en) | Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) | |
| CN109753459A (en) | A kind of high capacity data record device | |
| CN111444131B (en) | Data acquisition and transmission device based on USB3.0 | |
| CN103744807B (en) | Storage card based on PLD accesses control system | |
| CN201654787U (en) | Data collecting device based on USB | |
| CN106649183A (en) | Low power consumption serial communication chip based on MCU | |
| Tian et al. | Design and Implementation of USB3. 0 Data Transmission System based on FPGA | |
| CN104010109A (en) | Dual digital signal processing image processing board and operation mode thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180427 |