CN104731746A - Equipment controller device - Google Patents
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- CN104731746A CN104731746A CN201310706655.6A CN201310706655A CN104731746A CN 104731746 A CN104731746 A CN 104731746A CN 201310706655 A CN201310706655 A CN 201310706655A CN 104731746 A CN104731746 A CN 104731746A
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Abstract
The invention discloses an equipment controller device which comprises a USB protocol data processing module used for selecting the work of USB 2.0 mode or HSIC mode; an end-point control module used for processing address decoding of a plurality of end-points in the device; a register control module connected with the USB protocol data processing module and the end-point control module and used for storing the register parameters of ARM CPU of the device collocated according to the link layer protocol; a slave unit bus module of AMBA bus connected with the register control module, connected with the ARM CPU of the device through the AMBA bus and used for collocating the parameters for each register in the register control module according to the link layer protocol for the ARM CPU; a standard UIMI bus connected with USB 2.0 PHY or HSIC PHY. The equipment controller device supports the HSIC protocol and USB 2.0 protocol, greatly reduces the design cost and has enough flexibility.
Description
Technical field
The present invention relates to a kind of USB(Universal Serial Bus USB (universal serial bus)) device controller device, particularly relate to and a kind of support interconnected USB between HSIC(High Speed Inter-chip high-speed chip) the device controller device of agreement and USB2.0 agreement.
Background technology
USB is applied to PC(PC) technology of interface field, support plug and play and warm connection function.Applied rapid development in recent years, and be extended to more how consumer and portable kind equipment, become mainstream applications interface standard.In order to the demand of satisfied application, the continuous evolution of message transmission rate of USB standard, USB2.0 reaches 480Mbps(megabit per second), USB3.0 speed is then higher.At present and the coming years, USB2.0 application will exist with USB3.0 application is common.
Between HSIC high-speed chip, interconnect standard is as newer a kind of standard usb interface, makes full use of the infrastructure of existing USB, and without the need to adopting traditional USB cable and plug; Adopt digital interface generally, in same printed circuit board (PCB) or the interchange completing chip chamber information in same multi-chip product, reach interconnection, more easily become the standard interface of other agreement.Such as, USB (universal serial bus) between HSIC USB(high-speed chip) may be used for compact size PC or smart mobile phone in, connect embedded IP Camera, flash memory card reader, wifi(Wireless Fidelity WLAN (wireless local area network)) chip etc., HSIC also can be used as SIM(client identification module) transmission interface of card and mobile phone.
The compatible USB2.0 of HSIC supports 480Mbps speed, so can by providing HSIC USB PHY(Physical layer) reach inter-chip interconnects, and avoid adopting the cable and analog component that use in traditional USB2.0PHY simultaneously.Under this standard may operate in lower CMOS level, and interface is quite simple---only have 2 wires.This standard also being saved power consumption by avoiding adopting analog component, farthest being reduced costs, and contributes to reducing risk.HSIC was applied to design field from 2008.
USB hardware structure is divided into main frame, hub, and function device.For the function device of USB2.0, UTMI(USB2.0Transceiver Macrocell Interface USB2.0 Transceiver Macrocell Interface) difficulty developed for reducing device chip of interface standard, shorten the design cycle of product, reduce risk, its standardization USB PHY module and USB device controller module interface.
PHY module is also referred to as USB2.0Transceiver Macrocell(USB2.0 transceiver macroelement), for the treatment of Higher-Speed Physical Layer signaling protocol.USB device controller module is also called SIE(the Serial Interface Engine serial interface engine), for the treatment of USB link layer protocol.UTMI agreement carries out defining for the signal characteristic of USB2.0, is divided into 8 or 16 bit data interface, linestate(line states wherein) signal for reflecting physics bus state, control whole usb protocol state for USB device controller module.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of device controller device, supports HSIC agreement and USB2.0 agreement, can farthest reduce design and add cost, and have enough dirigibilities.
For solving the problems of the technologies described above, device controller device of the present invention, comprising:
One usb protocol data processing module, is operated in USB2.0 pattern or HSIC pattern for selecting;
One pipe control module, is connected with described usb protocol data processing module, for the treatment of the address decoding of the multiple end points of device interior;
One register control module, with described usb protocol data processing module, pipe control module is connected, each register parameters that the ARM CPU for depositing equipment configures according to link layer protocol;
The AdvancedMicro-Controller Bus Architecture of one AMBA(advanced micro controller bus architecture ARM Limited) bus from device bus module, be connected with described register control module, and by the advanced risc machine of the ARM(Advanced RISCMachines of AMBA bus and equipment) CPU is connected, and carries out parameter configuration for described ARM CPU according to link layer protocol to each register in described register control module;
One standard UIMI bus, for connecting USB2.0 physical layer block or HSIC physical layer block.
The present invention had both supported USB2.0 agreement, also supported HSIC agreement; By standard utmi interface, USB2.0 physical layer block or HSIC physical layer block can be connected, greatly reduce design, integrated, the cost of checking; And there is enough dirigibilities, be suitable in future products multiplexing, the demand of different application scene can be met, save time and capital.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the theory diagram that described device controller device is connected with HSIC physical layer block;
Fig. 2 is the theory diagram that described device controller device is connected with USB2.0 physical layer block;
Fig. 3 is usb protocol data processing module block diagram in Fig. 1,2;
Fig. 4 is register control module theory diagram in Fig. 1,2;
Fig. 5 is RAM interface control module theory diagram in Fig. 1,2.
Embodiment
Fig. 1 is that described device controller device is connected with HSIC physical layer block, supports HSIC agreement, is operated in the theory diagram of HSIC pattern.
Fig. 2 is that described device controller device is connected with USB2.0 physical layer block, supports USB2.0 agreement, is operated in the theory diagram of USB2.0 pattern.
Shown in composition graphs 1,2, described device controller device in the following embodiments, comprising:
One usb protocol data processing module, is operated in USB2.0 pattern or HSIC pattern for selecting; The bag identification of the dissimilar bag of the USB based on utmi interface receives, group bag sends and corresponding CRC(cyclic redundancy check (CRC) code) verification; Realize the state machine etc. of USB power managed agreement.The dissimilar handbag of described USB draws together token packet, packet, handshake packet and spectacle case.
One pipe control module, is connected with RAM interface control module with described usb protocol data processing module, for the treatment of the address decoding of the multiple end points of device interior; According to the Transport endpoint type that current hosts is chosen, reception and the transmission processing of the dissimilar bag of corresponding end points is carried out according to the steering order of different Transport endpoint type transport protocol and register control module, produce the interrupt identification and other mark that are used for register control module, produce the Read-write Catrol and data encasement that are used for RAM interface control module.Described Transport endpoint type, comprising: control end points, bulk transfer end points, interrupt transfer end points and synchronous transmission end points.Other mark described comprises the length of the bag receiving from host, and transmission and reception bag number indicates, and frame number indicates.
One RAM interface control module, is connected with described pipe control module, for plug-in Large Copacity RAM, is convenient to system-level saving storage space, accomplish storage unit system-level integrated time multiplexing, can accomplish by byte Coutinuous store 16 bit memory interfaces.
One register control module, with described usb protocol data processing module, pipe control module is connected with RAM interface control module, each register parameters that the ARM CPU for depositing equipment configures according to link layer protocol.
One AMBA bus from device bus module, be connected with described register control module, and be connected with the ARM CPU of equipment by AMBA bus, according to link layer protocol, parameter configuration is carried out to each register in described register control module for described ARM CPU.
One standard UIMI bus, for connecting USB2.0PHY module or HSIC PHY module.Described UIMI bus, comprises UIMI control bus and UIMI data bus.UIMI control bus comprises: clock (clk), reset(reset), opmode [1:0] (operator scheme), tevrselect (terminal selections), xcvrselect (transceiver selection) and suspendm(hang-up).
Described usb protocol data processing module, can be adopted software to be configured by AMBA bus by outside ARM CPU, select to be operated in USB2.0 pattern or HSIC pattern.Such as can by the mode select signal of the mode controller in AMBA bus definition usb protocol data processing module, 0 represents USB2.0 pattern, and 1 represents HSIC pattern, otherwise or.Described AMBA bus, comprises AHB(Advanced High-performance Bus) bus or APB(sophisticated equipment bus) bus.
Described usb protocol data processing module, the USB mode control signal that also can be produced by external hardware configuration selection is operated in USB2.0 pattern or HSIC pattern.If adopt the mode control signal control model that hardware produces, described device controller device is fixed into USB2.0 pattern or HSIC pattern when integrated or when applying.
Described usb protocol data processing module, also a selector switch can be set, in the mode control signal configuration of hardware generation with under adopting software definition to configure simultaneous situation, select corresponding control model, and select to be operated in USB2.0 pattern or HSIC pattern under corresponding control model.
According to the linestate signal definition of UTMI standard interface, linestate [1:0] reflects the state of USB2.0 bus signals, linestate [1] corresponding DM(data negative pole corresponding USB2.0 data negative pole D-in the UTMI of USB2.0) signal, linestate [0] corresponding DP(data positive pole corresponding USB2.0 data positive pole D+) signal.For " 00 ", linestate [1:0] value represents that USB2.0 bus is SE0, linestate [1:0] value is that " 01 " represents USB2.0 bus J state, and linestate [1:0] value is that " 10 " represent USB2.0 bus K state.In USB2.0 when Full-Speed mode or the transmission of low-speed mode non-data, SE0 represents reset, and J state representation bus free, K state representation is waken up.In data transmission procedure, DM and DP is differential signal, is alternately change substantially.Because speed is slow, linestate [1:0] directly reacts the change of USB2.0 bus signals, and namely K, J state alternately occurs.But in the data transmission procedure of fast mode, because USB2.0 bus signals overturns by 480M clock, linestate [1:0] can not directly react USB2.0 bus state, and standard specifies the data transmission of the J status representative fast mode of linestate [1:0].The reset of USB2.0 fast mode and free time, USB2.0 bus signals is all SE0 state, and namely { DM, DP} are { 0,0}.
Appearance due to HSIC standard is later than UTMI standard, so UTMI standard does not do corresponding and refinement further to HSIC.A kind of fast mode is only had for HSIC standard, transmission data phase and non-transmitting stage can be further subdivided in high speed mode.
Described device controller device is selected linestae, xcvrselect(transceiver based on HSIC and utmi interface) signal defines, and can control HSIC agreement according to this kind of definition.
Definition HSIC protocols work is in high speed non-transmitting stage and high-speed transfer stage.
The high speed non-transmitting stage of HSIC agreement, comprise: between turnoff time, power on period, the HSIC that powers on enable (power on enable refer to device power after, HSIC device controller is configured to enable, now can detect that HSIC bus is in drag down or IDLE state), the enable rear equipment Inspection that powers on is idle to HSIC bus IDLE() after the CONNECT(that must initiate connect) period (a unique CONNECT connects).The high speed non-transmitting stage also comprises the idle period of time sending out HSIC bus after CONNECT signal, the reseting period that first time main frame is subsequently initiated, during HSIC bus suspension, between awake period.
The high-speed transfer stage of HSIC agreement, comprise: after sending out CONNECT signal, host reset enters the high-speed transfer stage after terminating for the first time, HSIC bus is in idle condition subsequently, or data transmission state, or host reset state, until HSIC bus suspension enters again the high speed non-transmitting stage, HSIC bus also enters the high-speed transfer stage after waking end up.
Between awake period.Because HSIC agreement does not need to detect that the laggard horizontal reset of reset is shaken hands at every turn, so detect that reset signal 2.5 μ s enters the real high-speed transfer stage after terminating, HSIC bus is in the idle condition in high-speed transfer stage, then may initiate transmission.Linestate reflects HSIC bus state, the corresponding DATA(data of linestate [1]) line, the corresponding STROBE(gating of linestate [0]) line.When HSIC bus is in the high speed non-transmitting stage, xcvrselect is 1, linestate [1:0] is reaction { DATA directly, STROBE} state, when being in the high-speed transfer stage, in order to compatible USB2.0UTMI agreement can adopt linestate [1:0]=00 to represent bus free, linestate [1:0]=10 represents bus reset, and in high speed data transfer process, linestate [1:0]=01 represents that data are in transmission.Following table defines based on the UTMI bus state of HSIC.High speed non-transmitting stage of HSIC can the Full-Speed mode of analogy USB2.0, and the high-speed transfer stage can the fast mode of analogy USB2.0.
In upper table, because UTMI standard definition SE1 state is debugging purposes, do not allow in the course of the work to use SE1 state, therefore when initiating at high-speed transfer stage main frame, when resetting, linestate is defined as 10 (K), the free time in high-speed transfer stage is 00 (SE0) compatible USB2.0 fast mode, transmits data period linestate and be necessary for J in UTMI standard.If the high-speed transfer stage adopts to reset still be defined as 00 (SE0), so the free time in high-speed transfer stage just can only represent with 10 (K), but the linestate defined with USB2.0 and UTMI agreement [1:0] is 00 expression SE0, SE0 represents that the free time under fast mode does not meet.
Described device controller device is considered and is not done further definition to HSIC based on UTMI standard, HSIC PHY may be designed by different manufacturers, linestate is directly react bus state according to UTMI standard basic thought, in the high speed non-transmitting stage, directly react HSIC bus state, as above show, can redefine based on software register the reset of linestate and free time in the high-speed transfer stage, but ensure that transmission data period linestate is (01), i.e. J state.
The structure of described usb protocol data processing module as shown in Figure 3, comprising: a usb bus status control module, one based on utmi interface USB bag receive and sending module.
The described USB based on utmi interface wraps and receives and sending module, the information of described register control module is received by register interface, receive the external data signal from USB physical layer block by UTMI data bus, mainly realize receiving based on the identification of the dissimilar bag of USB of utmi interface and the transmission of group bag.
Described identification receives the decoding (token packet, packet, handshake packet, spectacle case) comprising Packet type mark domain, the extraction of device address and device interior end-point addresses, separate CRC code, frame number is extracted, the identification of utmi interface valid data and be converted to the high low byte of inner band effective marker.
Group bag sends the coding mainly comprising the Packet type mark domain of handshake packet and packet, height byte from described pipe control module counts to the data conversion of utmi interface, the coding of CRC code, USB2.0 agreement is sent for high speed speed identification signal Chirp-K according to sending request of usb bus status control module, the CONNECT(that sets up sending HSIC agreement connects) signal, send Remote Wake Up signal.
Described usb bus status control module, wraps to receive with the described USB based on utmi interface and is connected with sending module, comprising:
One mode controller, under the control of mode control signal, produces mode select signal, shows that work at present is in HSIC pattern or USB2.0 pattern; .
One HSIC line states detecting device, redefines signal and linestate [1:0] signal and HISC high-speed transfer stage decision device according to the HSIC high-speed transfer line states of input, produces HSIC state machine control signals.
One USB2.0 line states detecting device, redefines signal and linestate signal and USB2.0 speed decision device according to the HSIC high-speed transfer line states of input, produces USB2.0 state machine control signals.
One counter and time tag produce circuit. and its counter is in the time of certain state for adding up USB2.0 bus or HSIC bus, it is then put corresponding time tag according to the value of counter at corresponding time point that time tag produces circuit, such as, detect HSIC bus free 3ms under HSIC pattern, then 3ms time tag has been put, HSIC state machine detects the set of 3ms time tag, then HSIC state machine jumps to suspended state from idle condition.
One HSIC state machine, be connected with time tag generator with described mode controller, HSIC line states detecting device and counter, under the control of described mode select signal, starting work, and under the control of described HSIC state machine control signals, being idle for detecting current HSIC bus, reset, initiate to connect, transmission, Remote Wake Up, recover, or suspended state.
One USB2.0 state machine, be connected with time tag generator with described mode controller, USB2.0 line states detecting device and counter, work is started under the control of described mode select signal, and under the control of described USB2.0 state machine control signals, be idle for detecting current USB2.0 bus, reset, Chirp sends and detects, wake up, suspended state.
One sends CONNECT controller, is connected with HSIC state machine, and generation transmission CONNECT control signal is defeated by the described USB based on utmi interface bag and is received and sending module, and utmi interface produces the data of correspondence.
One selector switch, be connected with USB2.0 state machine with described mode controller, HSIC state machine, under the control of described mode select signal, USB2.0 pattern or HSIC pattern is operated in for selecting, and select UTMI control signal to export by described mode select signal, this UTMI control signal, comprises xcvrselect (transceiver selection), tevrselect (terminal selection), opmode (operator scheme), suspendm(hangs up) and reset(reset).
One sends Remote Wake Up controller, be connected with USB2.0 state machine with described mode controller, HSIC state machine, the Remote Wake Up control bit accepted from the power managed register in described register control module controls, wrap to the described USB based on utmi interface for generation of Remote Wake Up control signal to receive and sending module, send Remote Wake Up signal to main frame.
One sends and detects Chirp(high speed speed identification signal) controller, be connected with USB2.0 line states detecting device with USB2.0 state machine, Chirp-K control signal is produced for USB2.0 high speed reset handshake phase, and export to the described USB bag delivery and reception module based on utmi interface, and detect by linestate Chirp-K and the Chirp-J signal replaced that main frame sends subsequently.
The Chirp-K signal that equipment is initiated shows as the D-of USB two lines than D+ height 800mv, continues 1 millisecond to 7 milliseconds.Chirp-K and the Chirp_J signal replaced of high speed host computer host initiation subsequently, Chirp-K shows as the D-(data line negative pole) of USB two difference transmission lines than D+(data line positive pole) high 800mv, Chirp-J signal shows as the D+ of USB two difference transmission lines than D-line height 800mv millivolt, each Chirp-K and Chipr-J μ s's signal duration 40 and 60 μ s, middle uninterrupted.
One USB2.0 speed decision device, be connected with USB2.0 line states controller with USB2.0 state machine, utilize the USB20 speed-mode control bit deposited from the mode control register in described register control module, produce high speed or the full speed identification signal of USB2.0, the USB2.0 bus state further under control USB2.0 line states detecting device output corresponding modes.Produce zone bit to interrupt control register simultaneously.
One HSIC high-speed transfer stage decision device, is connected with HSIC line states controller with HISC state machine, produces the high-speed transfer stage identification signal of HISC, the HSIC bus state further under control HSIC line states detecting device output corresponding modes.
One USB reset controller, according to HSIC state machine, the output of USB state machine and mode controller produces the reseting controling signal from usb bus, controls the interrupt control register except register control module in described device controller device, beyond mode control register, remainder resets.
Shown in Figure 4, described register control module, comprising:
One address decoder, for according to the described address exported from device bus module, reads or writes Warning Mark, select signal, what produce the inner corresponding registers of described register control module reads enable signal, or write enable signal, and described register control module internal register physical address.
One Read Controller, reads enable and address for what produce according to described address decoder, writes described register control module corresponding registers by from the described supplemental characteristic from device bus module.
One writing controller, writes enable and address for what produce according to described address decoder, is read into by the supplemental characteristic of described register control module corresponding registers described from device bus module.
One interruptable controller, is converted to the Status Flag of the register of described register control module for the mark that detects from described usb protocol data processing module and pipe control module.
One mode control register, for depositing mode control signal, represents that the pattern of current peripheral work is HISC pattern or USB2.0 pattern; Deposit the enable control signal of HISC; Software reset's control bit is set simultaneously, register system Software reset signal; Deposit test mode signal; Deposit USB2.0 velocity mode signal, represent that USB2.0 is high speed or full speed; Deposit the USB2.0 software plug control bit of setting.
One end points n control register group, for depositing the controling parameters of end points n, comprise each end points start and end address in memory, end points storer resets and controls, the enable control of end points, endpoint type configures, endpoint number, end points direction, the upset of end-point data Packet type controls, in endpoint transmission, the long and short handbag length of maximum bag and respective enable control, very fast high-bandwidth block number configures, dissimilar transmission or receive successful interrupt flag register in the enable and transmission of dissimilar bag Transmission in the transmission of end points bag, stopping handshake packet being sent out in software control.For control end points (end points 0) can in register control module special setting register, the foundation bag of 8 bytes that the establishment stage controlling end points receives is placed in this special setting register, and controlling end points can send stopping bag by software control and send negative response handshake packet.
One software and hardware sends out CONNECT control register, sends out CONNECT control signal for depositing software and hardware, represents in HISC pattern configurations it is that CONENCT pattern sent out by software or CONNECT pattern sent out automatically by hardware.If CONNECT signal sent out automatically by hardware, then described device controller device detect and power on after HISC bus free automatically initiate CONNECT; If CONNECT sent out by software then also need send control bit in the initiation moment by software merit rating.Define CONNECT cut to lengthen bit in control bit, scope is from 1 to 16 HSIC data transfer cycles (HSIC transfer rate is 480M bits per second).
One HSIC high-speed transfer line states redefines register, redefining signal, redefining the implication receiving linestate on high-speed transfer rank for depositing HSIC high-speed transfer line states; Default mode, the high-speed transfer stage, HSIC bus reset state linestate was 10(K), idle condition linestate is 00 (SE0); Redefine pattern, the high-speed transfer stage, HSIC bus reset state linestate was 00 (SE0), and during idle condition, linestate is 10 (K).
One HSIC PHY High Speed I/O delays time to control register, for depositing HISC physical layer block High Speed I/O delay control signal, High Speed Analog I/O (I/O) in definition adjustment HSIC physical layer block, the time delay of the input buffering of STROBE (gating) and DATA (data), the multiple time delay unit of definable, such as 0 represents not delay, and 1 representative is inserted at the 100ps (psec) of HSIC.
One interrupt control register, for depositing the enable and usb bus state interrupt mark of usb bus state interrupt.Described interrupt identification, comprises; Frame start interrupt, reset interrupt, hang up interrupt, recover interrupt, USB2.0 high speed detection interrupt, HSIC power on idle-detection interrupt, HSIC initiates disconnecting.
One device address register, for depositing the device address of usb protocol data processing module described in software merit rating.
One frame number status register, for depositing the frame number receiving main frame transmission from described usb protocol data processing module.
One scratchpad register, is operated in the test mode signal of different test pattern for depositing software merit rating device controller device, and is transferred to described pipe control module.
One power managed register, whether detect that the 3ms free time enters suspended state for depositing software controlled device control device, software can control described device controller device and exit suspended state; Produce Remote Wake Up signal, initiate Remote Wake Up by software controlled device.
Described device controller device adopts software and hardware to send out the pattern of CONNECT signal, and can be sent out the length of CONNECT signal by software definition, to adapt to main frame and the abnormal conditions of different manufacturers in standard evolution.Be defaulted as described device controller device power on and enablely (enablely refer to that software merit rating mode control register is HSIC pattern, then think and enable HISC device controller) after HSIC bus free a period of time detected after, automatically CONNECT signal is sent out to main frame, length is defaulted as 4 bits, the transmission cycle of a bit is 2.083ns, the i.e. message transmission rate 480M bits per second of HSIC, meets initial stage HSIC standard; The CONNECT(8bit UTMI of 5 ~ 8 bit lengths is sent out by software definable) signal or 5 ~ 16bit(bit) the CONNECT(16bit UTMI of length) signal, what adapt to new standard regulation is greater than 2 STROBE(gatings) CONNECT in cycle.
Described device controller device adopts the High Speed I/O time delay of HSIC physical layer block High Speed I/O delay register definition HSIC physical layer block, after the parameter value of the complete described HSIC physical layer block High Speed I/O delays time to control register of software merit rating, the parameter value of this HSIC PHY High Speed I/O delays time to control register is directly outputted to described device controller device port by described device controller device, for the High Speed I/O time delay of control HISC physical layer block, be convenient to adjust because the wiring of plate level encapsulates the unequal problem of STROBE and DATA time delay brought.Adopt STROBE(gating) and DATA(data) two groups of control lines, often organize 8 bits, the Adjustment precision of 256 step-lengths can be controlled, namely can by the 480M clock period, be equivalent to 2.08ns and be divided at most 256 time quantums (8.125ps), embody rule can software definition.
Described device controller device is one group of register for each end design, i.e. described end points n control register group, often organize the starting and ending address having this port in register, the data that can define each port flexibly, in the position of plug-in RAM, are convenient to system application memory multiplexing.
Shown in Figure 5, described RAM interface control module, comprising:
One Asynchronous Reception FIFO(first in first out) register, for depositing the data being sent to described device controller device by main frame from described pipe control module.
The Read Controller of one Asynchronous Reception fifo register, for reading the data of described Asynchronous Reception fifo register, prepares the plug-in RAM of the described device controller device of write.
One asynchronous transmission fifo register, for depositing the data being issued main frame by described device controller device from described plug-in RAM.
The writing controller of one asynchronous transmission fifo register, for writing described asynchronous transmission fifo register by the data from described plug-in RAM.
One RAM Read-write Catrol module, it comprises:
One address ram counter, by the byte stored count of transmission during for transmitting at every turn, resets when each transmission starts.
One RAM base address controller, for recording the final end address after each end of transmission (EOT), preserves by byte.Upgrade preserved final end address after each end of transmission (EOT), add that the current transmission byte length just terminated is as preparation address ram with the final end address after last end of transmission (EOT), the final end address namely upgraded.Initial base address is the RAM start address of endpoint configurations.
One totalizer, is added the output of described address ram counter and the output of RAM base address controller, produces RAM byte address, as preparation address ram.Namely add that the current transmission byte length just terminated is as preparation address ram, is defeated by ram space and cut position controller with the final end address after last end of transmission (EOT).
One ram space and cut position controller, be connected with described totalizer, if current RAM byte address exceedes the end address that current endpoint distributes, then the end address delivery continuing to distribute by this end points is as current final end address.Time initial, the final end address of this end points is the start address that this end points distributes.
One RAM interface is read and write enable and is selected recording controller, and produce read-write indicator signal, chip selection signal, writes data, and high low byte instruction, receives the read data of RAM.
One odd bytes address starts controller, and according to the start address that end points distributes, the start address generation odd bytes address of each transmission starts control signal and exports to described pipe control module.
In Fig. 5, high byte effective marker signal, low byte effective marker signal, 8bit/16bit bit reception data, write enable, clock (clk), and reset signal (comprising electrification reset, software reset and USB to reset) sends into described Asynchronous Reception fifo register.Read enable, clock, 8bit/16bit sends data and inputs described asynchronous transmission fifo register.Namely the Read Controller of described Asynchronous Reception fifo register starts read data after described Asynchronous Reception fifo register non-NULL being detected, the high dibit read is high low byte effective index signal, this high low byte effective index signal is given described address ram counter and is carried out byte and add up, and the data of reading give described RAM Read-write Catrol module.The writing controller of described asynchronous transmission fifo register, after the storer receiving described register control module gets out instruction and receives the transmission token packet instruction from pipe control module, start to notify that RAM Read-write Catrol module is from plug-in RAM reading, write asynchronous transmission fifo register, each write 16 Bit datas simultaneously.Described address ram counter adds 1 or add 2 according to the enable and high low byte effective marker signal of reading of Asynchronous Reception fifo register, or all effective situation (because RAM is 16 bit widths) of high low byte that is enable and acquiescence of writing according to asynchronous transmission fifo register adds 2, add 1 in some cases when sending data simultaneously, mainly consider that this sends whether length is odd bytes, whether start address is odd number word.RAM Read-write Catrol module utilizes the base address of RAM to add the value of address ram counter, and as the address ram of 16 bit widths after intercepting lowest bit, attention will utilize end points end address and start address to do modulo operation.RAM Read-write Catrol module utilize the Read Controller of Asynchronous Reception fifo register read the plug-in RAM of enable generation read enable and chip selection signal, what the data that utilize the Read Controller of Asynchronous Reception fifo register to read produced RAM interface control module writes data, the high low byte effective marker signal utilizing the Read Controller of Asynchronous Reception fifo register to read produces the high low byte effective marker of RAM interface control module, utilize the write request of the writing controller of asynchronous transmission fifo register produce read plug-in RAM read enable and chip selection signal, the time delay of the read requests of the writing controller of asynchronous transmission fifo register is utilized to latch the data of plug-in RAM reading, during reading plug-in RAM, high low byte effective marker signal is all effective, give and provide high low byte when described pipe control module reads asynchronous transmission fifo register which byte is effective on earth.
Described device controller device, by the plug-in RAM of RAM interface control module, is convenient to the system integration and application, saves storage space; It is 16bit that RAM exports data-interface, if plug-in RAM is that 16bit is wide, because inside have employed the address ram counter based on byte, in conjunction with the start address of end points, can accomplish by byte(byte) write continuously, save storage space further.
Described device controller device adopts Asynchronous Reception fifo register and asynchronous transmission fifo register to isolate plug-in RAM and USB internal system clock.RAM interface control module is by every 30Mx16 bit rate design.When utmi interface is 16 bit, when the data from main frame are stored in Asynchronous Reception fifo register, the clock of writing of Asynchronous Reception fifo register is 30M, and it is 30M the most slowly that Asynchronous Reception fifo register reads enable speed, reads 16bit at every turn and writes into plug-in RAM.Can read after Asynchronous Reception fifo register non-NULL and write RAM.The data going to main frame are when writing asynchronous transmission fifo register, and writing enable is 30M the most slowly, and each 16 bits read from RAM, write asynchronous transmission fifo register.Described pipe control module each 30Mx16 bit is from described asynchronous transmission fifo register sense data, the high low byte effective marker signal of data is in the process of pipe control inside modules, whether whether the RAM needing to use this transmission is odd number start address and data length is odd bytes, because 16 Bit datas read from RAM when this transmission starts are likely only have high byte effective, 16 Bit datas read from RAM during this end of transmission (EOT) are likely that low byte is effective.When being 8 bit for utmi interface, UTMI clock is 60M, and will carry out spelling number from during the data write Asynchronous Reception fifo register that main frame is next, every two clap spellings data, then write described Asynchronous Reception fifo register.When the data going to main frame read from asynchronous transmission fifo register, 16bit data read by every two 60M clocks.
Described device controller device considers UTMI8bit and 16bit situation and odd bytes, in described RAM interface control module, adopts the Asynchronous Reception fifo register that 18bit is wide, and 16bitRAM interface control module; Can compatible UTMI8bit/16bit bus and odd bytes.High two bit [17:16] of described each address of Asynchronous Reception fifo register represent that high byte is effective or low byte effective, or effectively simultaneously.During described pipe control module write Asynchronous Reception fifo register, by 16 Bit datas and high 2 bits high byte effectively or low byte effective marker signal write Asynchronous Reception fifo register.RAM interface control module is the effective or low byte useful signal reading by the high byte of high 2 bits when reading from asynchronous transmission fifo register, exports as RAM data bus height low byte effective marker signal.Adopt each bag transmission based on the address ram counter of byte in RAM Read-write Catrol module, this address ram counter often wraps before transmission starts and is reset by clearing control signal, retains current bag count value during bag end of transmission (EOT).Arrange the RAM base address controller of the current bag base address of a byte oriented representation in addition, initial base address is the RAM start address of endpoint configurations, after each bag end of transmission (EOT), upgrades the final end address of preserving.If the byte-accessed address of the RAM interface control module of 16 Bit datas, RAM is RAM base address add described address ram counter, final address is RAM byte address low level is removed the RAM interface control module address that can be scaled 16 bits.
For described address ram counter, when UTMI8bit pattern, often receive or send a byte, then add one.When UTMI16bit pattern, often receive a host data when writing to RAM, because during pipe control module write Asynchronous Reception fifo register, by high low byte effective marker signal write Asynchronous Reception fifo register, thus when writing to RAM by the high low byte effective marker signal read by the current value of address ram counter adding 1 or add 2.Sending out data to main frame, when reading from RAM, 2 byte datas read by each 30M clock under normal circumstances, and address ram counter adds 2.When counter addition special consideration in following four kinds of situations.Current transmission bag is odd number byte length, and when last end rests on odd address, address ram counter adds 1 when first time peek; Current transmission bag is odd number byte length, when the last time rests on even bytes address, adds 1 when address ram counter is peeked at end; Current transmission bag is even number byte length, and when the last time rests on odd number byte address, address ram counter adds 1 when start address is peeked, and when end-of-packet, described address counter adds 1; Current transmission bag is even number byte length, and when the last time rests on even number byte, address ram counter all adds 2 when starting and ending.For UTMI16 bit interface address, whether whether the state machine of attention pipe control module will be considered often to wrap when main frame sends data is odd number byte start address and data length is counting byte length, and the high low byte of generation is read enable needs and done corresponding control.In pipe control module, respectively state machine is devised to control end points and popular endpoints (i.e. non-controlling end points), the token packet that the main frame that main basis receives is sent out and endpoint type, produce reading or writing control signal and reading and writing data to RAM interface control module and usb protocol data processing module of data, produce corresponding handshake packet control signal to usb protocol data processing module, generation control and status signal are to register control module.
Described equipment refers to the equipment with usb bus interface, and this device interior has CPU and the physical layer block based on usb bus interface and UTMI bus interface, based on the USB device controller module of UTMI bus interface, and the interface module of other type.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (26)
1. a device controller device, is characterized in that, comprising:
One usb protocol data processing module, is operated in USB2.0 pattern or HSIC pattern for selecting;
One pipe control module, is connected with described usb protocol data processing module, for the treatment of the address decoding of the multiple end points of device interior;
One register control module, with described usb protocol data processing module, pipe control module is connected, each register parameters that the ARM CPU for depositing equipment configures according to link layer protocol;
One AMBA bus from device bus module, be connected with described register control module, and be connected with the ARM CPU of equipment by AMBA bus, according to link layer protocol, parameter configuration is carried out to each register in described register control module for described ARM CPU;
One standard UTMI bus, for connecting USB2.0 physical layer block or HSIC physical layer block.
2. device controller device as claimed in claim 1, is characterized in that, also comprise: a RAM interface control module, be connected with described pipe control module with register module, for plug-in RAM, make RAM system-level integrated time multiplexing.
3. device controller device as claimed in claim 1 or 2, is characterized in that: described usb protocol data processing module, to the dissimilar bag of USB based on utmi interface carry out bag identify receive, group bag sends and cyclic redundancy check (CRC) code CRC check accordingly; Realize the bus state machine of USB power managed agreement; The dissimilar handbag of described USB draws together token packet, packet, handshake packet and spectacle case.
4. device controller device as claimed in claim 1 or 2, it is characterized in that: described pipe control module, according to the Transport endpoint type that current hosts is chosen, reception and the transmission processing of the bag of corresponding end points is carried out according to the steering order of dissimilar endpoint transmission agreement and register control module, produce the interrupt identification and other mark that are used for register control module, produce the Read-write Catrol and data encasement that are used for RAM interface control module; Described Transport endpoint type comprises: control end points, bulk transfer end points, interrupt transfer end points and synchronous transmission end points; Other mark described comprises the length of the bag receiving from host, and transmission and reception bag number indicates, and frame number indicates.
5. device controller device as claimed in claim 1 or 2, is characterized in that:
Described usb protocol data processing module, can be adopted software to be configured by AMBA bus by the ARM CPU of equipment, select to be operated in USB2.0 pattern or HSIC pattern;
Described usb protocol data processing module, the USB mode control signal that also can be produced by external hardware configuration selection is operated in USB2.0 pattern or HSIC pattern; If adopt the mode control signal control model that hardware produces, described device controller device is fixed into USB2.0 pattern or HSIC pattern when integrated or when applying;
Described usb protocol data processing module, one selector switch can also be set, in the mode control signal configuration of hardware generation with under adopting software definition to configure simultaneous situation, select corresponding control model, and select to be operated in USB2.0 pattern or HSIC pattern under corresponding control model.
6. device controller device as claimed in claim 1 or 2, is characterized in that: described AMBA bus, comprises ahb bus and APB bus.
7. device controller device as claimed in claim 1 or 2, is characterized in that: definition HSIC protocols work is in high speed non-transmitting stage and high-speed transfer stage;
The described high speed non-transmitting stage, comprise: between turnoff time, power on period, the HSIC that powers on is enable, during the connection CONNECT that must initiate after the enable rear described device controller device of the HSIC that powers on detects HSIC bus free IDLE, the idle period of time of HSIC bus after a connection CONNECT signal, the reseting period that first time main frame is subsequently initiated, during HSIC bus suspension, between awake period;
The described high-speed transfer stage, comprise: after sending out connection CONNECT signal, host reset enters the high-speed transfer stage after terminating for the first time, HSIC bus is in idle condition subsequently, or data transmission state, or host reset state, until HSIC bus suspension, HSIC bus enters again the high speed non-transmitting stage; HSIC bus also enters the high-speed transfer stage after waking end up.
8. device controller device as claimed in claim 7, is characterized in that:
The corresponding DATA line of linestate [1], the corresponding STROBE line of linestate [0]; In the high speed non-transmitting stage, xcvrselect is 1, linestate [1:0] is reaction { DATA directly, STROBE} state, when being in the high-speed transfer stage, linestate [1:0]=00 represents HSIC bus free, and linestate [1:0]=10 represents HSIC bus reset, and in high speed data transfer process, linestate [1:0]=01 represents that data are in transmission;
Wherein, Linestate is line states signal, reflection HSIC bus state; Xcvrselect is that signal selected by transceiver, and DATA is data, and STROBE is gating signal.
9. device controller device as claimed in claim 1 or 2, is characterized in that: described usb protocol data processing module, comprising: a usb bus status control module, and one receives and sending module based on the USB bag of utmi interface;
The described USB based on utmi interface wraps and receives and sending module, the information of described register control module is received by register interface, receive the external data signal from USB physical layer block by UTMI data bus, realize receiving based on the identification of the dissimilar bag of USB of utmi interface and the transmission of group bag;
Described usb bus status control module, wraps to receive with the described USB based on utmi interface and is connected with sending module, comprising:
One mode controller, under the control of mode control signal, produces mode select signal, shows that work at present is in HSIC pattern or USB2.0 pattern;
One HSIC line states detecting device, the HSIC high-speed transfer line states according to input redefines signal, the output signal of line states signal linestate [1:0] and HISC high-speed transfer stage decision device, produces HSIC state machine control signals;
One USB2.0 line states detecting device, according to the line states signal linestate of input and the output signal of USB2.0 speed decision device, produces USB2.0 state machine control signals;
One counter and time tag produce circuit. and its counter is in the time of certain state for adding up USB2.0 bus or HSIC bus, it is then put corresponding time tag according to the value of counter at corresponding time point that time tag produces circuit;
One HSIC state machine, be connected with time tag generator with described mode controller, HSIC line states detecting device and counter, work is started under the control of described mode select signal, being idle for detecting current HSIC bus, resetting, initiating to connect, transmission, Remote Wake Up, recovers, or suspended state;
One USB2.0 state machine, be connected with time tag generator with described mode controller, USB2.0 line states detecting device and counter, work is started under the control of described mode select signal, idle for detecting current USB2.0 bus, reset, Chirp sends and detects, and wakes up, or suspended state;
One sends connection CONNECT controller, is connected with HSIC state machine, and generation transmission connection CONNECT control signal is defeated by the described USB based on utmi interface and is wrapped reception and sending module, and utmi interface produces the data of correspondence;
One selector switch, be connected with USB2.0 state machine with described mode controller, HSIC state machine, under the control of described mode select signal, USB2.0 pattern or HSIC pattern is operated in for selecting, and select UTMI control signal by described mode select signal and export, this UTMI control signal comprises transceiver selection, terminal selection, operator scheme, hang-up and reset;
One sends Remote Wake Up controller, be connected with USB2.0 state machine with described mode controller, HSIC state machine, the Remote Wake Up control bit accepted from the power managed register in described register control module controls, wrap to the described USB based on utmi interface for generation of Remote Wake Up control signal to receive and sending module, send Remote Wake Up signal to main frame;
One sends and detects high speed speed identification signal Chirp controller, be connected with USB2.0 line states detecting device with described USB2.0 state machine, Chirp-K control signal is produced for USB2.0 high speed reset handshake phase device controller device, and export to the described USB bag delivery and reception module based on utmi interface, and detect by line states signal linestate Chirp-K and the Chirp-J signal replaced that main frame sends subsequently; The Chirp-K signal that device controller device sends shows as the D-of USB two lines than D+ height 800mv, continues 1 millisecond to 7 milliseconds, Chirp-K and the Chirp-J signal that what main frame was initiated subsequently replace; Chirp-K signal shows as the D+ of USB two difference transmission lines than D-line height 800mv, Chirp-J signal shows as the D+ of USB two difference transmission lines than D-line height 800mv, each Chirp-K and Chipr-J μ s signal duration 40 is to 60 μ s, middle uninterrupted; Wherein, D-is data line negative pole, and D+ is data line positive pole;
One USB2.0 speed decision device, be connected with USB2.0 line states detecting device with described USB2.0 state machine, utilize the USB2.0 speed-mode control bit deposited from the mode control register in described register control module, produce high speed or the full speed identification signal of USB2.0, the USB2.0 bus state further under control USB2.0 line states detecting device output corresponding modes; Produce zone bit to interrupt control register simultaneously;
One HSIC high-speed transfer stage decision device, is connected with HSIC line states controller with HISC state machine, produces the high-speed transfer stage identification signal of HISC, the HSIC bus state further under control HSIC line states detecting device output corresponding modes;
One USB reset controller, according to HSIC state machine, the output of USB2.0 state machine and mode controller produces the reseting controling signal of usb bus, controls in described device controller device except the interrupt control register of register control module and mode control register, and remainder resets.
10. device controller device as claimed in claim 9, is characterized in that:
Described identify to receive comprise the decoding of Packet type mark domain, the extraction of device address and device interior end-point addresses, separate CRC code, frame number is extracted, the identification of utmi interface valid data and be converted to the high low byte of device controller device inner band effective marker;
Described group of bag sends the coding comprising the Packet type mark domain of handshake packet and packet, height byte from described pipe control module counts to the data conversion of utmi interface, the coding of CRC code, USB2.0 agreement is sent for high speed speed identification signal Chirp-K according to sending request of described usb bus status control module, send the CONNECT signal that connects of HSIC agreement, send Remote Wake Up signal.
11. device controller devices as claimed in claim 1 or 2, it is characterized in that, described register control module, comprising:
One address decoder, for according to the described address exported from device bus module, reads or writes Warning Mark, select signal, what produce the inner corresponding registers of described register control module reads enable signal, or write enable signal, and described register control module internal register physical address;
One Read Controller, reads enable and address for what produce according to described address decoder, writes described register control module corresponding registers by from the described supplemental characteristic from device bus module;
One writing controller, writes enable and address for what produce according to described address decoder, is read into by the supplemental characteristic of described register control module corresponding registers described from device bus module;
One interruptable controller, is converted to the Status Flag of the register of described register control module for the mark that detects from described usb protocol data processing module and pipe control module;
One mode control register, for depositing mode control signal, represents that the pattern of current peripheral work is HISC pattern or USB2.0 pattern; Deposit the enable control signal of HISC; Software reset's control bit is set simultaneously, register system Software reset signal; Deposit test mode signal; Deposit USB2.0 velocity mode signal, represent that USB2.0 is high speed or full speed; Deposit the USB2.0 software plug control bit of setting;
One end points n control register group, it comprises address assignment register, for depositing the controling parameters of end points n;
One software and hardware is sent out and is connected CONNECT control register, sends out connection CONNECT control signal for depositing software and hardware, represent in HISC pattern configurations it is that connection CONENCT pattern sent out by software, or connection CONNECT pattern is sent out automatically by hardware;
One HSIC high-speed transfer line states redefines register, redefines signal for depositing HSIC high-speed transfer line states;
One HSIC physical layer block High Speed I/O delays time to control register, for depositing HISC physical layer block High Speed I/O delay control signal;
One interrupt control register, for depositing the enable and usb bus state interrupt mark of usb bus state interrupt;
One device address register, for depositing the device address signal of usb protocol data processing module described in software merit rating;
One frame number status register, for depositing the frame number receiving main frame transmission from described usb protocol data processing module;
One scratchpad register, is operated in the test mode signal of different test pattern for depositing software merit rating device controller device, and is transferred to described pipe control module;
One power managed register, whether detect that the 3ms free time enters suspended state for depositing software controlled device control device, software can control described device controller device and exit suspended state; Produce Remote Wake Up signal, initiate Remote Wake Up by device controller device described in software control.
12. devices as claimed in claim 11, it is characterized in that, the controling parameters of described end points n comprises: the start and end address of each end points in RAM, end points storer resets and controls, the enable control of end points, endpoint type configures, endpoint number, end points direction, the upset of end-point data Packet type controls, in endpoint transmission, the long and short handbag length of maximum bag and respective enable control, very fast high-bandwidth block number configures, dissimilar transmission or receive successful interrupt identification in the enable and transmission of dissimilar bag Transmission in the transmission of end points bag, stopping handshake packet being sent out in software control, for control end points special setting register in register control module, the foundation bag of 8 bytes that the establishment stage controlling end points receives is placed in this special setting register, controls end points and sends stopping bag by software control and send negative response handshake packet.
13. devices as claimed in claim 11, is characterized in that: if hardware is sent out automatically connect CONNECT signal, then described device controller device detect and power on after HISC bus free automatically initiate to connect CONNECT; If connection sent out by software, CONNECT then sends control bit in the initiation moment by software merit rating; Define in control bit and connect CONNECT cut to lengthen bit, scope is from 1 to 16 HSIC data transfer cycles.
14. devices as claimed in claim 11, is characterized in that: described HSIC high-speed transfer line states redefines signal, redefines the implication receiving line states signal linestate on high-speed transfer rank; Default mode, the high-speed transfer stage, HSIC bus reset state linestate was 10(K), idle condition linestate is 00, i.e. SE0; Redefine pattern, the high-speed transfer stage, HSIC bus reset state linestate was 00, i.e. SE0, and during idle condition, linestate is 10, i.e. K.
15. devices as claimed in claim 11, it is characterized in that: described HISC PHY High-speed I/O delay control signal, the time delay of the input buffering of High Speed Analog I/O, gating STROBE and data DATA in definition adjustment HSIC physical layer block, the multiple time delay unit of definable.
16. devices as claimed in claim 11, is characterized in that: described interrupt identification, comprises; Frame start interrupt, reset interrupt, hang up interrupt, recover interrupt, USB2.0 high speed detection interrupt, HSIC power on idle-detection interrupt, HSIC initiates disconnecting.
17. devices as claimed in claim 11, it is characterized in that: described software and hardware is sent out and connected CONNECT control register, be defaulted as described device controller device to power on, enable and after HSIC bus free a period of time being detected, automatically send out connection signal CONNECT to main frame, length is defaulted as 4 bits, and the transmission cycle of a bit is 2.083ns, the i.e. message transmission rate 480M bits per second of HSIC, meets initial stage HSIC standard; Can be defined by software and send out the connection signal CONNECT of 5 ~ 8 bit lengths or the connection signal CONNECT of 5 ~ 16 bit lengths, adapt to the connection signal CONNECT being greater than 2 gating STROBE cycles of new standard regulation.
18. devices as claimed in claim 11, it is characterized in that: after the parameter value of described HSIC physical layer block High Speed I/O delays time to control register has configured, directly output to the port of described device controller device, for the High Speed I/O time delay of control HISC physical layer block; Adopt gating STROBE and data DATA two groups of control lines, often organize 8 bits, realize the Adjustment precision of control 256 step-lengths.
19. devices as claimed in claim 2, it is characterized in that, described RAM interface control module, comprising:
One Asynchronous Reception fifo register, for depositing the data being sent to described device controller device by main frame from described pipe control module;
The Read Controller of one Asynchronous Reception fifo register, for reading the data of described Asynchronous Reception fifo register, prepares the RAM that the described device controller device of write is plug-in;
One asynchronous transmission fifo register, for depositing the data being issued main frame by described device controller device from described plug-in RAM;
The writing controller of one asynchronous transmission fifo register, for writing described asynchronous transmission fifo register by the data from described plug-in RAM;
One RAM Read-write Catrol module, it comprises:
One address ram counter, by the byte stored count of transmission during for transmitting at every turn, resets when each transmission starts;
One RAM base address controller, for recording the final end address after each end of transmission (EOT), preserves by byte; Upgrade preserved final end address after each end of transmission (EOT) and add that the current transmission byte length just terminated is as preparation address ram with the final end address after last end of transmission (EOT), namely the final end address upgraded, initial base address is the RAM start address of endpoint configurations;
One totalizer, is added the output of described address ram counter and the output of RAM base address controller, produces RAM byte address, as preparation address ram;
One ram space and cut position controller, be connected with described totalizer, if current RAM byte address exceedes the end address that current endpoint distributes, then the end address delivery continuing to distribute by this end points is as current final end address; Time initial, the final end address of this end points is the start address that this end points distributes;
One RAM interface is read and write enable and is selected recording controller, and produce read-write indicator signal, chip selection signal, writes data, and high low byte instruction, receives the read data of RAM;
One odd bytes address starts controller, and according to the start address that end points distributes, the start address of each transmission produces odd bytes address and starts control signal, and exports to described pipe control module.
20. devices as described in claim 2 or 19, is characterized in that: described RAM deposits continuously by byte byte.
21. devices as claimed in claim 19, is characterized in that: described Asynchronous Reception fifo register and described plug-in RAM and the USB internal system clock of asynchronous transmission fifo register isolation; RAM interface control module is by every 30Mx16 bit rate design; When utmi interface is 16 bit, when the data from main frame are stored in Asynchronous Reception fifo register, the clock of writing of Asynchronous Reception fifo register is 30M, and it is 30M the most slowly that Asynchronous Reception fifo register reads enable speed, reads 16bit at every turn and writes into plug-in RAM; Can read after Asynchronous Reception fifo register non-NULL and write RAM.
22. devices as claimed in claim 19, is characterized in that: described Asynchronous Reception fifo register is 18bit bit wide; High two bit [17:16] of described each address of Asynchronous Reception fifo register represent that high byte is effective or low byte effective, or effectively simultaneously; During described pipe control module write Asynchronous Reception fifo register, by 16 Bit datas and high 2 bits high byte effectively or low byte effective marker signal write Asynchronous Reception fifo register; RAM interface control module is the effective or low byte useful signal reading by the high byte of high 2 bits when reading from asynchronous transmission fifo register, exports as RAM data bus height low byte effective marker signal.
23. devices as claimed in claim 19, is characterized in that: described address ram counter, when UTMI8bit pattern, often receive or send a byte byte, then add one; When UTMI16bit pattern, often receive a host data when writing to RAM, make the current value of described address ram counter adds 1 or add 2 by the high byte effective marker signal read or low byte effective marker signal;
When sending out data to main frame, when reading from RAM, 2 byte datas read by each 30M clock under normal circumstances, and described address ram counter adds 2;
Current transmission bag is odd bytes byte length, and when last end rests on odd address, described address ram counter adds 1 when first time peek;
Current transmission bag is odd bytes byte length, when the last time rests on even bytes address, adds 1 when described address ram counter is peeked at end;
Current transmission bag is even bytes byte length, and when the last time rests on odd number byte address, described address ram counter adds 1 when start address is peeked, and when end-of-packet, described address ram counter adds 1;
Current transmission bag is even bytes byte length, and when the last time rests on even number byte, described address ram counter all adds 2 when starting and ending.
24. devices as claimed in claim 1 or 2, it is characterized in that: to control end points and popular endpoints design point machine respectively in described pipe control module, the token packet sent out according to the main frame received and endpoint type, produce reading or writing control signal and reading and writing data to described RAM interface control module and usb protocol data processing module of data, produce corresponding handshake packet control signal to usb protocol data processing module, generation control and status signal are to register control module.
25. devices as claimed in claim 1 or 2, is characterized in that: reserved software interface redefines the reach the standard grade free time of state interface linestate and the representative value software of reset of UTMI bus under entering the high speed data transfer stage.
26. devices as claimed in claim 1 or 2, it is characterized in that: control whole described device controller device by the line states signal linestate of physical layer block and be operated in the free time, reset, hang up, recover, or wake-up states, and carry out the conversion between state, the key signal of control UTMI bus further.
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| CN106462534B (en) * | 2014-06-16 | 2019-07-16 | 高通股份有限公司 | Link layer is to physical layer (PHY) serial line interface |
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| CN112770046B (en) * | 2020-12-21 | 2022-04-01 | 深圳市瑞立视多媒体科技有限公司 | Generation method of control SDK of binocular USB camera and control method of binocular USB camera |
| CN114615425A (en) * | 2020-12-21 | 2022-06-10 | 深圳市瑞立视多媒体科技有限公司 | Method for generating control SDK (software development kit) of binocular USB camera and method for controlling binocular USB camera |
| CN114615424A (en) * | 2020-12-21 | 2022-06-10 | 深圳市瑞立视多媒体科技有限公司 | Method for generating control SDK of binocular USB camera and method for controlling binocular USB camera |
| CN114615425B (en) * | 2020-12-21 | 2024-04-16 | 深圳市瑞立视多媒体科技有限公司 | Control method of binocular USB camera |
| WO2023174086A1 (en) * | 2022-03-14 | 2023-09-21 | 苏州浪潮智能科技有限公司 | Universal interface register system and rapid generation method |
| CN114637718A (en) * | 2022-05-19 | 2022-06-17 | 南京沁恒微电子股份有限公司 | USB multiplexing single-wire interface unit, chip and communication system |
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