CN104679629A - Debugging test circuit and debugging test method thereof - Google Patents
Debugging test circuit and debugging test method thereof Download PDFInfo
- Publication number
- CN104679629A CN104679629A CN201310648781.0A CN201310648781A CN104679629A CN 104679629 A CN104679629 A CN 104679629A CN 201310648781 A CN201310648781 A CN 201310648781A CN 104679629 A CN104679629 A CN 104679629A
- Authority
- CN
- China
- Prior art keywords
- unit
- signal
- serial bus
- universal serial
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Information Transfer Systems (AREA)
Abstract
Disclosed is a debugging test circuit. The debugging test circuit is arranged on a main board and comprises a central processing unit, a multi-task processing unit, a judgment unit and a universal serial bus unit, the multi-task processing unit is coupled with the central processing unit through a debugging channel and a universal serial bus channel, the judgment unit is coupled with the multi-task processing unit, the universal serial bus unit is coupled with the multi-task processing unit and the judgment unit, when the universal serial bus unit receives an identification signal, the identification signal is distinguished through the judgment unit, when the identification signal is distinguished and belongs to a set signal, the judgment unit outputs a first signal to the multi-task processing unit, and thereby, the multi-task processing unit can perform switching to be communicated with a debugging channel. According to the debugging test circuit and the debugging test method thereof, the judgment unit performs judgment, when the judgment result is the first signal, the multi-task processing unit is communicated with a universal asynchronous transceiver channel, and thereby, effects of saving time, lowering costs and improving convenience of detection of the main board are achieved.
Description
Technical field
The present invention relates to a kind of debug test circuit and debug method of testing thereof, particularly relate to a kind of the debug test circuit and the debug method of testing thereof that are arranged at mainboard.
Background technology
Along with the progress of science and technology, the electronic equipments such as computing machine, counter, flat computer, notebook computer, action communication device, personal digital assistant (PDA), handheld device, medical information platform, medical information care platform or servo host are also increasingly gradually many, therefore, above-mentioned electronic equipment has been popularized for office, group, enterprise, family or individual to use.For example, common people can operate tablet computing machine or intelligent mobile phone expediently, when going out can easily logging onto the Internet, see film, the activity such as listen to the music, see e-book, look into map or play games.
But, when the program of above-mentioned electronic device build-in, download, software or firmware (Firmware) are because of design defect or suffer virus to cause defect, or the hardware in above-mentioned electronic equipment, when the electronic components of circuit board or firmware etc. etc. are because of loss or bad defect, above-mentioned electronic equipment will break down, generally speaking, the electronic equipment of fault can send factory to keep in repair by people, therefore, staff first must dismantle casing or the shell of above-mentioned electronic equipment or unclamp many locking screws, to detect the mainboard installed in casing further, carry out debug operation thus, therefore detection time or the servicing time of staff is increased, even, there is the casing of portions of electronics equipment need use special instrument to dismantle, wherein, such as these speciality tools such as hexagon wrench or double off-set spanners are not necessarily configured at maintenance place, therefore staff is caused to detect the inconvenience of mainboard.
Summary of the invention
Technical matters to be solved by this invention is, a kind of debug test circuit and debug method of testing thereof is provided for the deficiencies in the prior art, wherein, the present invention reserves USB (universal serial bus) in electronic device exterior to carry out debug operation by described mainboard, reaches the convenience saved time, reduce costs and promote and detect mainboard thus.
The present invention proposes a kind of debug test circuit, is arranged at a mainboard, comprises a CPU (central processing unit), a multitasking unit, a judging unit and a USB (universal serial bus) unit; Multitasking unit passes through a debug channel and a USB (universal serial bus) channel, to couple CPU (central processing unit); Judging unit couples multitasking unit; USB (universal serial bus) unit is coupled to multitasking unit and judging unit; Wherein, when USB (universal serial bus) unit receives an identification signal, identification signal differentiates via judging unit, when determining identification signal and belonging to a setting signal, judging unit exports one first signal to multitasking unit, to make multitasking unit switched conductive one debug passage.
The present invention also provides a kind of debug method of testing, be suitable for detection one mainboard, this mainboard has a CPU (central processing unit), one multitasking unit, one judging unit and a USB (universal serial bus) unit, this multitasking unit is coupled to this CPU (central processing unit), between this judging unit and this USB (universal serial bus) unit, and this multitasking unit is by a debug channel and a USB (universal serial bus) channel, to couple this CPU (central processing unit), this debug method of testing comprises: when USB (universal serial bus) unit receives an identification signal, judge whether identification signal is a setting signal, if, judging unit exports one first signal to multitasking unit, and multitasking unit according to the first signal with conducting one debug passage.
Debug test circuit of the present invention, be arranged at mainboard, therefore, user by USB (universal serial bus), with grafting debug test circuit of the present invention, the wherein identification signal that exports according to USB (universal serial bus) of judging unit, with differentiate whether be the first signal, when the result differentiated is the first signal, multitasking unit, by conducting UART Universal Asynchronous Receiver Transmitter channel, reaches the convenience saved time, reduce costs and promote and detect mainboard thus.
Above general introduction and ensuing embodiment are to further illustrate technological means of the present invention and reaching technique effect, however the embodiment that describes and accompanying drawing only provide reference that use is described, be not used for being limited the present invention.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of debug test circuit of the present invention;
Fig. 2 is the circuit diagram of the debug test circuit according to Fig. 1;
Fig. 3 is the identification running table of the debug test circuit according to Fig. 2;
Fig. 4 is the process flow diagram of debug method of testing of the present invention.
[description of reference numerals]
1: debug test circuit
9: computer installation
10: CPU (central processing unit)
12: multitasking unit
14: judging unit
140: alternative route
OP1: the first comparer
C11: first input end
C12: the second input end
CO1: the first output terminal
OP2: the second comparer
C21: first input end
C22: the second input end
CO2: the second output terminal
16: USB (universal serial bus) unit
18: conversion equipment
181: the first Connection Elements
182: the second Connection Elements
U1: debug passage
U2: universal serial bus channel
OUTC: output channel
R1 ~ R4: resistance
IDV: identification signal
VDD: operating voltage
V1: the first voltage
V2: the second voltage
C1 ~ C6: electric capacity
D1: the first diode
D2: the second diode
DGND: earth terminal
S401 ~ S413: process step
Embodiment
Fig. 1 is the functional block diagram of debug test circuit of the present invention, and as shown in Figure 1, a kind of debug test circuit 1, comprises CPU (central processing unit) 10, multitasking unit 12, judging unit 14, USB (universal serial bus) unit 16 and a conversion equipment 18.
In practice, multitasking unit 12 couples USB (universal serial bus) unit 16, judging unit 14 and CPU (central processing unit) 10, and CPU (central processing unit) 10, multitasking unit 12, judging unit 14 and USB (universal serial bus) unit 16 are arranged on mainboard (Mother Board), and conversion equipment 18 is electrically connected USB (universal serial bus) unit 16 and computer installation 9 in external mode, wherein, the embedded program of mainboard is by USB (universal serial bus) unit 16 written-out program information, and show to export computer installation 9 to via conversion equipment 18, therefore, user is by the information shown by computer installation 9, to detect the defect (bug) of mainboard.
Furthermore, mainboard is such as having the computer plate of reduced instruction set computer (RISC) or advanced reduced instruction set computer (ARM), circuit board or printed circuit board (PCB), and be arranged at computing machine, counter, flat computer, notebook computer, action communication device, personal digital assistant (PDA), handheld device, medical information platform, the electronic equipments such as medical information care platform or servo host, the embedded program of another mainboard is such as built-in debug trace routine, the program compiler of initialize routine or support C Plus Plus and/or assembly language, the present embodiment does not limit form and the purposes of mainboard.
CPU (central processing unit) 10 is such as x86 processor, RISC processor (RISC Processor), advanced RISC processor (ARM Processor) or other kind processors, wherein CPU (central processing unit) 10 is such as by Advanced Micro Devices, TI, Samsung, the processor that the companies such as Cortex or Intel manufacture, and the exportable universal serial bus signal of CPU (central processing unit) 10 (USB Signal) and UART Universal Asynchronous Receiver Transmitter signal (Universal Asynchronous Receiver Transmitter Signal, UART Signal) to multitasking unit 12, the present embodiment does not limit the form of CPU (central processing unit) 10.
Multitasking unit 12 couples CPU (central processing unit) 10 and USB (universal serial bus) unit 16.In practice, multitasking unit 12 such as 2-1MUX, 3-1MUX, M-NMUX (M, N be greater than 2 positive integer), export and select multiplexer (DMUX) or PI3USB10 multiplexer, the present embodiment does not limit the form of multitasking unit 12.Wherein, have two channels between multitasking unit 12 and CPU (central processing unit) 10, one of them channel is in order to export or to receive universal serial bus signal, and D+, D-signal of such as USB (universal serial bus) can transmit on channel; One other channel is in order to export UART Universal Asynchronous Receiver Transmitter signal, and TX and the RX signal of such as UART Universal Asynchronous Receiver Transmitter can transmit on channel.
Specifically, multitasking unit 12 is by debug channel U1 and USB (universal serial bus) channel U2, to be electrically connected CPU (central processing unit) 10, and multitasking unit 12 is such as 2-1MUX, multitasking unit 12 is selected from two input signals: wherein an input signal is universal serial bus signal, and another input signal is UART Universal Asynchronous Receiver Transmitter signal, therefore, multitasking unit 12 can select two input signals one of them, and to be exported by USB (universal serial bus) unit 16.
For example, the input end of multitasking unit 12 couples CPU (central processing unit) 10, so, the input end of multitasking unit 12 is by the UART Universal Asynchronous Receiver Transmitter signal of the universal serial bus signal or TX/RX that receive D+/D-, wherein, the output terminal of multitasking unit 12 couples USB (universal serial bus) unit 16, so, multitasking unit 12 can according to first or secondary signal, to select USB (universal serial bus) channel U2 to export the universal serial bus signal of D+/D-, or select debug passage U1 to export with the UART Universal Asynchronous Receiver Transmitter signal of TX/RX, and the UART Universal Asynchronous Receiver Transmitter signal of the universal serial bus signal of D+/D-or TX/RX will transfer to computer installation 9 via USB (universal serial bus) unit 16.
In other embodiments, multitasking unit 12 such as selects multiplexer (DMUX) for exporting, wherein the input end of multitasking unit 12 couples USB (universal serial bus) unit 16, so, the input end of multitasking unit 12 will receive universal serial bus signal, wherein, the output terminal of multitasking unit 12 couples CPU (central processing unit) 10, multitasking unit 12 can according to the first signal or secondary signal, to select the UART Universal Asynchronous Receiver Transmitter signal of the universal serial bus signal or TX/RX that export D+/D-to CPU (central processing unit) 10, the present embodiment does not limit the operation shape of multitasking unit 12 and CPU (central processing unit) 10.
Judging unit 14 couples multitasking unit 12 and USB (universal serial bus) unit 16.In practice, when the first Connection Element 181 grafting USB (universal serial bus) unit 16 of conversion equipment 18, one of USB (universal serial bus) unit 16 identifies pin by output one identification signal to judging unit 14, and judging unit 14 is in order to judge identification signal, wherein identification signal is such as meeting the voltage signal of universal serial bus communications agreement, when this voltage signal meets the preset signals of universal serial bus communications agreement, CPU (central processing unit) 10 will according to preset signals to distinguish master slave relation.
For example, when being plugged in the USB (universal serial bus) unit 16 on mainboard when flash memory device, it is preset signals that judging unit 14 determines identification signal, then CPU (central processing unit) 10 will according to preset signals to distinguish master slave relation, the USB (universal serial bus) unit 16 of such as mainboard end is master port (Host Port), and the flash memory device of circumscribed is such as from port (Device Port), therefore, when flash memory device grafting USB (universal serial bus) of the present invention unit 16, judging unit 14 can according to the identification signal meeting preset signals, to determine flash memory device, and distinguish the master slave relation of flash memory device and mainboard.
Judging unit 14 comprises an alternative route 140, and alternative route 140 has one first voltage and one second voltage, and the first voltage is greater than the second voltage.In practice, alternative route 140 is such as circuit or chip, logical integrated circuit, chip or logic judging circuit or the chip of one or more comparer composition, the present embodiment does not limit the form of alternative route 140, wherein, first voltage is such as upper voltage limit, and the second voltage is such as lower voltage limit, and wherein upper voltage limit is such as 3,2.5 or 2.2 volts, and lower voltage limit is such as 0.5,0.8 or 1.1 volt, the present embodiment does not limit the numerical value of first and second voltage.
USB (universal serial bus) unit 16 is coupled to multitasking unit 12 and judging unit 14.In practice, USB (universal serial bus) unit 16 can be the transmission interface of USB (universal serial bus) (USB), mini USB (universal serial bus) (Mini USB), micro universal serial bus (Micro USB) or other signal transmissions, and the present embodiment does not limit the form of USB (universal serial bus) unit 16.
Next, when USB (universal serial bus) unit 16 receives an identification signal, identification signal differentiates via judging unit 14, when determining identification signal and belonging to a setting signal, judging unit 14 exports one first signal to multitasking unit 12, to make multitasking unit 12 switched conductive one debug passage U1.
In practice, setting signal meets the communication protocol of USB (universal serial bus), and setting signal is the voltage signal between the first voltage and the second voltage, and in other words, setting signal is the voltage signal between upper voltage limit and lower voltage limit.Therefore, when to determine identification signal be setting signal to judging unit 14, judging unit 14 exports the first signal to multitasking unit 12, wherein the first signal is the signal that instruction multitasking unit 12 selects UART Universal Asynchronous Receiver Transmitter channel, therefore, user by USB (universal serial bus) to carry out debug operation.
In addition, when USB (universal serial bus) unit 16 receives identification signal, identification signal differentiates via judging unit 14, when determining identification signal and belonging to a preset signals, judging unit 14 exports a secondary signal to multitasking unit 12, to make multitasking unit 12 switched conductive one universal serial bus channel U2.In practice, when identification signal is greater than the first voltage through differentiation, or identification signal is when being less than the second voltage through differentiation, it is preset signals that judging unit 14 determines identification signal, and therefore, judging unit 14 exports secondary signal to multitasking unit 12, wherein secondary signal is the signal that instruction multitasking unit 12 selects USB (universal serial bus) channel U2, therefore, user by USB (universal serial bus), to carry out the data access operation of the plug and play of general USB (universal serial bus).
Debug test circuit 1 also comprises a conversion equipment 18, has one first Connection Element 181 and one second Connection Element 182, wherein the first Connection Element 181 in order to grafting USB (universal serial bus) unit 16, second Connection Element 182 in order to grafting one computer installation 9.In practice, conversion equipment 18 is in order to be converted to the signal of RS-232 interface by UART Universal Asynchronous Receiver Transmitter signal, wherein the first Connection Element 181 is such as USB (universal serial bus) (USB), mini USB (universal serial bus) (Mini USB), the transmission interface of micro universal serial bus (Micro USB) or other signal transmissions, and the first Connection Element 181 coordinates the form of USB (universal serial bus) unit 16 and designs, second Connection Element 182 is such as RS-232, the form of the terminal prot of the second Connection Element 182 coupled computer device 9 and designing, the present embodiment does not limit the form of conversion equipment 18.
Following theory, further illustrates the running of thin portion and the circuit of debug test circuit 1.
Fig. 2 is the circuit diagram of the debug test circuit according to Fig. 1, as shown in Figure 2, one multitasking unit 12 and a judging unit 14, wherein judging unit 14 comprises an alternative route 140, and alternative route 140 is made up of multiple comparer OP1, OP2, multiple resistance R1 ~ R4, multiple electric capacity C1 ~ C4 and multiple diode D1, D2.
Furthermore, alternative route 140 comprises one first comparer OP1 and one second comparer OP2, the first input end C11 of the first comparer OP1 couples one first voltage, the second input end C12 of the first comparer OP1 is in order to receive identification signal IDV, the output terminal of the first comparer OP1 couples one first diode D1, the first input end C21 of the second comparer OP2 is in order to receive identification signal IDV, the second input end C22 of the second comparer OP2 couples the second voltage, and the output terminal of the second comparer OP2 couples one second diode D2.
Wherein, first or second comparer OP1, OP2 is such as operational amplifier (Operational Amplifier), wherein first input end C11, C21 is such as non-inverting input, and second input end C12, C22 is such as inverting input, therefore, first or second comparer OP1, OP2 in order to compare the voltage of non-inverting input and inverting input, and generates the signal relative with this result, and the present embodiment does not limit the form of first or second comparer OP1, OP2.
In simple terms, the first comparer OP1 in order to compare the voltage of first and second input end C11, C12, such as, compares the voltage of upper voltage limit and identification signal IDV, to generate the signal relative with this result.When the voltage of non-inverting input is greater than the voltage of inverting input, comparer OP1, OP2 can export a high logic level, otherwise when the voltage of non-inverting input is less than the voltage of inverting input, comparer OP1, OP2 can export a low logic level.
In like manner known, the second comparer OP2 in order to compare the voltage of first and second input end C21, C22, the voltage of such as relative discern signal IDV and lower voltage limit, and generate the signal relative with this result.First and second comparer OP1, OP2 have identical function, do not repeat them here.
In addition, first or second diode D1, D2 is such as voltage stabilizing diode, and the present embodiment does not limit the form of first or second diode D1, D2.The cathode terminal of the first diode D1 couples the first output terminal CO1 of the first comparer OP1, the cathode terminal of the second diode D2 couples the first output terminal CO1 of the second comparer OP2, and the anode tap of first and second diode D1, D2 couples the SEL pin of multitasking unit 12.
The SEL pin of multitasking unit 12 couples judging unit 14, Y0 and the Y1 pin of multitasking unit 12 couples USB (universal serial bus) unit 16, P1 and the P2 pin of multitasking unit 12 is in order to export or to receive universal serial bus signal, and P3, P4 pin is in order to receive UART Universal Asynchronous Receiver Transmitter signal, wherein the first signal or secondary signal are from judging unit 14, via SEL pin to transfer to multitasking unit 12, therefore, multitasking unit 12 can according to the first signal or secondary signal, and by Y0 and Y1 pin to export universal serial bus signal or UART Universal Asynchronous Receiver Transmitter signal.
In addition, in Fig. 2, the input node of identification signal IDV is coupled to a trimmable resistance (not shown), and one end ground connection of this trimmable resistance, the other end of this trimmable resistance couples a conventional resistive (not shown), wherein, this conventional resistive impedance value be a fixed numbers size, and this conventional resistive the other end couple an operating voltage VDD, therefore, trimmable resistance and conventional resistive are by formation one bleeder circuit, wherein, the large young pathbreaker of impedance value of trimmable resistance affects the voltage value of identification signal IDV, such as, when the impedance value of trimmable resistance is 10K ohm, the voltage value of identification signal IDV is 2.06 volts, when the impedance value of trimmable resistance is 1K ohm, the voltage value of identification signal IDV is 2.3 volts, thus, user is by adjusting the impedance value of trimmable resistance, to make the voltage value of identification signal IDV between the first voltage and the second voltage, so, user can whenever and wherever possible by adjustment trimmable resistance, to detect mainboard and to carry out debug operation.
Fig. 3 is the identification running table of the debug test circuit according to Fig. 2.As Fig. 3 and with reference to shown in figure 2, for convenience of description, first voltage of the present invention is such as 2.2 volts, second voltage is such as 1.1 volts, therefore, the voltage of the non-inverting input of the first comparer OP1 is 2.2 volts, and the voltage of the inverting input of the second comparer OP2 is 1.1 volts, wherein user by USB (universal serial bus) with grafting USB (universal serial bus) unit 16 of the present invention, and the present embodiment is with 3 volts, the voltage signal of the identification of 0 volt and 1.5 volts illustrates, those skilled in the art can freely design first and second voltage, the voltage value of identification signal IDV.
Under the operating conditions of state one, it is such as the voltage of the identification signal IDV of 3V that judging unit 14 receives, the voltage that wherein the first comparer OP1 compares non-inverting input is less than the voltage of inverting input, and therefore, the first comparer OP1 generates the signal of a low logic level; The voltage that another second comparer OP2 compares non-inverting input is greater than the voltage of inverting input, and therefore, the second comparer OP2 generates the signal of a high logic level.
The SEL pin of multitasking unit 12 can receive the signal of a low logic level and a high logic level, wherein the signal of low logic level and high logic level is such as unequal signal, and these not identical signals above-mentioned are such as secondary signal, therefore, multitasking unit 12 according to secondary signal to select USB (universal serial bus) channel, and this function above-mentioned is USB (universal serial bus)-client (USB-Client), distinguishing mainboard end is thus master port, and flash memory device end is from port.
Next, under the operating conditions of state two, it is such as the voltage of identification signal IDV of 0V that judging unit 14 receives, and the voltage that wherein the first comparer OP1 compares non-inverting input is greater than the voltage of inverting input, therefore, the first comparer OP1 generates the signal of a high logic level; The voltage that another second comparer OP2 compares non-inverting input is less than the voltage of inverting input, and therefore, the second comparer OP2 generates the signal of a low logic level.
The SEL pin of multitasking unit 12 can receive the signal of a high logic level and a low logic level, wherein the signal of high logic level and low logic level is such as unequal signal, and these not identical signals above-mentioned are such as secondary signal, therefore, multitasking unit 12 according to secondary signal to select USB (universal serial bus) channel, and this function above-mentioned is USB (universal serial bus)-host side (USB-Host), distinguishing mainboard end is thus from port, and flash memory device end is master port.
Afterwards, under the operating conditions of state three, it is such as the voltage of identification signal IDV of 1.5V that judging unit 14 receives, and the voltage that wherein the first comparer OP1 compares non-inverting input is greater than the voltage of inverting input, therefore, the first comparer OP1 generates the signal of a high logic level; The voltage that another second comparer OP2 compares non-inverting input is greater than the voltage of inverting input, and therefore, the second comparer OP2 generates the signal of a high logic level.
The SEL pin of multitasking unit 12 can receive the signal of two high logic levels, wherein the signal of these two high logic levels is such as identical signal, and these identical signals above-mentioned are the first signal, therefore, multitasking unit 12 according to the first signal to select UART Universal Asynchronous Receiver Transmitter channel, and this function above-mentioned is debug-UART Universal Asynchronous Receiver Transmitter (Debug-UART), therefore user by computer installation 9 to carry out debug operation.
Fig. 4 is the process flow diagram of debug method of testing of the present invention, and if Fig. 4 is also with reference to shown in figure 1, a kind of debug method of testing, is applicable to detection one mainboard, comprises:
Step 401, judges whether USB (universal serial bus) unit 16 receives an identification signal.In practice, user is by flash memory device or the device with USB (universal serial bus), during with grafting USB (universal serial bus) of the present invention unit 16, flash memory device or the device with USB (universal serial bus) will produce identification signal, and be transferred to judging unit 14, and judging unit 14 can differentiate whether receive identification signal, if so, then carry out step 403; If not, then USB (universal serial bus) unit 16 of the present invention still maintains virgin state or armed state.
Step 403, judges whether identification signal is a setting signal.In practice, judging unit 14 can according to identification signal, to differentiate that whether this identification signal is for setting signal, wherein differentiate that the condition of setting signal is, the voltage of this identification signal, between the first voltage and the second voltage, when the judged result of judging unit 14 is for being, then carry out step 405, if when the judged result of judging unit 14 is no, then carry out step 409.
Step 405, judging unit 14 exports one first signal to multitasking unit 12.In practice, the judged result of step 403 is yes, represent that USB (universal serial bus) unit 16 of the present invention is plugged into the computer installation 9 that carries out debug operation, therefore, judging unit 14 exports the first signal to multitasking unit 12, and wherein the first signal is the signal that instruction multitasking unit 12 selects UART Universal Asynchronous Receiver Transmitter channel.
Step 407, multitasking unit 12 according to the first signal with conducting one debug passage U1.In practice, UART Universal Asynchronous Receiver Transmitter channel is in order to carry out the channel of debug operation, therefore, when the U1 conducting of debug passage, the above-mentioned computer installation 9 carrying out debug operation can receive the debugging information of CPU (central processing unit) 10, such as, be the debugging information of TX/RX, therefore, user can dismounting casing, and reserves USB (universal serial bus) unit 16 in electronic device exterior to carry out debug operation by mainboard, promotes the convenience of debug operation thus.
Step 409, judges whether identification signal is a preset signals.In practice, judging unit 14 can according to identification signal, to differentiate that whether this identification signal is for preset signals, wherein differentiate that the condition of preset signals is, the voltage of this identification signal is greater than the first voltage, or the voltage of this identification signal is less than the second voltage, when the judged result of judging unit 14 is for being, then carry out step 411, if when the judged result of judging unit 14 is no, then USB (universal serial bus) unit 16 of the present invention still maintains virgin state or armed state.
Step 411, judging unit 14 exports a secondary signal to multitasking unit 12.In practice, the judged result of step 409 is yes, represent that USB (universal serial bus) unit 16 of the present invention is plugged into a flash memory device, therefore, judging unit 14 exports secondary signal to multitasking unit 12, and wherein secondary signal is the signal that instruction multitasking unit 12 selects USB (universal serial bus) channel U2.
Step 413, multitasking unit 12 according to secondary signal with conducting one universal serial bus channel U2.In practice, universal serial bus channel U2 is in order to carry out general universal serial bus signal or the channel of electric power transfer, therefore, when universal serial bus channel U2 conducting, above-mentioned flash memory device can receive the USB (universal serial bus) information of CPU (central processing unit) 10, be such as the USB (universal serial bus) information of D+/D-, therefore, user can carry out the operations such as the data access of plug and play.
Step 403 ~ 407 and step 409 ~ 413 adjustable sequencing, such as first can carry out step 409(and judge whether identification signal is a preset signals) judgement, carry out step 403(again and judge whether identification signal is a setting signal) judgement, certainly, according to the judged result of step 409 or step 403, corresponding subsequent step will be carried out.In addition, in other embodiments, step 409 ~ 413 are omissible steps, such as step 409 ~ 413 are defined by the specification of original USB (universal serial bus), and debug test circuit 1 carry out step 403 ~ judgement of 407, certainly, step 403(judges whether identification signal is a setting signal) be judged as NO time, can transfer to the circuit of original universal serial bus specification to judge, the present embodiment does not limit the form of the flow process of debug method of testing.
In sum, debug test circuit of the present invention is by USB (universal serial bus) unit, to be external to the computer installation that carries out debug operation, wherein, user is by USB (universal serial bus), with grafting debug test circuit of the present invention, the wherein identification signal that exports according to USB (universal serial bus) of judging unit, with differentiate whether be the first signal, when the result differentiated is the first signal, multitasking unit, by conducting one UART Universal Asynchronous Receiver Transmitter channel, reaches the convenience saved time, reduce costs and promote and detect mainboard thus.In addition, when the result differentiated is secondary signal, multitasking unit, by conducting one universal serial bus channel, reaches the convenience of the data access of plug and play thus.
The foregoing is only embodiments of the invention, it is also not used to limit to claims of the present invention.
Claims (11)
1. a debug test circuit, is arranged at a mainboard, it is characterized in that, comprising:
One CPU (central processing unit);
One multitasking unit, by a debug channel and a USB (universal serial bus) channel, to couple this CPU (central processing unit);
One judging unit, couples this multitasking unit; And
One USB (universal serial bus) unit, is coupled to this multitasking unit and this judging unit;
Wherein, when this USB (universal serial bus) unit receives an identification signal, this identification signal is differentiated by this judging unit, when determining this identification signal and belonging to a setting signal, this judging unit exports one first signal to this multitasking unit, to make this this debug passage of multitasking unit switched conductive.
2. debug test circuit as claimed in claim 1, it is characterized in that, when this USB (universal serial bus) unit receives this identification signal, this identification signal differentiates via this judging unit, when determining this identification signal and belonging to a preset signals, this judging unit exports a secondary signal to this multitasking unit, to make this this universal serial bus channel of multitasking unit switched conductive.
3. debug test circuit as claimed in claim 1 or 2, it is characterized in that, this judging unit comprises an alternative route, this alternative route has one first voltage and one second voltage, this first voltage is greater than this second voltage, when this identification signal through differentiation between this first voltage and this second voltage time, this judging unit determines this identification signal and belongs to this setting signal.
4. debug test circuit as claimed in claim 3, it is characterized in that, this alternative route comprises one first comparer and one second comparer, one first input end of this first comparer couples this first voltage, one second input end of this first comparer is in order to receive this identification signal, one first output terminal of this first comparer couples one first diode, one first input end of this second comparer is in order to receive this identification signal, one second input end of this second comparer couples this second voltage, one second output terminal of this second comparer couples one second diode.
5. debug test circuit as claimed in claim 3, it is characterized in that, when this identification signal is greater than this first voltage through differentiation, or this identification signal is less than this second voltage during through differentiation, this judging unit determines this identification signal and belongs to this preset signals.
6. debug test circuit as claimed in claim 2, is characterized in that, this first signal is the signal of this multitasking Unit selection debug channel of instruction, and secondary signal is the signal of this multitasking Unit selection USB (universal serial bus) of instruction.
7. debug test circuit as claimed in claim 2, wherein this debug channel is a UART Universal Asynchronous Receiver Transmitter channel, when this UART Universal Asynchronous Receiver Transmitter channel of this multitasking cell conduction, this CPU (central processing unit) exports or receives a UART Universal Asynchronous Receiver Transmitter signal, and this UART Universal Asynchronous Receiver Transmitter signal is via this UART Universal Asynchronous Receiver Transmitter channel, to transfer to this multitasking unit, and export via this USB (universal serial bus) unit, or this UART Universal Asynchronous Receiver Transmitter signal inputs via this USB (universal serial bus) unit, to transfer to this multitasking unit, and via this this CPU (central processing unit) of UART Universal Asynchronous Receiver Transmitter transmission.
8. debug test circuit as claimed in claim 7, it is characterized in that, described debug test circuit also comprises a conversion equipment, there is one first Connection Element and one second Connection Element, this first Connection Element is in order to connect this USB (universal serial bus) unit, this second Connection Element is in order to connect a computer installation, and this first Connection Element is USB (universal serial bus), this second Connection Element is RS-232, and this UART Universal Asynchronous Receiver Transmitter signal transfers to this computer installation via this conversion equipment, or this computer installation transmits this UART Universal Asynchronous Receiver Transmitter signal, and transfer to this USB (universal serial bus) unit via this conversion equipment.
9. a debug method of testing, be suitable for detection one mainboard, this mainboard has a CPU (central processing unit), a multitasking unit, a judging unit and a USB (universal serial bus) unit, this multitasking unit is coupled to this CPU (central processing unit), between this judging unit and this USB (universal serial bus) unit, and this multitasking unit is by a debug channel and a USB (universal serial bus) channel, to couple this CPU (central processing unit), it is characterized in that, this debug method of testing comprises:
When this USB (universal serial bus) unit receives an identification signal, judge whether this identification signal is a setting signal, if the determination result is YES, then this judging unit exports one first signal to this multitasking unit; And
This multitasking unit according to this first signal with this debug passage of conducting.
10. debug method of testing as claimed in claim 9, is characterized in that, when judging whether this identification signal is in the step of a setting signal, comprising:
If when judging that this identification signal is not this setting signal, then judge whether this identification signal is a preset signals, if when judging this identification signal as this preset signals, then this judging unit exports a secondary signal to this multitasking unit; And
This multitasking unit according to this secondary signal with this universal serial bus channel of conducting.
11. debug method of testings as claimed in claim 10, it is characterized in that, this judging unit comprises the alternative route that has one first voltage and one second voltage, and this first voltage is greater than this second voltage, when this identification signal is between this first voltage and this second voltage of this alternative route, this judging unit determines this identification signal and belongs to this setting signal; When this identification signal is greater than this first voltage of this alternative route, or when this identification signal is less than this second voltage of this alternative route, this judging unit determines this identification signal and belongs to this preset signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310648781.0A CN104679629A (en) | 2013-12-03 | 2013-12-03 | Debugging test circuit and debugging test method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310648781.0A CN104679629A (en) | 2013-12-03 | 2013-12-03 | Debugging test circuit and debugging test method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104679629A true CN104679629A (en) | 2015-06-03 |
Family
ID=53314715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310648781.0A Pending CN104679629A (en) | 2013-12-03 | 2013-12-03 | Debugging test circuit and debugging test method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104679629A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937414A (en) * | 2010-08-26 | 2011-01-05 | 惠州Tcl移动通信有限公司 | Method and device of sharing minitype USB interface for UART (Universal Asynchronous Receive/Transmitter) and USB (Universal Serial Bus) |
| US20110273309A1 (en) * | 2008-12-05 | 2011-11-10 | Jinjing Zhang | Mobile network terminal device and method for monitoring electrophysiological data and pathological image |
| CN102609384A (en) * | 2011-01-21 | 2012-07-25 | 富泰华工业（深圳）有限公司 | Interface integrated device |
| US20120290246A1 (en) * | 2011-05-13 | 2012-11-15 | Anuj Bhatnagar | Test systems with cables that support multiple communications buses |
| CN102999408A (en) * | 2012-12-06 | 2013-03-27 | 大连奥林匹克电子城腾飞办公设备商行 | Mainboard failure detection system based on singlechip |
| CN103167080A (en) * | 2013-02-04 | 2013-06-19 | 北京大友迅捷科技有限公司 | System and method of testing functions of main board of mobile phone |
| CN203149322U (en) * | 2012-12-07 | 2013-08-21 | 江苏嘉钰新能源技术有限公司 | Extendable measurement channel switching circuit |
-
2013
- 2013-12-03 CN CN201310648781.0A patent/CN104679629A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110273309A1 (en) * | 2008-12-05 | 2011-11-10 | Jinjing Zhang | Mobile network terminal device and method for monitoring electrophysiological data and pathological image |
| CN101937414A (en) * | 2010-08-26 | 2011-01-05 | 惠州Tcl移动通信有限公司 | Method and device of sharing minitype USB interface for UART (Universal Asynchronous Receive/Transmitter) and USB (Universal Serial Bus) |
| CN102609384A (en) * | 2011-01-21 | 2012-07-25 | 富泰华工业（深圳）有限公司 | Interface integrated device |
| US20120290246A1 (en) * | 2011-05-13 | 2012-11-15 | Anuj Bhatnagar | Test systems with cables that support multiple communications buses |
| CN102999408A (en) * | 2012-12-06 | 2013-03-27 | 大连奥林匹克电子城腾飞办公设备商行 | Mainboard failure detection system based on singlechip |
| CN203149322U (en) * | 2012-12-07 | 2013-08-21 | 江苏嘉钰新能源技术有限公司 | Extendable measurement channel switching circuit |
| CN103167080A (en) * | 2013-02-04 | 2013-06-19 | 北京大友迅捷科技有限公司 | System and method of testing functions of main board of mobile phone |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100905795B1 (en) | Mobile device of supporting uart and usb communication using same connector and operating method there-of | |
| US9129065B2 (en) | USB device and control method thereof | |
| JP5283719B2 (en) | Electronic equipment and electronic equipment system | |
| US9684578B2 (en) | Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems | |
| WO2019199611A1 (en) | Overcurrent protection for universal serial bus type-c (usb-c) connector systems | |
| US10824530B2 (en) | System, apparatus and method for non-intrusive platform telemetry reporting using an all-in-one connector | |
| CN107239372B (en) | Electronic device and detection method thereof | |
| CN105071484A (en) | Charging method and apparatus of terminal having data exchange function | |
| CN211427337U (en) | Computer mainboard based on explain majestic treaters | |
| CN101573676B (en) | Power control for serial bus peripheral device | |
| US8990461B2 (en) | On-The-Go (OTG) USB devices configuration method for identifying configuration of other connected devices by reacting to change in resistance value on a resistive line | |
| CN101782879B (en) | Signal conversion device of all-in-one serial bus connector | |
| CN105261278A (en) | Camera module group demonstration tool system, and communication and detection method thereof | |
| CN103365735A (en) | Transmission interface and method for determining transmission signal | |
| CN101126781B (en) | USB apparatus power consumption test device | |
| CN104679629A (en) | Debugging test circuit and debugging test method thereof | |
| US20060095626A1 (en) | Multifunction adapter | |
| CN201876870U (en) | Test system for internal integrated circuit bus and device for internal integrated circuit bus | |
| JP2024508592A (en) | USB interface multiplexing method, circuit, electronic equipment and storage medium | |
| CN103311766A (en) | Mobile equipment switching device and working mode switching method thereof | |
| TWI524177B (en) | Debug test circuit and method thereof | |
| CN112968332A (en) | Compatible device and method for switching TYPE-C interface of tablet personal computer mainboard to UART serial port communication | |
| CN102479129B (en) | Detecting device for states of peripheral components | |
| CN101430637B (en) | Apparatus capable of detecting independent redundancy magnetic disk array initialization | |
| CN105988962B (en) | Overcurrent detecting system and circuit for detecting |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150603 |
|
| WD01 | Invention patent application deemed withdrawn after publication |