CN104579451B - A kind of iridium communication signal receiving device - Google Patents
A kind of iridium communication signal receiving device Download PDFInfo
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- CN104579451B CN104579451B CN201310511739.4A CN201310511739A CN104579451B CN 104579451 B CN104579451 B CN 104579451B CN 201310511739 A CN201310511739 A CN 201310511739A CN 104579451 B CN104579451 B CN 104579451B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Abstract
The present invention provides a kind of iridium communication signal receiving devices, are related to technical field of satellite communication, and described device includes：Preprocessor, FPGA processor and dsp processor；Preprocessor obtains iridium satellite digital signal for carrying out sample quantization to the iridium communication signal of reception by preset rules；FPGA processor obtains iridium satellite channel signal for carrying out Digital Down Convert and digital filtering to iridium satellite digital signal；Dsp processor, after carrying out base band demodulating decoding to iridium satellite channel signal, output demodulation iridium communication signal.The device carries out Digital Down Convert and digital filtering by FPGA processor to iridium communication signal, output demodulates iridium communication signal after dsp processor carries out base band demodulating decoding to the iridium satellite channel signal that FPGA processor exports, and is achieved in the reception to iridium communication signal.
Description
Technical field
The present invention relates to technical field of satellite communication, in particular to a kind of iridium communication signal receiving device.
Background technology
The country there is no the special receiver that confrontation is scouted to iridium communication system at present.However to adapt to my army's Future Information
The demand fought with current anti-terrorism stability maintenance, it would be desirable to some satellite communication signals are intercepted and captured, to be provided for information fighting and anti-terrorism
Information Assurance needs to be realized using reception machine platform in the prior art.
Invention content
The purpose of the present invention is to provide a kind of iridium communication signal receiving devices, to solve the above problem.
A kind of iridium communication signal receiving device is provided in an embodiment of the present invention, including：At preprocessor, FPGA
Manage device and dsp processor；
The preprocessor obtains iridium satellite for carrying out sample quantization to the iridium communication signal of reception by preset rules
Digital signal；
The FPGA processor obtains iridium for carrying out Digital Down Convert and digital filtering to the iridium satellite digital signal
Star channel signal；
The dsp processor, after carrying out base band demodulating decoding to the iridium satellite channel signal, output demodulation iridium satellite is logical
Believe signal.
The iridium communication signal receiving device of the above embodiment of the present invention by FPGA processor to iridium communication signal into
Row Digital Down Convert and digital filtering, dsp processor carry out base band demodulating solution to the iridium satellite channel signal that FPGA processor exports
Output demodulation iridium communication signal, is achieved in the reception to iridium communication signal after code.
Description of the drawings
Fig. 1 shows a kind of structural schematic diagram of iridium communication signal receiving device in the embodiment of the present invention；
Fig. 2 shows another structural schematic diagrams of iridium communication signal receiving device in the embodiment of the present invention；
Fig. 3 and Fig. 4 shows the structural representation of the first receiver in iridium communication signal receiving device of the embodiment of the present invention
Figure；
Fig. 5 shows the structural schematic diagram of second receiver in iridium communication signal receiving device of the embodiment of the present invention；
Fig. 6 and Fig. 7 shows the structural representation of third receiver in iridium communication signal receiving device of the embodiment of the present invention
Figure.
Specific implementation mode
The present invention is described in further detail below through specific implementation examples and in conjunction with the accompanying drawings.
A kind of iridium communication signal receiving device is provided in the embodiment of the present invention, as shown in Figure 1, including mainly：Pretreatment
Device 11, FPGA processor 12 and dsp processor 13；
Preprocessor 11 obtains iridium satellite number for carrying out sample quantization to the iridium communication signal of reception by preset rules
Word signal；
FPGA processor 12 obtains iridium satellite for carrying out Digital Down Convert and digital filtering to the iridium satellite digital signal
Channel signal；
Dsp processor 13, after carrying out base band demodulating decoding to the iridium satellite channel signal, output demodulation iridium communication
Signal.
The iridium communication signal receiving device of the embodiment of the present invention carries out iridium communication signal by FPGA processor 12
Digital Down Convert and digital filtering, dsp processor 13 carry out base band demodulating to the iridium satellite channel signal that FPGA processor 12 exports
Output demodulation iridium communication signal, is achieved in the reception to iridium communication signal after decoding.
Iridium communication signal receiving device in the embodiment of the present invention is in addition to it can receive iridium communication signal, moreover it is possible to send
Number message input by user.
Specifically, further include in iridium communication signal receiving device：User message receiver, digital analog converter and filtering
Device；
The user message receiver, for receiving number message input by user, specifically, as shown in Fig. 2, logical
It crosses network interface 16 or serial ports 15 receives number message input by user.
Dsp processor 13 is additionally operable to that the number message is encoded, interweaved and modulated to generate number biography
Defeated signal；
FPGA processor 12 is additionally operable to number transmission signal carrying out frame mapping, upconversion process, be used
Transmit mixed frequency signal in family；
Digital analog converter（DAC）114, be converted to analogue transmission signal for transmitting mixed frequency signal to the user；Filtering
Device 113, for being sent after being filtered to the analogue transmission signal.
Because iridium communication signal receiving device needs DSP to the iridium satellite channel during receiving iridium communication signal
Signal carries out base band demodulating decoding, needs dsp processor 13 to described during receiving number message input by user
Number message, which is encoded, interweaved and modulated, generates number transmission signal, to mitigate 13 arithmetic speed of dsp processor
And signal-data processing pressure, the processing function of DSP are completed by two dsp processors 13.As shown in Fig. 2, believing in iridium communication
In number reception device, dsp processor 13 includes the first DSP processing chips and the 2nd DSP processing chips；The first DSP processing
Chip and the 2nd DSP processing chips are connect with FPGA processor 12, and the first DSP processing chips are denoted as DSP1a in Fig. 2,
2nd DSP processing chips are denoted as DSP2b.
Base band demodulating decoding is carried out to the iridium satellite channel signal when wherein DSP1a is mainly used for receiving iridium communication signal
Output demodulation iridium communication signal；To realize the function, as shown in Fig. 2, DSP1a includes mainly demodulation module a1, deinterleaves mould
Block a2 and decoding module a3, demodulation module a1, de-interleaving block a2 and decoding module a3 are sequentially connected.Specifically, demodulation module
A1, de-interleaving block a2 and decoding module a3 be respectively used to demodulate the iridium satellite channel signal that FPGA processor 12 exports,
It deinterleaves and decoding is handled, iridium communication signal is demodulated with output.
As shown in Fig. 2, to the number message when DSP2b is mainly used for sending number message input by user
It encoded, interweaved and is modulated and generate number transmission signal；To realize the function, DSP2b include mainly coding module b3,
Interleaving block b2 and modulation module b1, coding module b3, interleaving block b2 and modulation module b1 are sequentially connected.
Turn as shown in Fig. 2, the preprocessor 11 that iridium communication signal receiving device includes includes amplifier 111 and modulus
Parallel operation（ADC）112；Amplifier 111 is connect with ADC112；Amplifier 111 is put for the iridium communication signal to reception
Greatly；ADC112 obtains iridium satellite number for carrying out sample quantization to the amplified iridium communication signal by default sampling rate
Word signal.
As shown in Fig. 2, FPGA processor 12 includes：Down-converted device（DDC）121 and digital filtering module 122；
DDC121 is connect with digital filtering module 122 and ADC112 respectively；Digital filtering module 122 is connect with demodulation module a1.Wherein
The iridium satellite digital signal that DDC121 is used to export analog-digital converter carries out Digital Down Convert, digital filtering module 122, is used for pair
The signal of DDC121 outputs carries out digital filtering, and output obtains iridium satellite channel signal.
In addition, as shown in Fig. 2, further including in FPGA processor 12：Sequentially connected signal forms module 124 and upper change
Frequency processing module（DUC123）, it is respectively used to carry out frame mapping and upconversion process to number transmission signal.
As shown in Fig. 2, further including microcontroller 14 in iridium communication signal receiving device；MCU14 and FPGA processor
12 connections, control FPGA processor 12 by MCU14.
Further include SMA interfaces in iridium communication signal receiving device；The SMA interfaces are for receiving the iridium communication
Signal；SMA interfaces are additionally operable to send the analogue transmission signal of user.
Further, further include serial ports 15 in iridium communication signal receiving device, serial ports 15 is connect with MCU14.
Further include network interface 16 in iridium communication signal receiving device, network interface 16 is connect with dsp processor 13.
In the embodiment of the present invention, demodulation iridium satellite will receive and conversion output may be implemented in serial ports 15 and network interface 16
Signal of communication is exported；In addition, serial ports 15 and network interface 16 may be incorporated for receiving number message input by user.
Iridium communication signal receiving device in the embodiment of the present invention, can demodulating and decoding go out ring channel signal, broadcast
Ring channel signal and traffic channel signal, in order to realize above-mentioned function, the FPGA processor 12 in iridium satellite signal receiving device
It is cooperatively formed by preset rules for decoding the ring channel receiver for exporting ring channel signal with the first DSP processing chips；
FPGA processor 12 is respectively formed with the 2nd DSP processing chips by preset rules cooperation wide for decoding output
It broadcasts the broadcast channel receiver of channel signal, export the request channel receiver of request channel signal and for decoding for decoding
Export the bi-directional traffic channels receiver of bi-directional traffic channels signal.
The ring channel receiver cooperatively forms the first receiver with the broadcast channel receiver；
The ring channel receiver cooperatively forms second receiver with the request channel receiver；
The ring channel receiver cooperatively forms third receiver with the bi-directional traffic channels receiver.
In the embodiment of the present invention, further provide the first receiver, second receiver and third receiver concrete structure.
First receiver can parse decoding ring channel signal and multiplex broadcasting channel signal all the way.
As shown in figure 3, in the first receiver, the structure for parsing ring channel signal includes：In FPGA processor 12
It include the down-converted device for parsing decoding ring channel signal（DDC）121 and digital filtering module 122, at FPGA
Further include in reason device 12：Doppler measurement module 125, signal judgment module 126 and fifo module 127；
Specifically, DDC121 includes sinusoidal frequency conversion output end and cosine frequency conversion output end；
The sine frequency conversion output end and the cosine frequency conversion output end are connect with digital filtering module 122 all the way respectively；
The output end of two-way digital filtering module 122 is connect with Doppler measurement module 125；
Doppler measurement module 125, signal judgment module 126 and fifo module 127 are sequentially connected.
As shown in figure 3, digital filtering module 122 includes：CIC decimation filters, HR decimation filters and FIR shaping filters
Device；The CIC decimation filters, HR decimation filters and FIR shaping filters are sequentially connected.
The output end of fifo module 127 and the input terminal of DSP1a connect, as shown in figure 4, the demodulation module a1 in DSP1a
Including Samples selecting device, frequency offset correction device, skew corrector and demodulator of PM signal PM；
As shown in figure 4, decoding module a3 includes viterbi decoder, CRC check device and information parser；
The Samples selecting device, frequency offset correction device, skew corrector, demodulator of PM signal PM, de-interleaving block a2, Viterbi
Decoder, CRC check device and information parser are sequentially connected.
As shown in Figures 3 and 4, in the first receiver, the structure for parsing broadcast channel signal includes：FPGA processor
DDC121, digital filtering module 122, signal screening judgment module 128 and FIFO moulds in 12 for parsing broadcast channel signal
Block 127；
Specifically, DDC121 includes sinusoidal frequency conversion output end and cosine frequency conversion output end；
The sine frequency conversion output end and the cosine frequency conversion output end are connect with digital filtering module 122 all the way respectively；
The output end of two-way digital filtering module 122 is connect with signal screening judgment module 128.As shown in figure 3, described
Digital filtering module 122 includes：CIC decimation filters, HR decimation filters and FIR shaping filters；
In the embodiment of the present invention, the decoding of ring channel signal is parsed：During ADC112 is sampled by DDC121
Frequency signal changes to baseband signal, is extracted by CIC decimation filters and HB according to sampling rate and the relationship of ring channel speed
The method that filter is combined carries out efficient, low time delay extraction to signal, to reduce sample rate, reduces operand.Molding filter
Can the design of wave device be the key that correctly to restore data, according to system features using the square root liter with transmitting terminal identical parameters
Cosine roll-off filter, the matched filtering of complete pair signals.Since iridium communication system is Low-Orbit Satellite Communication system, signal
Frequency Doppler effect is more serious, so using Doppler's detection module, measures baseband signal frequency deviation in real time, and feed back in due course
Digital Down Convert processor（DDC）121, achieve the purpose that synchronous with iridium communication system frequency.Since iridium communication system is adopted
The screening to signal is realized, to subtract by signal judgment module 126 according to burst signals feature with TDMA multi-access modes
The pressure of light DSP processing, is then transmitted data to by FIFO in DSP1a.
DSP1a handles the multiple velocity rate data that FPGA is sended over, and finds synchronous code by related operation first
Position regard correlation peak as optimal sample point for corresponding one group, completes by carrying out sliding related operation to synchronous code waveform
The selection of sampled point.In the correction for completing frequency deviation skew by synchronous code, correlation demodulation, decoding, solution are carried out according to systematic parameter
Interweave, verify the reduction that message can be completed.By the parsing of the information to ring channel, broadcast channel frequencies are obtained, and lead to
It crosses data/address bus and is sent to FPGA broadcast channel Digital Down Convert processors（DDC）121.
For the parsing of broadcast channel signal in the embodiment of the present invention：To realize that full probability receives, the first receiver receives
Multiplex broadcasting channel, frequency pass through the parsing acquisition to ring channel information.CIC is equally used according to the parameter of broadcast channel
Method that decimation filter, HB decimation filters and FIR low pass formed filters are combined complete extraction to broadcast channel and
Filtering tentatively compensates the Doppler shift of broadcast channel by " the Doppler's detection module " of ring channel.According to broadcast channel
Parameter completes the processing to each path channels using the processing method of similar ring channel, and information is sent to by network interface 16
In the machine of position.
Second receiver can parse decoding ring channel signal and multichannel request channel signal all the way.
As shown in figure 5, for parsing in the structure of ring channel signal all the way and the first receiver in second receiver
Structure for parsing ring channel signal is identical, and details are not described herein again, in addition, the DSP1a in second receiver and DSP2b pairs
The processing structure of data-signal is identical as the structure of Fig. 4, does not provide further herein.For parsing all the way in second receiver
The structure of ring channel signal can realize local reception device and iridium communication system by the parsing of completion ring channel signal
The frequency and time synchronization of system.
For the structure of request channel signal resolution as shown in figure 5, to realize full probability reception, iridium satellite in second receiver
Reception device receives multichannel request channel signal, and receives frequency passes through the parsing acquisition to ring channel signal.According to iridium
The research of star communication system, request channel signal appear in the adjacent channel group of some frequencies（Every group of 3 adjacent channels）, it is
It economizes on resources using every group of adjacent channel as a channel, digital frequency conversion and molding filtration is carried out again after reduction of speed rate.Pass through signal
Screening is stored in random access memory after judging（RAM）It 31 and is sent in DSP2b.In addition pass through " Doppler's detection of ring channel
The Doppler shift of module " tentatively compensation request channel.According to request channel parameter, using the processing method of similar ring channel
The processing to each road request channel signal is completed in DSP2b, and information is sent in host computer.
Third receiver can realize the parsing of bi-directional traffic channels signal, specifically, structure such as Fig. 6 of third receiver
And shown in Fig. 7.FPGA processor 12 mainly completes the Digital Down Convert of system synchronization and two-way channel, filter in third receiver
The processing such as wave extraction；DSP1a and DSP2b is respectively completed Traffic Channel processing, parsing and speech decompression.Third receiver passes through
The slot synchronization and channel Doppler that iridium communication signal receiving device and satellite are completed to the capture of ring channel signal compensate,
To realize to the synchronous and parsing with bi-directional traffic channels signal of ring channel signal, language is completed by dsp processor 13 in real time
Sound decompresses.
As shown in fig. 6, for being parsed in decoded structure and the first receiver to ring channel signal in third receiver
To parse decoded structure to ring channel signal identical, therefore details are not described herein again, by believing ring in third receiver
The synchronous of local receiver and iridium communication system frequency and time is completed in the parsing decoding of road signal.
Structure in third receiver for being parsed to traffic channel signal is as shown in FIG. 6 and 7, is instructed according to host computer
NCO frequency words are set, assigned traffic channel signal is become into baseband signal, it is real by " the Doppler's detection module " of ring channel
When compensating traffic channel signal Doppler shift.According to Traffic Channel parameter, corresponding filtering extraction processing is carried out, at DSP
The processing and speech decoding completed in device 13 to each path channels are managed, and the data that parsing decodes out are reported.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any made by repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of iridium communication signal receiving device, which is characterized in that including：Preprocessor, FPGA processor and DSP processing
Device；
The preprocessor obtains iridium satellite number for carrying out sample quantization to the iridium communication signal of reception by preset rules
Signal；
The FPGA processor obtains iridium satellite letter for carrying out Digital Down Convert and digital filtering to the iridium satellite digital signal
Road signal；
The dsp processor, after carrying out base band demodulating decoding to the iridium satellite channel signal, output demodulation iridium communication letter
Number；
The dsp processor includes the first DSP processing chips and the 2nd DSP processing chips；
The first DSP processing chips and the 2nd DSP processing chips are connect with the FPGA processor；Described first
Base band demodulating decoding output demodulation iridium is carried out to the iridium satellite channel signal when DSP processing chips are for receiving iridium communication signal
Star signal of communication；To the number when the 2nd DSP processing chips are used to send number message input by user
Message, which is encoded, interweaved and modulated, generates number transmission signal；
The FPGA processor is cooperatively formed by preset rules for decoding output ring channel with the first DSP processing chips
The ring channel receiver of signal；
The FPGA processor is respectively formed by preset rules cooperation for decoding output broadcast with the 2nd DSP processing chips
The broadcast channel receiver of channel signal, for decode output request channel signal request channel receiver and for decoding it is defeated
Go out the bi-directional traffic channels receiver of bi-directional traffic channels signal；
The ring channel receiver cooperatively forms the first receiver with the broadcast channel receiver；
The ring channel receiver cooperatively forms second receiver with the request channel receiver；
The ring channel receiver cooperatively forms third receiver with the bi-directional traffic channels receiver.
2. the apparatus according to claim 1, which is characterized in that further include：User message receiver, digital analog converter and filter
Wave device；
The user message receiver, for receiving number message input by user；
The dsp processor is additionally operable to that the number message is encoded, interweaved and modulated to generate number transmission
Signal；
The FPGA processor is additionally operable to number transmission signal carrying out frame mapping, upconversion process, obtains user
Transmit mixed frequency signal；
The digital analog converter is converted to analogue transmission signal for transmitting mixed frequency signal to the user；
The filter, for being sent after being filtered to the analogue transmission signal.
3. the apparatus of claim 2, which is characterized in that the preprocessor includes amplifier and analog-digital converter；
The amplifier is connect with the analog-digital converter；
The amplifier is amplified for the iridium communication signal to reception；
The analog-digital converter, for carrying out sample quantization to the amplified iridium communication signal by default sampling rate,
Obtain iridium satellite digital signal.
4. device according to claim 3, which is characterized in that the dsp processor includes：Demodulation module deinterleaves mould
Block and decoding module；
The demodulation module, the de-interleaving block and the decoding module are sequentially connected.
5. device according to claim 4, which is characterized in that the FPGA processor includes：Down-converted device and number
Word filter module；
The down-converted device is connect with the digital filtering module and the analog-digital converter respectively；The digital filtering mould
Block is connect with the demodulation module.
6. the apparatus according to claim 1, which is characterized in that further include：Microcontroller；The MCU and FPGA
Processor connects.
7. device according to claim 6, which is characterized in that further include：SMA interfaces；The SMA interfaces are for receiving institute
State iridium communication signal；
And/or
Further include serial ports, the serial ports is connect with the MCU；
And/or
Further include network interface, the network interface is connect with the dsp processor.
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