CN103795456B - A kind of maritime satellite communications receiving system and method - Google Patents
A kind of maritime satellite communications receiving system and method Download PDFInfo
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- CN103795456B CN103795456B CN201410046685.3A CN201410046685A CN103795456B CN 103795456 B CN103795456 B CN 103795456B CN 201410046685 A CN201410046685 A CN 201410046685A CN 103795456 B CN103795456 B CN 103795456B
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Abstract
The invention discloses a kind of maritime satellite communications receiving system and method, wherein, method comprises the following steps：First the DVB reception of the satellite communication signals of zone beam channel and dissection process to global beam channel all the way and all the way；Reception and dissection process of second DVB to the satellite communication signals of narrow spot beam channel；3rd DVB is to the reversely reception of the satellite communication signals of application and Traffic Channel and dissection process.Maritime satellite communications receiving system and method that the present invention is provided, with widely used, integrated level height, compact, structure is reliable, steady operation and other merits, can complete the reception to two kinds of channels of global beam channel and zone beam channel and dissection process.
Description
Technical field
The present invention relates to technical field of satellite communication, more particularly to a kind of maritime satellite communications receiving system and side
Method.
Background technology
To adapt to the demand that my army's Future Information is fought with current anti-terrorism stability maintenance, it would be desirable to intercept and capture some satellite communications letter
Number, to be that information fighting and anti-terrorism provide Information Assurance；At present, the world there is no connects to maritime affairs four generations communication service information
Receipts, the special receiver of demodulation process, the maritime affairs four generations receiver that some factories are developed can only be communicated by receiving the generation of maritime affairs four
Signal spectrum, the parameter in terms of a few channels to obtain the communication of the generation of maritime affairs four, and key parameter, letter to the communication of the generation of maritime affairs four
Breath and business are helpless.
When implementing, it is difficult to there is a kind of machine platform that receives to complete to global beam channel and zone beam channel
The reception of two kinds of channels and dissection process.
The content of the invention
It is an object of the invention to provide a kind of maritime satellite communications receiving system and method, to solve above-mentioned technology
Problem.
In order to achieve the above object, the technical proposal of the invention is realized in this way：
A kind of maritime satellite communications receiving system, including host computer and satellite reception platform, the host computer and institute
The communication connection of satellite reception platform network interface is stated, wherein：
The satellite reception platform includes the first DVB, the second DVB, the 3rd DVB, its
In：
First DVB, for global beam channel all the way and the satellite communication of zone beam channel all the way
The reception of signal and dissection process；
Second DVB, reception and dissection process for the satellite communication signals to narrow spot beam channel；
3rd DVB, for the reception and parsing to the reversely satellite communication signals of application and Traffic Channel
Processing.
It is preferred that first DVB includes the first fpga chip and two the first dsp chips, wherein：
First fpga chip, for the numeral to the two communication channels of global beam channel and zone beam channel
Down coversion, filtering extraction, frequency correction, synchronization character matching and skew compensation deals；
First fpga chip includes down-converted module, filtering process module, frequency deviation measurement module, synchronization character
With module and skew compensating module, wherein：
The down-converted module, for the satellite communication signals in global beam channel and zone beam channel
Intermediate-freuqncy signal carries out mixing operation and moved to baseband signal, and the satellite communication signals after Frequency mixing processing are sent to the filtering
Manage module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, is used for
Satellite communication signals are carried out with filtering extraction processing operation, the satellite communication signals after filtering process are sent to frequency deviation measurement mould
Block；
The frequency deviation measurement module, for carrying out preliminary surveying to satellite communication signals frequency deviation, and feeds back to the lower change
Frequency processing module carries out frequency deviation convergence；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to skew
Compensating module；
The skew compensating module, for carrying out skew compensating operation to satellite communication signals, and after skew is handled
Satellite communication signals are sent to first dsp chip；
Described two first dsp chips are additionally operable in the global beam channel and zone beam channel that are sended over to FPGA
Satellite communication signals be demodulated, deinterleave, Turbo decodings, descrambling, CRC check and information analysis processing, so as to complete complete
The information reverting operation of the satellite communication signals of ball beam-channel and zone beam channel.
It is preferred that second DVB includes the second fpga chip and two the second dsp chips, wherein：
Second fpga chip, for the Digital Down Convert of narrow channel, filtering extraction, frequency correction, synchronization character
Matching and skew compensation deals；Described two second dsp chips, for completion jointly to be to the decoding of narrow channel, descrambling and leads to
Letter operation；
Second fpga chip includes down-converted module, filtering process module, frequency deviation measurement module, synchronization character
With module and skew compensating module, wherein：
The down-converted module, mixing behaviour is carried out for the intermediate-freuqncy signal to the satellite communication signals in narrow channel
Move to baseband signal, the satellite communication signals after Frequency mixing processing are sent to the filtering process module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, is used for
Satellite communication signals are carried out with filtering extraction processing operation, the satellite communication signals after filtering process are sent to frequency deviation measurement mould
Block；
The frequency deviation measurement module, for carrying out preliminary surveying to satellite communication signals frequency deviation, and feeds back to the lower change
Frequency processing module carries out frequency deviation convergence；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to skew
Compensating module；
The skew compensating module, for carrying out skew compensating operation to satellite communication signals, and after skew is handled
Satellite communication signals are sent to second dsp chip；
Described two second dsp chips are additionally operable to the satellite communication signals in the common narrow channel sended over to FPGA
It is demodulated, deinterleaves, Turbo is decoded, descramble, CRC check and information analysis are handled, so that the satellite for completing narrow channel leads to
Believe the information reverting operation of signal.
It is preferred that the 3rd DVB includes the 3rd fpga chip and two the 3rd dsp chips, wherein：
3rd fpga chip, for completing system reversely application and change under the numeral of reverse traffic channel all the way all the way
Frequently, filtering extraction, signalling channel judge, synchronization character is matched and FIFO processing；
3rd fpga chip includes down-converted module, filtering process module, signalling channel judge module, synchronization
Word matching module, FIFO processing modules, wherein：
The down-converted module, for reversely application and all the way the satellite communication letter in reverse traffic channel all the way
Number intermediate-freuqncy signal carry out mixing operation move to baseband signal, the satellite communication signals after Frequency mixing processing are sent to the filter
Ripple processing module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, is used for
Satellite communication signals are carried out with filtering extraction processing operation, the satellite communication signals after filtering process are sent to frequency deviation measurement mould
Block；
The signalling channel judge module, for carrying out parallel processing respectively to two paths of signals, determines signal source in real time,
And signal is sent in synchronization character matching module；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to FIFO
Processing module；
The FIFO processing modules, same dequeue is entered together for being created according to the satellite communication signals after reception；According to same
Enter same dequeue and reduce the signal of communication of each data frame, and be sent to the 3rd dsp chip；
Described two 3rd dsp chips, are additionally operable to the reversely application and all the way reverse traffic all the way sended over to FPGA
Satellite communication signals in channel are demodulated, deinterleaved, Turbo is decoded, descramble, CRC check and information analysis are handled, so that
Complete reversely application and all the way the information reverting operation of the satellite communication signals of reverse traffic channel all the way.
It is preferred that the host computer is PC；
The host computer passes through RJ45 network interface connections with multiple DVBs respectively.
Correspondingly, present invention also offers a kind of maritime satellite communications signal acceptance method, comprise the following steps：
First DVB satellite communication signals of zone beam channel to global beam channel all the way and all the way connect
Receive and dissection process；
Reception and dissection process of second DVB to the satellite communication signals of narrow spot beam channel；
3rd DVB is to the reversely reception of the satellite communication signals of application and Traffic Channel and dissection process.
It is preferred that the satellite of first DVB zone beam channel to global beam channel all the way and all the way leads to
Believe reception and the dissection process of signal, specifically include following steps：
The down-converted module in first fpga chip is in global beam channel and zone beam channel
Satellite communication signals intermediate-freuqncy signal carry out mixing operation move to baseband signal, by the satellite communication signals after Frequency mixing processing
Send to the filtering process module；
The filtering process module in first fpga chip carries out filtering extraction processing to satellite communication signals and grasped
Make, the satellite communication signals after filtering process are sent to frequency deviation measurement module；
The frequency deviation measurement module in first fpga chip carries out preliminary surveying to satellite communication signals frequency deviation, and
Feed back to the down-converted module and carry out frequency deviation convergence；
The synchronization character matching module in first fpga chip synchronizes word matching behaviour to satellite communication signals
Make, and be sent to skew compensating module；
The skew compensating module in first fpga chip carries out skew compensating operation to satellite communication signals, and
Satellite communication signals after skew is handled are sent to first dsp chip；
Defending in global beam channel and zone beam channel that described two first dsp chips are also sended over to FPGA
Star signal of communication is demodulated, deinterleaved, Turbo is decoded, descramble, CRC check and information analysis are handled, so as to complete global ripple
The information reverting operation of the satellite communication signals of Shu Xindao and zone beam channel.
It is preferred that second DVB to the reception and parsing of the satellite communication signals of narrow spot beam channel at
Reason, specifically includes following steps：
The down-converted module in second fpga chip is in the satellite communication signals in narrow channel
Frequency signal carries out mixing operation and moved to baseband signal, and the satellite communication signals after Frequency mixing processing are sent to the filtering process
Module；
Filtering process module described in second fpga chip carries out filtering extraction processing to satellite communication signals and operated,
Satellite communication signals after filtering process are sent to frequency deviation measurement module；
Frequency deviation measurement module described in second fpga chip carries out preliminary surveying to satellite communication signals frequency deviation, and instead
The down-converted module of feeding carries out frequency deviation convergence；
Synchronization character matching module synchronizes word matching operation to satellite communication signals described in second fpga chip,
And it is sent to skew compensating module；
Skew compensating module described in second fpga chip carries out skew compensating operation to satellite communication signals, and will
Satellite communication signals after skew processing are sent to second dsp chip；
Satellite communication signals in the also common narrow channel sended over to FPGA of described two second dsp chips are carried out
Demodulation, deinterleaving, Turbo decodings, descrambling, CRC check and information analysis processing, so as to complete the satellite communication letter of narrow channel
Number information reverting operation.
It is preferred that reception of the 3rd DVB to the reversely satellite communication signals of application and Traffic Channel is conciliate
Analysis is handled, and specifically includes following steps：
Down-converted module described in 3rd fpga chip is to reversely application and all the way reverse traffic channel all the way
In satellite communication signals intermediate-freuqncy signal carry out mixing operation move to baseband signal, by after Frequency mixing processing satellite communication believe
Number send to the filtering process module；
Filtering process module described in 3rd fpga chip carries out filtering extraction processing to satellite communication signals and operated,
Satellite communication signals after filtering process are sent to frequency deviation measurement module；
Signalling channel judge module carries out parallel processing to two paths of signals respectively described in 3rd fpga chip, in real time
Determine that signal is originated, and signal is sent in synchronization character matching module；
Synchronization character matching module synchronizes word matching operation to satellite communication signals described in 3rd fpga chip,
And it is sent to FIFO processing modules；
FIFO processing modules described in 3rd fpga chip create same with entering according to the satellite communication signals after reception
Dequeue；The signal of communication of each data frame is reduced according to same dequeue is entered together, and is sent to the 3rd dsp chip；
The reversely application and all the way in reverse traffic channel all the way that described two 3rd dsp chips are also sended over to FPGA
Satellite communication signals be demodulated, deinterleave, Turbo decoding, descrambling, CRC check and information analysis processing, so as to complete one
Road reversely application and the information reverting operation of the satellite communication signals of reverse traffic channel all the way.
Compared with prior art, this have the advantage that：
A kind of maritime satellite communications receiving system and method that the present invention is provided, the wherein reception system, main bag
Include two major parts of host computer and satellite reception platform；
Satellite reception platform includes the first DVB, the second DVB and the 3rd DVB, three kinds
DVB receives the satellite communication signals of different channels and carries out pretreatment operation（Including power amplification, analog-to-digital conversion and
The processing such as filtering）；First, the first DVB, for global beam channel all the way and zone beam channel is defended all the way
The reception of star signal of communication and dissection process；Second DVB, for the satellite communication signals to narrow spot beam channel
Receive and dissection process；3rd DVB, for reversely application and Traffic Channel satellite communication signals reception and
Dissection process.Three kinds of receivers are main to be believed by global beam Channel Processing software, zone beam Channel Processing software, narrow spot beam
Road processing software, request channel processing software and communication software composition, all kinds of Channel Processing softwares are respectively embedded in fpga chip
With respective function is completed in dsp chip（Each DVB is equipped with above-mentioned similar hardware）.When implementing, first
DVB is mainly responsible for the parsing of 1 road global beam channel and 1 road zone beam channel, and wherein FPGA mainly completes two
The processing such as Digital Down Convert, filtering extraction, frequency correction, the synchronization character matching of channel bank；Two DSP are respectively completed to the whole world
Channel decoding, descrambling and communication with zone beam channel.Second DVB is mainly responsible for the parsing to narrow channel, its
Middle FPGA mainly completes the processing such as the Digital Down Convert, filtering extraction, frequency correction, synchronization character matching of 1 narrow channel；Two
DSP completes decoding, descrambling and the communication to narrow channel jointly.3rd DVB is mainly responsible for system reverse application and industry
The parsing of business channel, wherein FPGA mainly completes system reverse request channel and change under the numeral of reverse traffic channel all the way all the way
Frequently, filtering extraction etc. is handled；Two DSP are respectively completed the functions such as channel demodulation, decoding.
The maritime satellite communications receiving system that present example is provided, by the maritime affairs four generations telecommunication satellite whole world
The demodulation of wave beam and zone beam signal, processing, parse maritime affairs four generations communication satellite system wave beam distribution situation and business is logical
The key parameters such as letter situation, are applicable to the monitoring to the maritime affairs four generations communication information, obtain maritime affairs four generations communication intelligence, can be extensive
Applied to anti-terrorism stability maintenance and military struggle field.
Brief description of the drawings
Fig. 1 is the structural representation of maritime satellite communications receiving system provided in an embodiment of the present invention；
Fig. 2 is the structure of the first DVB in maritime satellite communications receiving system provided in an embodiment of the present invention
Schematic diagram；
Fig. 3 be maritime satellite communications receiving system provided in an embodiment of the present invention in the first DVB it is specific
Hardware architecture diagram；
Fig. 4 is the structure of the second DVB in maritime satellite communications receiving system provided in an embodiment of the present invention
Schematic diagram；
Fig. 5 be maritime satellite communications receiving system provided in an embodiment of the present invention in the second DVB it is specific
Hardware architecture diagram；
Fig. 6 is the structure of the 3rd DVB in maritime satellite communications receiving system provided in an embodiment of the present invention
Schematic diagram；
Fig. 7 be maritime satellite communications receiving system provided in an embodiment of the present invention in the 3rd DVB it is specific
Hardware architecture diagram；
Fig. 8 is the schematic flow sheet of maritime satellite communications signal acceptance method provided in an embodiment of the present invention.
Embodiment
The present invention is described in further detail below by specific embodiment and with reference to accompanying drawing.
Referring to Fig. 1, present example provides a kind of maritime satellite communications receiving system 1, including the He of host computer 10
Satellite reception platform 20, the host computer 10 is communicated to connect with the satellite reception platform 20 with network interface, wherein：
The satellite reception platform 20 connects including the first DVB 21, the second DVB 22 and the 3rd satellite
Receipts machine 23, wherein：
First DVB 21, the satellite for global beam channel all the way and all the way zone beam channel leads to
Believe reception and the dissection process of signal；
Second DVB 22, at the reception and parsing of the satellite communication signals to narrow spot beam channel
Reason；
3rd DVB 23, conciliates for the reception to the reversely satellite communication signals of application and Traffic Channel
Analysis is handled.
It should be noted that：In embodiments of the present invention, maritime satellite communications receiving system includes host computer and defended
Two major parts of star receiving platform, DVB reception processing satellite-signal, host computer is responsible for each operation of receiver shape
The control of state.
Three kinds of DVBs receive satellite communication signals and carry out pretreatment operation（Including power amplification, analog-to-digital conversion
With filtering etc. processing）；First, the first DVB, for global beam channel all the way and all the way zone beam channel
The reception of satellite communication signals and dissection process；Second DVB, for the satellite communication signals to narrow spot beam channel
Reception and dissection process；3rd DVB, for the reception to the reversely satellite communication signals of application and Traffic Channel
And dissection process.Three kinds of receivers are main by global beam Channel Processing software, zone beam Channel Processing software, narrow spot beam
Channel Processing software, request channel processing software and communication software composition, all kinds of Channel Processing softwares are respectively embedded in FPGA cores
Respective function is completed in piece and dsp chip（Each DVB is equipped with above-mentioned similar hardware）.When implementing, the
One DVB is mainly responsible for the parsing of 1 road global beam channel and 1 road zone beam channel, and wherein FPGA mainly completes two
The processing such as Digital Down Convert, filtering extraction, frequency correction, the synchronization character matching of individual channel bank；Two DSP are respectively completed to complete
Channel decoding, descrambling and the communication of ball and zone beam channel.Second DVB is mainly responsible for the parsing to narrow channel,
Wherein FPGA mainly completes the processing such as the Digital Down Convert, filtering extraction, frequency correction, synchronization character matching of 1 narrow channel；Two
Individual DSP completes decoding, descrambling and the communication to narrow channel jointly.3rd DVB mainly be responsible for system reverse application and
The parsing of Traffic Channel, wherein FPGA mainly complete system reversely application and change under the numeral of reverse traffic channel all the way all the way
Frequently, filtering extraction etc. is handled；Two DSP are respectively completed the functions such as channel demodulation, decoding.
Receiver platform hardware is mainly using current FPGA, DSP relatively more stable than higher-end, performance in the embodiment of the present invention
Deng large scale integrated chip (LSI chip)（Said chip is integrated in control mainboard, and above-mentioned control mainboard also includes other components, for example, connect
Mouth device, peripheral circuit and serial ports）, with being sampled to analog signal figure, the work(such as Digital Signal Processing, modulates baseband signals
Can, can be by downloading parsing of the demodulating and decoding software realization to marine satellite signal.
Referring to Fig. 2 and Fig. 3, it is preferred that first DVB 21 includes the first fpga chip 210 and two first
Dsp chip 211, wherein：
First fpga chip, for the numeral to the two communication channels of global beam channel and zone beam channel
Down coversion, filtering extraction, frequency correction, synchronization character matching and skew compensation deals；
First fpga chip includes down-converted module, filtering process module, frequency deviation measurement module, synchronization character
With module and skew compensating module, wherein：
The down-converted module, for the satellite communication signals in global beam channel and zone beam channel
Intermediate-freuqncy signal carries out mixing operation and moved to baseband signal, and the satellite communication signals after Frequency mixing processing are sent to the filtering
Manage module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, is used for
Satellite communication signals are carried out with filtering extraction processing operation, the satellite communication signals after filtering process are sent to frequency deviation measurement mould
Block；
The frequency deviation measurement module, for carrying out preliminary surveying to satellite communication signals frequency deviation, and feeds back to the lower change
Frequency processing module carries out frequency deviation convergence；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to skew
Compensating module；
The skew compensating module, for carrying out skew compensating operation to satellite communication signals, and after skew is handled
Satellite communication signals are sent to first dsp chip；
Described two first dsp chips are additionally operable in the global beam channel and zone beam channel that are sended over to FPGA
Satellite communication signals be demodulated, deinterleave, Turbo decodings, descrambling, CRC check and information analysis processing, so as to complete complete
The information reverting operation of the satellite communication signals of ball beam-channel and zone beam channel.
It should be noted that in embodiments of the present invention, wherein FPGA mainly completes to become under the numeral of two channel banks
Frequently, the processing such as filtering extraction, frequency correction, synchronization character matching；Two DSP are respectively completed the letter to the whole world and zone beam channel
Road decoding, descrambling and communication.
Specifically,（1）The parsing of global beam channel：The ADC intermediate-freuqncy signals sampled are changed to base band by logical Digital Down Convert
Signal, is mutually tied according to sampling rate and the relation of ring channel speed by " CIC decimation filters " and " HB decimation filters "
The method of conjunction carries out the extraction of efficient, low time delay to signal, to reduce sample rate, reduces operand.The design of formed filter
It is that can correctly recover the key of data, uses the Square-root Raised Cosine with transmitting terminal identical parameters to filter according to system features
Ripple device, the matched filtering of good complete pair signals.It is that correction signal frequency deviation uses " frequency deviation detection module " measurement base band in real time
Signal frequency deviation, and leading portion Digital Down Converter Module is fed back in good time, reach the purpose synchronous with system frequency.Information in the system
Stream constitutes a frame with some code elements, and row information is entered in units of frame and goes out transmission.To realize that the synchronization to signal is received, by same
Step code waveform enters line slip related operation, using correlation peak it is corresponding one group as optimal sample point, and complete the position to information
It is synchronous.Then using pilot tone as reference, sequence initial phase is determined.
（2）The parsing of zone beam channel：Zone beam and global beam channel parameter difference, specific believe with reference to it
Road parameter designing modules, the parsing to regional signal is completed with similar step.
Referring to Fig. 4 and Fig. 5, it is preferred that second DVB 22 includes the second fpga chip 220 and two second
Dsp chip 221, wherein：
Second fpga chip, for the Digital Down Convert of narrow channel, filtering extraction, frequency correction, synchronization character
Matching and skew compensation deals；Described two second dsp chips, for completion jointly to be to the decoding of narrow channel, descrambling and leads to
Letter operation；
Second fpga chip includes down-converted module, filtering process module, frequency deviation measurement module, synchronization character
With module and skew compensating module, wherein：
The down-converted module, mixing behaviour is carried out for the intermediate-freuqncy signal to the satellite communication signals in narrow channel
Move to baseband signal, the satellite communication signals after Frequency mixing processing are sent to the filtering process module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, is used for
Satellite communication signals are carried out with filtering extraction processing operation, the satellite communication signals after filtering process are sent to frequency deviation measurement mould
Block；
The frequency deviation measurement module, for carrying out preliminary surveying to satellite communication signals frequency deviation, and feeds back to the lower change
Frequency processing module carries out frequency deviation convergence；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to skew
Compensating module；
The skew compensating module, for carrying out skew compensating operation to satellite communication signals, and after skew is handled
Satellite communication signals are sent to second dsp chip；
Described two second dsp chips are additionally operable to the satellite communication signals in the common narrow channel sended over to FPGA
It is demodulated, deinterleaves, Turbo is decoded, descramble, CRC check and information analysis are handled, so that the satellite for completing narrow channel leads to
Believe the information reverting operation of signal.
It should be noted that the parsing of narrow spot beam channel：Compared with other channels, narrow spot beam channel speed is higher,
The processing to a narrow channel can be completed by needing two DSP parallel processings.
Referring to Fig. 6 and Fig. 7, it is preferred that the 3rd DVB 23 includes the 3rd fpga chip 230 and two the 3rd
Dsp chip 231, wherein：
3rd fpga chip 230, for completing system reversely application and all the way numeral of reverse traffic channel all the way
Down coversion, filtering extraction, signalling channel judge, synchronization character is matched and FIFO processing；
The down-converted module, for reversely application and all the way the satellite communication letter in reverse traffic channel all the way
Number intermediate-freuqncy signal carry out mixing operation move to baseband signal, the satellite communication signals after Frequency mixing processing are sent to the filter
Ripple processing module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, is used for
Satellite communication signals are carried out with filtering extraction processing operation, the satellite communication signals after filtering process are sent to frequency deviation measurement mould
Block；
The signalling channel judge module, for carrying out parallel processing respectively to two paths of signals, determines signal source in real time,
And signal is sent in synchronization character matching module；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to FIFO
Processing module；
The FIFO processing modules, same dequeue is entered together for being created according to the satellite communication signals after reception；According to same
Enter same dequeue and reduce the signal of communication of each data frame, and be sent to the 3rd dsp chip；
Described two 3rd dsp chips, are additionally operable to the reversely application and all the way reverse traffic all the way sended over to FPGA
Satellite communication signals in channel are demodulated, deinterleaved, Turbo is decoded, descramble, CRC check and information analysis are handled, so that
Complete reversely application and all the way the information reverting operation of the satellite communication signals of reverse traffic channel all the way.
It should be noted that（1）The parsing of request channel：Two phases are likely to appear according to system features request channel
In adjacent channel, economized on resources to improve efficiency of algorithm.Parallel processing is carried out respectively to two paths of signals first, then by " logical
Cross signalling channel judgement " module determines that signal is originated in real time, and signal is sent in synchronization character matching module further located
Reason.Data that DSP1 is sended over to FPGA carry out QPSK demodulation, Turbo decodings, descrambling, verification can completion message also
It is former.
（2）The parsing of Traffic Channel：Traffic Channel might have two kinds of channel types, so determining it according to communication signaling
Channel type, selects one to be handled in a program.
Wherein, the data that DSP2 is sended over to FPGA carry out QPSK or 16QAM demodulation, Turbo decodings, descrambling, verification
Can completion message reduction.
It should be noted that FIFO processing modules, team is gone out together for creating to enter together according to the satellite communication signals after reception
Row list；Frame synchronization counter, for when initially receiving to satellite communication signals, setting frame synchronization counter initial value, is carried out
Clocked operation, calculates the queue frame number and timeslot number obtained with the signal of communication of each data frame in same dequeue list is entered；
The dsp chip carries out Samples selecting to satellite communication signals, corrects frequency deviation, corrects skew, and demodulation, solution is handed over
Knit, decode, CRC check and information analysis processing；While being parsed to present satellites signal of communication, obtain and inquire about same
Enter the queue frame number and timeslot number of the signal of communication of current data frame in same dequeue list, calculate the communication of current data frame
The eccentric traveling distance of the clock signal of dsp chip in the corresponding DVB of signal, and the eccentric traveling distance is fed back to frame
Coincidence counter；Frame synchronization counter, is additionally operable to according to the eccentric traveling distance, to dsp chip in adjustment DVB
Clock signal, after migration, the clock signal for completing dsp chip in DVB is synchronous with satellite communication signals
Operation.
It is preferred that the host computer is PC；
The host computer passes through RJ45 network interface connections with multiple DVBs respectively.
Specifically, above-mentioned host computer is to include the control system of computer or industrial computer, can receive satellite communication number
According to.Above-mentioned fpga chip can be with other external communication interfaces, including network interface is (for example:RJ45), serial communication interface etc.
Interface.The connection of above-mentioned RS232 or RS485 bus modes is one of them preferred technical scheme, it is also possible to make lan network or
It is other communication modes such as Ethernet connection, present example is no longer repeated this one by one.
In addition, fpga chip is as control core element, above-mentioned various modules are integrated with, the different function for realizing.
Fpga chip is in the high-performance microcontroller come based on MCU development, it is preferred that it uses following configuration：CPU is up to 500,
000 gate logic element resources；Clock point active crystal oscillators of 50MHz and the active crystal oscillators of 12MHz；64M SDRAM16 bit data interfaces；Hold
The SRAM for measuring the 256Kx16Bit for 4Mbit tells memory；The serial flash memories of 8Mbits of SPI, can be FPGA and match somebody with somebody
Put memory；Independent JPAG interfaces；Therefore fpga chip has high performance computation disposal ability, for example：Can quickly it handle
Satellite communication signals simultaneously carry out corresponding computing.
It will be understood by those skilled in the art that developer can utilize hardware description language（For example：Verilog
HDL hardware program languages）Fpga chip functional development is carried out, or passes through related software（For example：Quartues II、verilog）
To realize configuration pre-arranged code parameter information（For example：For the storage and setting of every Channel coding parameters）Setting and pass through
Configuration processor handles operation to realize.Developer burns program after fpga chip, and interlock circuit is integrated into control master
Integral control circuit is realized on plate.
Various receiver in the embodiment of the present invention takes closed loop configuration, and the frequency with signal is completed by the way of negative-feedback
Rate is synchronous.Receiver carries out AD samplings, mixing orthogonal with local oscillator NCO progress, by CIC and HB to intermediate-freuqncy signal first
LPF is carried out after decimation filter, I, Q two-way baseband signal of 16 times of character rates is formed.According to the characteristics of frame structure,
Frame Synchronization Test and capturing frequency deviation are completed using unique word joint DFT parallel processings.I, Q are divided into two-way, the first via passes through certainly
Related algorithm parallel capture detects synchronization character, completes the frame synchronization of receiver and signal；Second tunnel passes through to 16 times of symbol speed
The signal of rate carries out the probable ranges that 64 point DFT estimate frequency deviation, completes thick frequency offset correction for the first time.Sign synchronization completes laggard
Matched filtering of row, sends into fine calibrating frequency module and completes inherent spurious frequency deviation correction, and feed back to NCO amendment frequency deviations.Then pass through
Locally known UW carries out computing cross-correlation with signal, is sent the data to after obtaining phase offset, phase calibration in DSP, carries out
Further demodulation, decoding, descrambling and CRC check.
It specifically can reach following technique effect；
1. wave filter is designed：The ADC intermediate-freuqncy signals sampled are changed to baseband signal by logical Digital Down Convert, according to sampling rate
Signal is carried out with the method that the relation of channel speed is combined by " CIC decimation filters " and " HB decimation filters " high
Effect, the extraction of low time delay, to reduce sample rate, reduce operand.Can the design of formed filter correctly recover data
Key, according to system features using the square root raised cosine filter with transmitting terminal identical parameters, is completed to letter well
Number preliminary filtering.
2. frame synchronization designs：Information flow constitutes a frame with some code elements in the system, and row information is entered in units of frame and goes out biography
It is defeated.The need for frame synchronization, communication system inserts synchronization character in frame head（UW）, it is length sequence known to 40 bipolarity
Row, to realize that the synchronization to signal is received, using this feature by entering line slip related operation to synchronous code waveform, by correlation
Peak value it is corresponding one group as optimal sample point, and complete the frame synchronization to information.
3. Frequency Synchronization is designed：Frequency Synchronization realizes that local frequency deviation is received by the way of multistage calibrating frequency processing and closed loop feedback
Hold back.First using thick calibrating frequency module complete to signal frequency deviation according to a preliminary estimate after, by matched filtering module according to channel parameter
Matched filtering is carried out to signal, to reach the purpose to the undistorted recovery of signal.Then on the basis of thick calibrating frequency, make
Identical method is used, using thick calibrating frequency precision as scope, the offset estimation of higher precision is carried out, inherent spurious frequency deviation is removed, and will be final
Frequency deviation result is fed back in NCO, and the convergence of receiver frequency deviation is done step-by-step.The method for coordinating matched filtering is detected using frequency deviation step by step
Compared with single-stage frequency offset processing, have the advantages that can efficiently, it is accurate, save resource, it is possible to while realizing to signal
With filtering, the purpose that final matching is received is reached.
4. skew Compensation Design：It is complete by the estimation to known synchronization character sequence phase on the basis of frame synchronization is completed
The calculating of pair signals skew, phase offset compensation purpose is reached by being multiplied by twiddle factor to signal.
5.QPSK is demodulated：According to system modulation mapping relations, judgement demodulation is completed.
6.Turbo is decoded：The intertexture defined using system and punctured table, are decoded using the completion of MaxLog-map algorithms,
Error correcting capability is more excellent compared with SOVA algorithms.
7. descrambling and verification：Finally, the descrambling of information, and CRC are completed using system scrambling code generator and communication scrambler
Data check.
Based on same inventive concept, present invention also offers a kind of maritime satellite communications signal acceptance method, due to this side
The principle that method solves problem is similar to a kind of foregoing maritime satellite communications receiving system function, therefore the implementation of this method can
Repeated no more with by aforementioned system Implement of Function Module, repeating part.
Referring to Fig. 8, present invention also offers a kind of maritime satellite communications signal acceptance method, comprise the following steps：
Step S100, the first DVB are to global beam channel all the way and the satellite communication of zone beam channel all the way
The reception of signal and dissection process；
The reception and dissection process of step S200, the second DVB to the satellite communication signals of narrow spot beam channel；
The reception and parsing of step S300, the 3rd DVB to the reversely satellite communication signals of application and Traffic Channel
Processing.
It is preferred that the satellite of first DVB zone beam channel to global beam channel all the way and all the way leads to
Believe reception and the dissection process of signal, specifically include following steps：
The down-converted module in first fpga chip is in global beam channel and zone beam channel
Satellite communication signals intermediate-freuqncy signal carry out mixing operation move to baseband signal, by the satellite communication signals after Frequency mixing processing
Send to the filtering process module；
The filtering process module in first fpga chip carries out filtering extraction processing to satellite communication signals and grasped
Make, the satellite communication signals after filtering process are sent to frequency deviation measurement module；
The frequency deviation measurement module in first fpga chip carries out preliminary surveying to satellite communication signals frequency deviation, and
Feed back to the down-converted module and carry out frequency deviation convergence；
The synchronization character matching module in first fpga chip synchronizes word matching behaviour to satellite communication signals
Make, and be sent to skew compensating module；
The skew compensating module in first fpga chip carries out skew compensating operation to satellite communication signals, and
Satellite communication signals after skew is handled are sent to first dsp chip；
Defending in global beam channel and zone beam channel that described two first dsp chips are also sended over to FPGA
Star signal of communication is demodulated, deinterleaved, Turbo is decoded, descramble, CRC check and information analysis are handled, so as to complete global ripple
The information reverting operation of the satellite communication signals of Shu Xindao and zone beam channel.
It is preferred that second DVB to the reception and parsing of the satellite communication signals of narrow spot beam channel at
Reason, specifically includes following steps：
The down-converted module in second fpga chip is in the satellite communication signals in narrow channel
Frequency signal carries out mixing operation and moved to baseband signal, and the satellite communication signals after Frequency mixing processing are sent to the filtering process
Module；
Filtering process module described in second fpga chip carries out filtering extraction processing to satellite communication signals and operated,
Satellite communication signals after filtering process are sent to frequency deviation measurement module；
Frequency deviation measurement module described in second fpga chip carries out preliminary surveying to satellite communication signals frequency deviation, and instead
The down-converted module of feeding carries out frequency deviation convergence；
Synchronization character matching module synchronizes word matching operation to satellite communication signals described in second fpga chip,
And it is sent to skew compensating module；
Skew compensating module described in second fpga chip carries out skew compensating operation to satellite communication signals, and will
Satellite communication signals after skew processing are sent to second dsp chip；
Satellite communication signals in the also common narrow channel sended over to FPGA of described two second dsp chips are carried out
Demodulation, deinterleaving, Turbo decodings, descrambling, CRC check and information analysis processing, so as to complete the satellite communication letter of narrow channel
Number information reverting operation.
It is preferred that reception of the 3rd DVB to the reversely satellite communication signals of application and Traffic Channel is conciliate
Analysis is handled, and specifically includes following steps：
Down-converted module described in 3rd fpga chip is to reversely application and all the way reverse traffic channel all the way
In satellite communication signals intermediate-freuqncy signal carry out mixing operation move to baseband signal, by after Frequency mixing processing satellite communication believe
Number send to the filtering process module；
Filtering process module described in 3rd fpga chip carries out filtering extraction processing to satellite communication signals and operated,
Satellite communication signals after filtering process are sent to frequency deviation measurement module；
Signalling channel judge module carries out parallel processing to two paths of signals respectively described in 3rd fpga chip, in real time
Determine that signal is originated, and signal is sent in synchronization character matching module；
Synchronization character matching module synchronizes word matching operation to satellite communication signals described in 3rd fpga chip,
And it is sent to FIFO processing modules；
FIFO processing modules described in 3rd fpga chip create same with entering according to the satellite communication signals after reception
Dequeue；The signal of communication of each data frame is reduced according to same dequeue is entered together, and is sent to the 3rd dsp chip；
The reversely application and all the way in reverse traffic channel all the way that described two 3rd dsp chips are also sended over to FPGA
Satellite communication signals be demodulated, deinterleave, Turbo decoding, descrambling, CRC check and information analysis processing, so as to complete one
Road reversely application and the information reverting operation of the satellite communication signals of reverse traffic channel all the way.
Maritime satellite communications receiving system provided in an embodiment of the present invention and method, with widely used, integrated level
Height, compact, structure is reliable, steady operation and other merits, can complete to two kinds of global beam channel and zone beam channel
The reception of channel and dissection process.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (5)
1. a kind of maritime satellite communications receiving system, it is characterised in that including host computer and satellite reception platform, it is described on
Position machine is communicated to connect with the satellite reception platform network interface, wherein：
The satellite reception platform includes the first DVB, the second DVB and the 3rd DVB, wherein：
First DVB, for the global beam channel all the way and all the way satellite communication signals of zone beam channel
Reception and dissection process；
Second DVB, reception and dissection process for the satellite communication signals to narrow spot beam channel；
3rd DVB, at the reception and parsing to the reversely satellite communication signals of application and Traffic Channel
Reason；
First DVB includes the first fpga chip and two the first dsp chips, wherein：
First fpga chip, for becoming under the numeral to the two communication channels of global beam channel and zone beam channel
Frequently, filtering extraction, frequency correction, synchronization character matching and skew compensation deals；
First fpga chip includes down-converted module, filtering process module, frequency deviation measurement module, synchronization character matching mould
Block and skew compensating module, wherein：
The down-converted module, for the intermediate frequency to the satellite communication signals in global beam channel and zone beam channel
Signal carries out mixing operation and moved to baseband signal, and the satellite communication signals after Frequency mixing processing are sent to the filtering process mould
Block；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, for defending
Star signal of communication carries out filtering extraction processing operation, and the satellite communication signals after filtering process are sent to frequency deviation measurement module；
The frequency deviation measurement module, for carrying out preliminary surveying to satellite communication signals frequency deviation, and feeds back at the down coversion
Manage module and carry out frequency deviation convergence；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to skew compensation
Module；
The skew compensating module, for satellite communication signals to be carried out with skew compensating operation, and the satellite after skew is handled
Signal of communication is sent to first dsp chip；
Described two first dsp chips are additionally operable to defending in the global beam channel and zone beam channel that are sended over to FPGA
Star signal of communication is demodulated, deinterleaved, Turbo is decoded, descramble, CRC check and information analysis are handled, so as to complete global ripple
The information reverting operation of the satellite communication signals of Shu Xindao and zone beam channel；
Second DVB includes the second fpga chip and two the second dsp chips, wherein：
Second fpga chip, for being matched to the Digital Down Convert of narrow channel, filtering extraction, frequency correction, synchronization character
With skew compensation deals；Described two second dsp chips, decoding, descrambling and communication for completing jointly to narrow channel are grasped
Make；
Second fpga chip includes down-converted module, filtering process module, frequency deviation measurement module, synchronization character matching mould
Block and skew compensating module, wherein：
The down-converted module, carries out mixing operation for the intermediate-freuqncy signal to the satellite communication signals in narrow channel and removes
Baseband signal is moved to, the satellite communication signals after Frequency mixing processing are sent to the filtering process module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, for defending
Star signal of communication carries out filtering extraction processing operation, and the satellite communication signals after filtering process are sent to frequency deviation measurement module；
The frequency deviation measurement module, for carrying out preliminary surveying to satellite communication signals frequency deviation, and feeds back at the down coversion
Manage module and carry out frequency deviation convergence；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to skew compensation
Module；
The skew compensating module, for satellite communication signals to be carried out with skew compensating operation, and the satellite after skew is handled
Signal of communication is sent to second dsp chip；
The satellite communication signals that described two second dsp chips are additionally operable in the common narrow channel sended over to FPGA are carried out
Demodulation, deinterleaving, Turbo decodings, descrambling, CRC check and information analysis processing, so as to complete the satellite communication letter of narrow channel
Number information reverting operation；
3rd DVB includes the 3rd fpga chip and two the 3rd dsp chips, wherein：
3rd fpga chip, for complete system all the way reversely application and all the way the Digital Down Convert of reverse traffic channel,
Filtering extraction, signalling channel judge, synchronization character is matched and FIFO processing；
The down-converted module, for reversely applying and the satellite communication signals in reverse traffic channel all the way all the way
Intermediate-freuqncy signal carries out mixing operation and moved to baseband signal, and the satellite communication signals after Frequency mixing processing are sent to the filtering
Manage module；
The filtering process module includes CIC decimation filters and HB decimation filters and FIR shaping filters, for defending
Star signal of communication carries out filtering extraction processing operation, and the satellite communication signals after filtering process are sent to frequency deviation measurement module；
The signalling channel judge module, for carrying out parallel processing respectively to two paths of signals, determines signal source in real time, and will
Signal is sent in synchronization character matching module；
The synchronization character matching module, for satellite communication signals to be synchronized with word matching operation, and is sent to FIFO processing
Module；
The FIFO processing modules, same dequeue is entered together for being created according to the satellite communication signals after reception；According to same with entering
Dequeue reduces the signal of communication of each data frame, and is sent to the 3rd dsp chip；
Two the 3rd dsp chips, the reversely application and all the way in reverse traffic channel all the way for being additionally operable to send over FPGA
Satellite communication signals are demodulated, deinterleaved, Turbo is decoded, descramble, CRC check and information analysis are handled, so as to complete all the way
Reversely application and all the way the information reverting operation of the satellite communication signals of reverse traffic channel.
2. maritime satellite communications receiving system as claimed in claim 1, it is characterised in that
The host computer is PC；
The host computer passes through RJ45 network interface connections with multiple DVBs respectively.
3. a kind of maritime satellite communications signal acceptance method, it is characterised in that comprise the following steps：
First DVB to global beam channel all the way and all the way the reception of the satellite communication signals of zone beam channel and
Dissection process；
Reception and dissection process of second DVB to the satellite communication signals of narrow spot beam channel；
3rd DVB is to the reversely reception of the satellite communication signals of application and Traffic Channel and dissection process；
First DVB satellite communication signals of zone beam channel to global beam channel all the way and all the way connect
Receive and dissection process, specifically include following steps：
Down-converted module in first fpga chip is believed the satellite communication in global beam channel and zone beam channel
Number intermediate-freuqncy signal carry out mixing operation move to baseband signal, the satellite communication signals after Frequency mixing processing are sent to filtering
Manage module；
The filtering process module in first fpga chip carries out filtering extraction processing to satellite communication signals and operated, will
Satellite communication signals after filtering process are sent to frequency deviation measurement module；
The frequency deviation measurement module in first fpga chip carries out preliminary surveying to satellite communication signals frequency deviation, and feeds back
Frequency deviation convergence is carried out to the down-converted module；
Synchronization character matching module in first fpga chip synchronizes word matching operation to satellite communication signals, and sends
Give skew compensating module；
The skew compensating module in first fpga chip carries out skew compensating operation to satellite communication signals, and by phase
Satellite communication signals partially after processing are sent to the first dsp chip；
Satellite communication letter in global beam channel and zone beam channel that two the first dsp chips are also sended over to FPGA
Number be demodulated, deinterleave, Turbo decodings, descrambling, CRC check and information analysis processing so that complete global beam channel and
The information reverting operation of the satellite communication signals of zone beam channel.
4. maritime satellite communications signal acceptance method as claimed in claim 3, it is characterised in that
Reception and dissection process of second DVB to the satellite communication signals of narrow spot beam channel, specifically include as
Lower step：
The down-converted module in second fpga chip is entered to the intermediate-freuqncy signal of the satellite communication signals in narrow channel
Row mixing operation is moved to baseband signal, and the satellite communication signals after Frequency mixing processing are sent to the filtering process module；
Filtering process module described in second fpga chip carries out filtering extraction processing to satellite communication signals and operated, and will filter
Satellite communication signals after ripple processing are sent to frequency deviation measurement module；
Frequency deviation measurement module described in second fpga chip carries out preliminary surveying to satellite communication signals frequency deviation, and feeds back to
The down-converted module carries out frequency deviation convergence；
Synchronization character matching module synchronizes word matching operation to satellite communication signals described in second fpga chip, concurrently
Give skew compensating module；
Skew compensating module described in second fpga chip carries out skew compensating operation to satellite communication signals, and by skew
Satellite communication signals after processing are sent to the second dsp chip；
Satellite communication signals in the also common narrow channel sended over to FPGA of two the second dsp chips are demodulated, solved
Interweave, Turbo is decoded, descramble, CRC check and information analysis are handled, so as to complete the letter of the satellite communication signals of narrow channel
Cease restoring operation.
5. maritime satellite communications signal acceptance method as claimed in claim 4, it is characterised in that
3rd DVB to reversely application and Traffic Channel satellite communication signals reception and dissection process, specifically
Comprise the following steps：
Down-converted module described in 3rd fpga chip is to reversely application and all the way satellite in reverse traffic channel all the way
The intermediate-freuqncy signal of signal of communication carries out mixing operation and moved to baseband signal, by the satellite communication signals after Frequency mixing processing send to
The filtering process module；
Filtering process module described in 3rd fpga chip carries out filtering extraction processing to satellite communication signals and operated, and will filter
Satellite communication signals after ripple processing are sent to frequency deviation measurement module；
Signalling channel judge module carries out parallel processing respectively to two paths of signals described in 3rd fpga chip, determines in real time
Signal is originated, and signal is sent in synchronization character matching module；
Synchronization character matching module synchronizes word matching operation to satellite communication signals described in 3rd fpga chip, concurrently
Give FIFO processing modules；
FIFO processing modules described in 3rd fpga chip create to enter together according to the satellite communication signals after reception goes out together team
Row；The signal of communication of each data frame is reduced according to same dequeue is entered together, and is sent to the 3rd dsp chip；
What two the 3rd dsp chips were also sended over to FPGA reversely applies leading to the satellite in reverse traffic channel all the way all the way
Letter signal is demodulated, deinterleaved, Turbo is decoded, descramble, CRC check and information analysis are handled, so as to complete reverse Shen all the way
Please the information reverting with the satellite communication signals of reverse traffic channel all the way is operated.
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