CN103795456A - Maritime satellite communication signal receiving system and method - Google Patents
Maritime satellite communication signal receiving system and method Download PDFInfo
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- CN103795456A CN103795456A CN201410046685.3A CN201410046685A CN103795456A CN 103795456 A CN103795456 A CN 103795456A CN 201410046685 A CN201410046685 A CN 201410046685A CN 103795456 A CN103795456 A CN 103795456A
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Abstract
The invention discloses a maritime satellite communication signal receiving system and method. The method includes the following steps that satellite communication signals of a global beam channel and satellite communication signals of a regional beam channel are received, analyzed and processed by a first satellite receiver; satellite communication signals of a narrow spot beam channel are received, analyzed and processed by a second satellite receiver; satellite communication signals of a reverse application and service channel are received, analyzed and processed by a third satellite receiver. The maritime satellite communication signal receiving system and method have the advantages that the application range is wide, the integration degree is high, the system is exquisite and reliable in structure, and good working stability is achieved; by means of the maritime satellite communication signal receiving system and method, receiving, analysis and processing of the global beam channel and the regional beam channel can be completed.
Description
Technical field
The present invention relates to technical field of satellite communication, relate in particular to a kind of maritime satellite communications receiving system and method.
Background technology
In order to adapt to, my army's Future Information is fought and the demand of current anti-terrorism stability maintenance, and we need to intercept and capture some satellite communication signals, think that information fighting and anti-terrorism provide Information Assurance; At present, the world there is no to maritime affairs four generations communication service information receive, the special receiver of demodulation process, the maritime affairs four generations receiver that some factory develops can only be by receiving maritime affairs four generations signal of communication frequency spectrum, obtain the parameter of a few channels aspect of maritime affairs four generations communication, and helpless to key parameter, information and the business of maritime affairs four generations communication.
In the time of specific implementation, be difficult to a kind of receiver platform and can complete reception and the dissection process to global beam channel and two kinds of channels of zone beam channel.
Summary of the invention
The object of the present invention is to provide a kind of maritime satellite communications receiving system and method, to solve the problems of the technologies described above.
In order to achieve the above object, technical scheme of the present invention is achieved in that
A kind of maritime satellite communications receiving system, comprises host computer and satellite reception platform, described host computer and the communication connection of described satellite reception platform network interface, wherein:
Described satellite reception platform comprises the first satellite receiver, the second satellite receiver, the 3rd satellite receiver, wherein:
Described the first satellite receiver, for reception and the dissection process of the satellite communication signal of global beam channel He Yi road, Dui Yi road zone beam channel;
Described the second satellite receiver, for reception and the dissection process of the satellite communication signal to narrow spot beam channel;
Described the 3rd satellite receiver, for reception and the dissection process of the satellite communication signal to reverse application and Traffic Channel.
Preferably, described the first satellite receiver comprises the first fpga chip and two the first dsp chips, wherein:
Described the first fpga chip, for the Digital Down Convert to global beam channel and these two communication channels of zone beam channel, filtering extraction, frequency correction, synchronization character coupling and skew compensation deals;
Described the first fpga chip comprises down-converted module, filtering processing module, frequency deviation measurement module, synchronization character matching module and skew compensating module, wherein:
Described down-converted module, carries out mixing operation for the intermediate-freuqncy signal of the satellite communication signal to global beam channel and zone beam channel and moves to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module, for satellite communication signal frequency deviation is carried out to preliminary surveying, and feeds back to described down-converted module and carries out frequency deviation convergence;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to skew compensating module;
Described skew compensating module, for satellite communication signal is carried out to skew compensating operation, and sends to described the first dsp chip by satellite communication signal after treatment skew;
Described two the first dsp chips also carry out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing for global beam channel that FPGA is sended over and the satellite communication signal of zone beam channel, thereby complete the information reverting operation of the satellite communication signal of global beam channel and zone beam channel.
Preferably, described the second satellite receiver comprises the second fpga chip and two the second dsp chips, wherein:
Described the second fpga chip, for the Digital Down Convert to narrow some channel, filtering extraction, frequency correction, synchronization character coupling and skew compensation deals; Described two the second dsp chips, for jointly completing decoding, descrambling and the traffic operation to narrow some channel;
Described the second fpga chip comprises down-converted module, filtering processing module, frequency deviation measurement module, synchronization character matching module and skew compensating module, wherein:
Described down-converted module, carries out mixing operation for the intermediate-freuqncy signal of the satellite communication signal to narrow some channel and moves to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module, for satellite communication signal frequency deviation is carried out to preliminary surveying, and feeds back to described down-converted module and carries out frequency deviation convergence;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to skew compensating module;
Described skew compensating module, for satellite communication signal is carried out to skew compensating operation, and sends to described the second dsp chip by satellite communication signal after treatment skew;
Described two the second dsp chips also carry out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing for the satellite communication signal of the common narrow some channel that FPGA is sended over, thereby complete the information reverting operation of the satellite communication signal of narrow some channel.
Preferably, described the 3rd satellite receiver comprises the 3rd fpga chip and two the 3rd dsp chips, wherein:
Described the 3rd fpga chip, oppositely applies for that for completion system one tunnel Digital Down Convert, filtering extraction, signalling channel judgement, synchronization character coupling and the FIFO of He Yi road reverse traffic channel processes;
Described the 3rd fpga chip comprises down-converted module, filtering processing module, signalling channel judge module, synchronization character matching module, FIFO processing module, wherein:
Described down-converted module, oppositely applies for that for Dui Yi road the intermediate-freuqncy signal of the satellite communication signal of He Yi road reverse traffic channel carries out mixing operation and move to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described signalling channel judge module, for two paths of signals is carried out respectively to parallel processing, determines in real time signal source, and signal is delivered in synchronization character matching module;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to FIFO processing module;
Described FIFO processing module, for entering together same dequeue according to the satellite communication signal creation after receiving; According to reducing the signal of communication of each Frame with entering same dequeue, and send to the 3rd dsp chip;
Described two the 3rd dsp chips, the satellite communication signal of also oppositely applying for He Yi road reverse traffic channel for FPGA being sended over to Yi road carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of oppositely applying for He Yi road reverse traffic channel in a road.
Preferably, described host computer is PC;
Described host computer is connected by RJ45 network interface with multiple satellite receiver respectively.
Correspondingly, the present invention also provides a kind of maritime satellite communications signal acceptance method, comprises the steps:
Reception and the dissection process of the satellite communication signal of the first global beam channel He Yi road, satellite receiver Dui Yi road zone beam channel;
Reception and the dissection process of the satellite communication signal of the second satellite receiver to narrow spot beam channel;
Reception and the dissection process of the satellite communication signal of the 3rd satellite receiver to reverse application and Traffic Channel.
Preferably, reception and the dissection process of the satellite communication signal of described the first global beam channel He Yi road, satellite receiver Dui Yi road zone beam channel, specifically comprise the steps:
Described down-converted module in described the first fpga chip is carried out mixing operation to the intermediate-freuqncy signal of the satellite communication signal in global beam channel and zone beam channel and is moved to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module in described the first fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module in described the first fpga chip is carried out preliminary surveying to satellite communication signal frequency deviation, and feeds back to described down-converted module and carry out frequency deviation convergence;
Described synchronization character matching module in described the first fpga chip carries out synchronization character matching operation to satellite communication signal, and sends to skew compensating module;
Described skew compensating module in described the first fpga chip carries out skew compensating operation to satellite communication signal, and satellite communication signal after treatment skew is sent to described the first dsp chip;
Satellite communication signal in global beam channel and zone beam channel that described two the first dsp chips also send over FPGA carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of global beam channel and zone beam channel.
Preferably, reception and the dissection process of the satellite communication signal of described the second satellite receiver to narrow spot beam channel, specifically comprise the steps:
Described down-converted module in described the second fpga chip is carried out mixing operation to the intermediate-freuqncy signal of the satellite communication signal in narrow some channel and is moved to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Filtering processing module described in described the second fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described in described the second fpga chip, frequency deviation measurement module is carried out preliminary surveying to satellite communication signal frequency deviation, and feeds back to described down-converted module and carry out frequency deviation convergence;
Described in described the second fpga chip, synchronization character matching module carries out synchronization character matching operation to satellite communication signal, and sends to skew compensating module;
Described in described the second fpga chip, skew compensating module carries out skew compensating operation to satellite communication signal, and satellite communication signal after treatment skew is sent to described the second dsp chip;
Satellite communication signal in the narrow some channel that described two the second dsp chips also send over FPGA jointly carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of narrow some channel.
Preferably, reception and the dissection process of the satellite communication signal of described the 3rd satellite receiver to reverse application and Traffic Channel, specifically comprise the steps:
Down-converted module Dui Yi road described in described the 3rd fpga chip oppositely applies for that the intermediate-freuqncy signal of the satellite communication signal in the reverse traffic channel of He Yi road carries out mixing operation and move to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Filtering processing module described in described the 3rd fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described in described the 3rd fpga chip, signalling channel judge module carries out respectively parallel processing to two paths of signals, determines in real time signal source, and signal is delivered in synchronization character matching module;
Described in described the 3rd fpga chip, synchronization character matching module carries out synchronization character matching operation to satellite communication signal, and sends to FIFO processing module;
FIFO processing module described in described the 3rd fpga chip is entered together same dequeue according to the satellite communication signal creation after receiving; According to reducing the signal of communication of each Frame with entering same dequeue, and send to the 3rd dsp chip;
Described two the 3rd dsp chips also send over Yi road to FPGA and oppositely apply for that the satellite communication signal in the reverse traffic channel of He Yi road carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby complete the information reverting operation of the satellite communication signal of oppositely applying for He Yi road reverse traffic channel in a road.
Compared with prior art, the advantage of the embodiment of the present invention is:
A kind of maritime satellite communications receiving system provided by the invention and method, wherein this receiving system, mainly comprises two major parts of host computer and satellite reception platform;
Satellite reception platform comprises the first satellite receiver, the second satellite receiver and the 3rd satellite receiver, and three kinds of satellite receiver receive the satellite communication signal of different channels and carry out pretreatment operation (comprising the processing such as power amplification, analog-to-digital conversion and filtering); First, the first satellite receiver, for reception and the dissection process of the satellite communication signal of global beam channel He Yi road, Dui Yi road zone beam channel; The second satellite receiver, for reception and the dissection process of the satellite communication signal to narrow spot beam channel; The 3rd satellite receiver, for reception and the dissection process of the satellite communication signal to reverse application and Traffic Channel.Three kinds of receivers are mainly made up of global beam Channel Processing software, zone beam Channel Processing software, narrow spot beam Channel Processing software, request channel process software and communication software, and all kinds of Channel Processing software is embedded into respectively and in fpga chip and dsp chip, completes function (each satellite receiver disposes above-mentioned similar hardware) separately.When specific implementation, the first satellite receiver is mainly responsible for the parsing of 1 road global beam channel and 1 road zone beam channel, and wherein FPGA mainly completes the processing such as Digital Down Convert, filtering extraction, frequency correction, synchronization character coupling of two channel banks; Two DSP complete respectively channel decoding, the descrambling to the whole world and zone beam channel and communicate by letter.The second satellite receiver is mainly responsible for parsing to narrow some channel, and wherein FPGA mainly completes the processing such as Digital Down Convert, filtering extraction, frequency correction, synchronization character coupling of 1 narrow some channel; Two DSP jointly complete decoding, the descrambling to narrow some channel and communicate by letter.The 3rd satellite receiver is mainly responsible for the parsing of system reverse application and Traffic Channel, the wherein processing such as Digital Down Convert, filtering extraction of main completion system one reverse request channel He Yi road, the tunnel reverse traffic channel of FPGA; Two DSP complete respectively the function such as channel demodulation, decoding.
The maritime satellite communications receiving system that example of the present invention provides, by demodulation, processing to maritime affairs four generations communication satellite global beam and zone beam signal, parse the key parameters such as maritime affairs four generations communication satellite system wave beam distribution situation and service communication situation, applicable to the monitoring to the maritime affairs four generations communication information, obtain maritime affairs four generations communication intelligence, can be widely used in anti-terrorism stability maintenance and military struggle field.
Accompanying drawing explanation
The structural representation of the maritime satellite communications receiving system that Fig. 1 provides for the embodiment of the present invention;
The structural representation of the first satellite receiver in the maritime satellite communications receiving system that Fig. 2 provides for the embodiment of the present invention;
The particular hardware structural representation of the first satellite receiver in the maritime satellite communications receiving system that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the second satellite receiver in the maritime satellite communications receiving system that Fig. 4 provides for the embodiment of the present invention;
The particular hardware structural representation of the second satellite receiver in the maritime satellite communications receiving system that Fig. 5 provides for the embodiment of the present invention;
The structural representation of the 3rd satellite receiver in the maritime satellite communications receiving system that Fig. 6 provides for the embodiment of the present invention;
The particular hardware structural representation of the 3rd satellite receiver in the maritime satellite communications receiving system that Fig. 7 provides for the embodiment of the present invention;
The schematic flow sheet of the maritime satellite communications signal acceptance method that Fig. 8 provides for the embodiment of the present invention.
Embodiment
Also by reference to the accompanying drawings the present invention is described in further detail below by specific embodiment.
Referring to Fig. 1, example of the present invention provides a kind of maritime satellite communications receiving system 1, comprises host computer 10 and satellite reception platform 20, described host computer 10 and described satellite reception platform 20 use network interface communication connections, wherein:
Described satellite reception platform 20 comprises the first satellite receiver 21, the second satellite receiver 22 and the 3rd satellite receiver 23, wherein:
Described the first satellite receiver 21, for reception and the dissection process of the satellite communication signal of global beam channel He Yi road, Dui Yi road zone beam channel;
Described the second satellite receiver 22, for reception and the dissection process of the satellite communication signal to narrow spot beam channel;
Described the 3rd satellite receiver 23, for reception and the dissection process of the satellite communication signal to reverse application and Traffic Channel.
It should be noted that: in embodiments of the present invention, maritime satellite communications receiving system comprises host computer and two major parts of satellite reception platform, satellite receiver reception & disposal satellite-signal, host computer is responsible for the control to each operation of receiver state.
Three kinds of satellite receiver receive satellite communication signal and carry out pretreatment operation (comprising the processing such as power amplification, analog-to-digital conversion and filtering); First, the first satellite receiver, for reception and the dissection process of the satellite communication signal of global beam channel He Yi road, Dui Yi road zone beam channel; The second satellite receiver, for reception and the dissection process of the satellite communication signal to narrow spot beam channel; The 3rd satellite receiver, for reception and the dissection process of the satellite communication signal to reverse application and Traffic Channel.Three kinds of receivers are mainly made up of global beam Channel Processing software, zone beam Channel Processing software, narrow spot beam Channel Processing software, request channel process software and communication software, and all kinds of Channel Processing software is embedded into respectively and in fpga chip and dsp chip, completes function (each satellite receiver disposes above-mentioned similar hardware) separately.When specific implementation, the first satellite receiver is mainly responsible for the parsing of 1 road global beam channel and 1 road zone beam channel, and wherein FPGA mainly completes the processing such as Digital Down Convert, filtering extraction, frequency correction, synchronization character coupling of two channel banks; Two DSP complete respectively channel decoding, the descrambling to the whole world and zone beam channel and communicate by letter.The second satellite receiver is mainly responsible for parsing to narrow some channel, and wherein FPGA mainly completes the processing such as Digital Down Convert, filtering extraction, frequency correction, synchronization character coupling of 1 narrow some channel; Two DSP jointly complete decoding, the descrambling to narrow some channel and communicate by letter.The 3rd satellite receiver is mainly responsible for the parsing of system reverse application and Traffic Channel, and wherein the processing such as Digital Down Convert, filtering extraction of He Yi road reverse traffic channel is oppositely applied on the main completion system of FPGA one tunnel; Two DSP complete respectively the function such as channel demodulation, decoding.
In the embodiment of the present invention, receiver platform hardware mainly adopts now that (said chip is integrated in and controls on mainboard than large scale integrated chip (LSI chip)s such as higher-end, the relatively stable FPGA of performance, DSP, above-mentioned control mainboard also comprises other components and parts, for example interface arrangement, peripheral circuit and serial ports), have functions such as analog signal figure sampling, Digital Signal Processing, baseband signal modulation, can realize the parsing to marine satellite signal by downloading demodulating and decoding software.
Referring to Fig. 2 and Fig. 3, preferably, described the first satellite receiver 21 comprises the first fpga chip 210 and two the first dsp chips 211, wherein:
Described the first fpga chip, for the Digital Down Convert to global beam channel and these two communication channels of zone beam channel, filtering extraction, frequency correction, synchronization character coupling and skew compensation deals;
Described the first fpga chip comprises down-converted module, filtering processing module, frequency deviation measurement module, synchronization character matching module and skew compensating module, wherein:
Described down-converted module, carries out mixing operation for the intermediate-freuqncy signal of the satellite communication signal to global beam channel and zone beam channel and moves to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module, for satellite communication signal frequency deviation is carried out to preliminary surveying, and feeds back to described down-converted module and carries out frequency deviation convergence;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to skew compensating module;
Described skew compensating module, for satellite communication signal is carried out to skew compensating operation, and sends to described the first dsp chip by satellite communication signal after treatment skew;
Described two the first dsp chips also carry out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing for global beam channel that FPGA is sended over and the satellite communication signal of zone beam channel, thereby complete the information reverting operation of the satellite communication signal of global beam channel and zone beam channel.
It should be noted that, in embodiments of the present invention, wherein FPGA mainly completes the processing such as the Digital Down Convert, filtering extraction, frequency correction, synchronization character coupling of two channel banks; Two DSP complete respectively channel decoding, the descrambling to the whole world and zone beam channel and communicate by letter.
Particularly, (1) parsing of global beam channel: the intermediate-freuqncy signal of ADC sampling is changed to baseband signal by logical Digital Down Convert, with the method that the relation of ring channel speed combines by " CIC decimation filter " and " HB decimation filter ", signal is carried out to extraction efficient, low time delay according to sampling rate, to reduce sample rate, reduce operand.Can the design of formed filter be the key that correctly recover data, and the square root raised cosine filter according to the employing of system feature with transmitting terminal identical parameters, well completes the matched filtering to signal.Measure in real time baseband signal frequency deviation for correction signal frequency deviation adopts " frequency deviation detection module ", and feed back to leading portion Digital Down Converter Module in good time, reach the object of synchronizeing with system frequency.In this system, information flow forms a frame with some code elements, goes out transmission take frame as the unit information of carrying out.For realizing synchronous reception to signal, by related operation that synchronous code waveform is slided, using corresponding correlation peak one group as optimal sample point, and complete the bit synchronization to information.Then with pilot tone as a reference, determine sequence initial phase.
(2) parsing of zone beam channel: zone beam and global beam channel parameter difference to some extent, in conjunction with its concrete channel parameter design modules, complete the parsing to regional signal with similar step.
Referring to Fig. 4 and Fig. 5, preferably, described the second satellite receiver 22 comprises the second fpga chip 220 and two the second dsp chips 221, wherein:
Described the second fpga chip, for the Digital Down Convert to narrow some channel, filtering extraction, frequency correction, synchronization character coupling and skew compensation deals; Described two the second dsp chips, for jointly completing decoding, descrambling and the traffic operation to narrow some channel;
Described the second fpga chip comprises down-converted module, filtering processing module, frequency deviation measurement module, synchronization character matching module and skew compensating module, wherein:
Described down-converted module, carries out mixing operation for the intermediate-freuqncy signal of the satellite communication signal to narrow some channel and moves to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module, for satellite communication signal frequency deviation is carried out to preliminary surveying, and feeds back to described down-converted module and carries out frequency deviation convergence;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to skew compensating module;
Described skew compensating module, for satellite communication signal is carried out to skew compensating operation, and sends to described the second dsp chip by satellite communication signal after treatment skew;
Described two the second dsp chips also carry out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing for the satellite communication signal of the common narrow some channel that FPGA is sended over, thereby complete the information reverting operation of the satellite communication signal of narrow some channel.
It should be noted that the parsing of narrow spot beam channel: compared with other channels, narrow spot beam channel speed is higher, need two DSP parallel processings can complete the processing to a narrow some channel.
Referring to Fig. 6 and Fig. 7, preferably, described the 3rd satellite receiver 23 comprises the 3rd fpga chip 230 and two the 3rd dsp chips 231, wherein:
Described the 3rd fpga chip 230, oppositely applies for that for completion system one tunnel Digital Down Convert, filtering extraction, signalling channel judgement, synchronization character coupling and the FIFO of He Yi road reverse traffic channel processes;
Described down-converted module, oppositely applies for that for Dui Yi road the intermediate-freuqncy signal of the satellite communication signal of He Yi road reverse traffic channel carries out mixing operation and move to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described signalling channel judge module, for two paths of signals is carried out respectively to parallel processing, determines in real time signal source, and signal is delivered in synchronization character matching module;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to FIFO processing module;
Described FIFO processing module, for entering together same dequeue according to the satellite communication signal creation after receiving; According to reducing the signal of communication of each Frame with entering same dequeue, and send to the 3rd dsp chip;
Described two the 3rd dsp chips, the satellite communication signal of also oppositely applying for He Yi road reverse traffic channel for FPGA being sended over to Yi road carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of oppositely applying for He Yi road reverse traffic channel in a road.
It should be noted that the parsing of (1) request channel: may appear in two adjacent channels according to system feature request channel, economize on resources for improving efficiency of algorithm.First two paths of signals is carried out respectively to parallel processing, then determine in real time signal source by " judging by signalling channel " module, and signal is delivered in synchronization character matching module and is further processed.The data that DSP1 sends over FPGA are carried out QPSK demodulation, Turbo decoding, descrambling, verification and can complete the reduction of message.
(2) parsing of Traffic Channel: Traffic Channel may have two kinds of channel types so determine its channel type according to communication signaling, selects one to process in program.
Wherein, the data that DSP2 sends over FPGA are carried out QPSK or 16QAM demodulation, Turbo decoding, descrambling, verification and can complete the reduction of message.
It should be noted that, FIFO processing module, for entering together same dequeue list according to the satellite communication signal creation after receiving; Frame synchronization counter, in the time initially receiving satellite communication signal, arranges frame synchronization counter initial value, carries out timing operation, calculates with the queue frame number and the timeslot number that enter the signal of communication of each Frame in same dequeue list;
Described dsp chip carries out Samples selecting to satellite communication signal, proofreaies and correct frequency deviation, proofreaies and correct skew, demodulation, deinterleaving, decoding, CRC check and information analysis processing; When current satellite communication signal is resolved, obtain and inquire about with the queue frame number and the timeslot number that enter the signal of communication of current data frame in same dequeue list, calculate the migration amount of the clock signal of dsp chip in the satellite receiver corresponding signal of communication of current data frame, and feed back described migration amount to frame synchronization counter; Frame synchronization counter, also for according to described migration amount, to adjusting the clock signal of dsp chip in satellite receiver, after migration, completes the clock signal of dsp chip and the simultaneous operation of satellite communication signal in satellite receiver.
Preferably, described host computer is PC;
Described host computer is connected by RJ45 network interface with multiple satellite receiver respectively.
Particularly, above-mentioned host computer is to comprise computer or the control system of industrial computer, can receive satellite communications data.All right external other communication interfaces of above-mentioned fpga chip, comprise the interfaces such as network interface (for example: RJ45), serial communication interface.Above-mentioned RS232 or RS485 bus mode connect just one of them preferred technical scheme, also may make other communication modes such as lan network or Ethernet connection, and example of the present invention repeats no longer one by one to this.
In addition, fpga chip is as control core element, and integrated above-mentioned various modules, for realizing different functions.Fpga chip is developing the high-performance microcontroller of coming based on MCU, preferably, it adopts following configuration: CPU up to 500,000 gate logic element resources; Clock divides the active crystal oscillator of 50MHz and the active crystal oscillator of 12MHz; 64M SDRAM16 bit data interface; Capacity is that the SRAM of the 256Kx16Bit of 4Mbit tells memory; 8Mbits of SPI serial flash memory, can do FPGA config memory; Independently JPAG interface; Therefore fpga chip has high performance computation disposal ability, for example: can fast processing satellite communication signal and carry out corresponding computing.
Those skilled in the art are to be understood that, developer can utilize hardware description language (for example: Verilog HDL hardware program language) to carry out fpga chip functional development, or for example, is realized the setting of the default coding parameter information (for example: for storage and the setting of every chnnel coding parameter) of configuration and realized and processed operation by executive program by related software (: Quartues II, verilog).After program is burnt fpga chip by developer, interlock circuit is integrated into control on mainboard and realizes complete control circuit.
Various receiver in the embodiment of the present invention is taked closed-loop structure, adopts degenerative mode to complete and the Frequency Synchronization of signal.First receiver carries out AD sampling to intermediate-freuqncy signal, carries out orthogonal mixing with local oscillator NCO, after CIC and HB decimation filter, carries out low-pass filtering, forms I, the Q two-way baseband signal of 16 times of character rates.According to the feature of frame structure, adopt unique word associating DFT parallel processing to complete frame synchronization and detect and capturing frequency deviation.I, Q are divided into two-way, and the first via detects synchronization character by auto-correlation algorithm parallel capture, completes the frame synchronization of receiver and signal; The second tunnel estimates the probable ranges of frequency deviation by the signal of 16 times of character rates is carried out to 64 DFT, complete thick frequency offset correction for the first time.After sign synchronization completes, carry out a matched filtering, send into meticulous calibrating frequency module and complete inherent spurious frequency deviation correction, and feed back to NCO correction frequency deviation.Then carry out computing cross-correlation by the known UW in this locality and signal, obtain phase deviation, after phase calibration, data are sent in DSP, carry out further demodulation, decoding, descrambling and CRC check.
Specifically can reach following technique effect;
1. design of filter: the intermediate-freuqncy signal of ADC sampling is changed to baseband signal by logical Digital Down Convert, with the method that the relation of channel speed combines by " CIC decimation filter " and " HB decimation filter ", signal is carried out to extraction efficient, low time delay according to sampling rate, to reduce sample rate, reduce operand.Can the design of formed filter be the key that correctly recover data, and the square root raised cosine filter according to the employing of system feature with transmitting terminal identical parameters, well completes the preliminary filtering to signal.
2. frame synchronization designs: in this system, information flow forms a frame with some code elements, goes out transmission take frame as the unit information of carrying out.For the needs of frame synchronization, communication system is inserted synchronization character (UW) at frame head, it is that length is 40 bipolarity known array, for realizing the synchronous reception to signal, utilize this feature by related operation that synchronous code waveform is slided, using corresponding correlation peak one group as optimal sample point, and complete the frame synchronization to information.
3. Frequency Synchronization design: Frequency Synchronization adopts the mode of multistage calibrating frequency processing and closed loop feedback to realize local frequency deviation convergence.First adopt thick calibrating frequency module complete to signal frequency deviation according to a preliminary estimate after, according to channel parameter, signal is carried out to a matched filtering by matched filtering module, to reach the object to the undistorted recovery of signal.Then on the basis of thick calibrating frequency, using identical method, take thick calibrating frequency precision as scope, carry out more high-precision frequency deviation and estimate, remove inherent spurious frequency deviation, and by final frequency deviation result feedback in NCO, progressively realize the convergence of receiver frequency deviation.Adopt frequency deviation step by step to detect and coordinate the method for matched filtering compared with single-stage frequency offset processing, having advantages of can be efficiently, accurately, saving resource, and can realize the matched filtering to signal simultaneously, reach the object of final coupling reception.
4. skew Compensation Design: on the basis that completes frame synchronization, by the estimation to known synchronization character sequence phase, complete the calculating to signal skew, by signal times is reached to phase offset compensation object with twiddle factor.
5.QPSK demodulation: according to system modulation mapping relations, complete judgement demodulation.
6.Turbo decoding: use interweaving and deleting remaining table of system definition, adopt the decoding that completes of MaxLog-map algorithm, error correcting capability is more excellent compared with SOVA algorithm.
7. descrambling and verification: last, use system scrambling code generator and the scrambler of communicating by letter complete the descrambling of information, and CRC data check.
Based on same inventive concept, the present invention also provides a kind of maritime satellite communications signal acceptance method, principle and aforementioned a kind of maritime satellite communications receiving system functional similarity of dealing with problems due to the method, therefore the enforcement of the method can be passed through aforementioned system Implement of Function Module, repeats part and repeats no more.
Referring to Fig. 8, the present invention also provides a kind of maritime satellite communications signal acceptance method, comprises the steps:
Reception and the dissection process of the satellite communication signal of step S100, the first global beam channel He Yi road, satellite receiver Dui Yi road zone beam channel;
Reception and the dissection process of step S200, the satellite communication signal of the second satellite receiver to narrow spot beam channel;
Reception and the dissection process of step S300, the satellite communication signal of the 3rd satellite receiver to reverse application and Traffic Channel.
Preferably, reception and the dissection process of the satellite communication signal of described the first global beam channel He Yi road, satellite receiver Dui Yi road zone beam channel, specifically comprise the steps:
Described down-converted module in described the first fpga chip is carried out mixing operation to the intermediate-freuqncy signal of the satellite communication signal in global beam channel and zone beam channel and is moved to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module in described the first fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module in described the first fpga chip is carried out preliminary surveying to satellite communication signal frequency deviation, and feeds back to described down-converted module and carry out frequency deviation convergence;
Described synchronization character matching module in described the first fpga chip carries out synchronization character matching operation to satellite communication signal, and sends to skew compensating module;
Described skew compensating module in described the first fpga chip carries out skew compensating operation to satellite communication signal, and satellite communication signal after treatment skew is sent to described the first dsp chip;
Satellite communication signal in global beam channel and zone beam channel that described two the first dsp chips also send over FPGA carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of global beam channel and zone beam channel.
Preferably, reception and the dissection process of the satellite communication signal of described the second satellite receiver to narrow spot beam channel, specifically comprise the steps:
Described down-converted module in described the second fpga chip is carried out mixing operation to the intermediate-freuqncy signal of the satellite communication signal in narrow some channel and is moved to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Filtering processing module described in described the second fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described in described the second fpga chip, frequency deviation measurement module is carried out preliminary surveying to satellite communication signal frequency deviation, and feeds back to described down-converted module and carry out frequency deviation convergence;
Described in described the second fpga chip, synchronization character matching module carries out synchronization character matching operation to satellite communication signal, and sends to skew compensating module;
Described in described the second fpga chip, skew compensating module carries out skew compensating operation to satellite communication signal, and satellite communication signal after treatment skew is sent to described the second dsp chip;
Satellite communication signal in the narrow some channel that described two the second dsp chips also send over FPGA jointly carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of narrow some channel.
Preferably, reception and the dissection process of the satellite communication signal of described the 3rd satellite receiver to reverse application and Traffic Channel, specifically comprise the steps:
Down-converted module Dui Yi road described in described the 3rd fpga chip oppositely applies for that the intermediate-freuqncy signal of the satellite communication signal in the reverse traffic channel of He Yi road carries out mixing operation and move to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Filtering processing module described in described the 3rd fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described in described the 3rd fpga chip, signalling channel judge module carries out respectively parallel processing to two paths of signals, determines in real time signal source, and signal is delivered in synchronization character matching module;
Described in described the 3rd fpga chip, synchronization character matching module carries out synchronization character matching operation to satellite communication signal, and sends to FIFO processing module;
FIFO processing module described in described the 3rd fpga chip is entered together same dequeue according to the satellite communication signal creation after receiving; According to reducing the signal of communication of each Frame with entering same dequeue, and send to the 3rd dsp chip;
Described two the 3rd dsp chips also send over Yi road to FPGA and oppositely apply for that the satellite communication signal in the reverse traffic channel of He Yi road carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby complete the information reverting operation of the satellite communication signal of oppositely applying for He Yi road reverse traffic channel in a road.
Maritime satellite communications receiving system and method that the embodiment of the present invention provides, have of many usesly, integrated level is high, and volume is small and exquisite, reliable in structure, steady operation and other merits, can complete reception and dissection process to global beam channel and two kinds of channels of zone beam channel.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a maritime satellite communications receiving system, is characterized in that, comprises host computer and satellite reception platform, described host computer and the communication connection of described satellite reception platform network interface, wherein:
Described satellite reception platform comprises the first satellite receiver, the second satellite receiver and the 3rd satellite receiver, wherein:
Described the first satellite receiver, for reception and the dissection process of the satellite communication signal of global beam channel He Yi road, Dui Yi road zone beam channel;
Described the second satellite receiver, for reception and the dissection process of the satellite communication signal to narrow spot beam channel;
Described the 3rd satellite receiver, for reception and the dissection process of the satellite communication signal to reverse application and Traffic Channel.
2. maritime satellite communications receiving system as claimed in claim 1, is characterized in that,
Described the first satellite receiver comprises the first fpga chip and two the first dsp chips, wherein:
Described the first fpga chip, for the Digital Down Convert to global beam channel and these two communication channels of zone beam channel, filtering extraction, frequency correction, synchronization character coupling and skew compensation deals;
Described the first fpga chip comprises down-converted module, filtering processing module, frequency deviation measurement module, synchronization character matching module and skew compensating module, wherein:
Described down-converted module, carries out mixing operation for the intermediate-freuqncy signal of the satellite communication signal to global beam channel and zone beam channel and moves to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module, for satellite communication signal frequency deviation is carried out to preliminary surveying, and feeds back to described down-converted module and carries out frequency deviation convergence;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to skew compensating module;
Described skew compensating module, for satellite communication signal is carried out to skew compensating operation, and sends to described the first dsp chip by satellite communication signal after treatment skew;
Described two the first dsp chips also carry out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing for global beam channel that FPGA is sended over and the satellite communication signal of zone beam channel, thereby complete the information reverting operation of the satellite communication signal of global beam channel and zone beam channel.
3. maritime satellite communications receiving system as claimed in claim 2, is characterized in that,
Described the second satellite receiver comprises the second fpga chip and two the second dsp chips, wherein:
Described the second fpga chip, for the Digital Down Convert to narrow some channel, filtering extraction, frequency correction, synchronization character coupling and skew compensation deals; Described two the second dsp chips, for jointly completing decoding, descrambling and the traffic operation to narrow some channel;
Described the second fpga chip comprises down-converted module, filtering processing module, frequency deviation measurement module, synchronization character matching module and skew compensating module, wherein:
Described down-converted module, carries out mixing operation for the intermediate-freuqncy signal of the satellite communication signal to narrow some channel and moves to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module, for satellite communication signal frequency deviation is carried out to preliminary surveying, and feeds back to described down-converted module and carries out frequency deviation convergence;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to skew compensating module;
Described skew compensating module, for satellite communication signal is carried out to skew compensating operation, and sends to described the second dsp chip by satellite communication signal after treatment skew;
Described two the second dsp chips also carry out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing for the satellite communication signal of the common narrow some channel that FPGA is sended over, thereby complete the information reverting operation of the satellite communication signal of narrow some channel.
4. maritime satellite communications receiving system as claimed in claim 3, is characterized in that,
Described the 3rd satellite receiver comprises the 3rd fpga chip and two the 3rd dsp chips, wherein:
Described the 3rd fpga chip, oppositely applies for that for completion system one tunnel Digital Down Convert, filtering extraction, signalling channel judgement, synchronization character coupling and the FIFO of He Yi road reverse traffic channel processes;
Described the 3rd fpga chip comprises down-converted module, filtering processing module, signalling channel judge module, synchronization character matching module, FIFO processing module, wherein:
Described down-converted module, oppositely applies for that for Dui Yi road the intermediate-freuqncy signal of the satellite communication signal of He Yi road reverse traffic channel carries out mixing operation and move to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module comprises CIC decimation filter and HB decimation filter and FIR shaping filter, processes operation for satellite communication signal being carried out to filtering extraction, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described signalling channel judge module, for two paths of signals is carried out respectively to parallel processing, determines in real time signal source, and signal is delivered in synchronization character matching module;
Described synchronization character matching module, for satellite communication signal is carried out to synchronization character matching operation, and sends to FIFO processing module;
Described FIFO processing module, for entering together same dequeue according to the satellite communication signal creation after receiving; According to reducing the signal of communication of each Frame with entering same dequeue, and send to the 3rd dsp chip;
Described two the 3rd dsp chips, the satellite communication signal of also oppositely applying for He Yi road reverse traffic channel for FPGA being sended over to Yi road carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of oppositely applying for He Yi road reverse traffic channel in a road.
5. maritime satellite communications receiving system as claimed in claim 1, is characterized in that,
Described host computer is PC;
Described host computer is connected by RJ45 network interface with multiple satellite receiver respectively.
6. a maritime satellite communications signal acceptance method, is characterized in that, comprises the steps:
Reception and the dissection process of the satellite communication signal of the first global beam channel He Yi road, satellite receiver Dui Yi road zone beam channel;
Reception and the dissection process of the satellite communication signal of the second satellite receiver to narrow spot beam channel;
Reception and the dissection process of the satellite communication signal of the 3rd satellite receiver to reverse application and Traffic Channel.
7. maritime satellite communications signal acceptance method as claimed in claim 6, is characterized in that,
Reception and the dissection process of the satellite communication signal of described the first global beam channel He Yi road, satellite receiver Dui Yi road zone beam channel, specifically comprise the steps:
Described down-converted module in described the first fpga chip is carried out mixing operation to the intermediate-freuqncy signal of the satellite communication signal in global beam channel and zone beam channel and is moved to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Described filtering processing module in described the first fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described frequency deviation measurement module in described the first fpga chip is carried out preliminary surveying to satellite communication signal frequency deviation, and feeds back to described down-converted module and carry out frequency deviation convergence;
Described synchronization character matching module in described the first fpga chip carries out synchronization character matching operation to satellite communication signal, and sends to skew compensating module;
Described skew compensating module in described the first fpga chip carries out skew compensating operation to satellite communication signal, and satellite communication signal after treatment skew is sent to described the first dsp chip;
Satellite communication signal in global beam channel and zone beam channel that described two the first dsp chips also send over FPGA carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of global beam channel and zone beam channel.
8. maritime satellite communications signal acceptance method as claimed in claim 7, is characterized in that,
Reception and the dissection process of the satellite communication signal of described the second satellite receiver to narrow spot beam channel, specifically comprise the steps:
Described down-converted module in described the second fpga chip is carried out mixing operation to the intermediate-freuqncy signal of the satellite communication signal in narrow some channel and is moved to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Filtering processing module described in described the second fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described in described the second fpga chip, frequency deviation measurement module is carried out preliminary surveying to satellite communication signal frequency deviation, and feeds back to described down-converted module and carry out frequency deviation convergence;
Described in described the second fpga chip, synchronization character matching module carries out synchronization character matching operation to satellite communication signal, and sends to skew compensating module;
Described in described the second fpga chip, skew compensating module carries out skew compensating operation to satellite communication signal, and satellite communication signal after treatment skew is sent to described the second dsp chip;
Satellite communication signal in the narrow some channel that described two the second dsp chips also send over FPGA jointly carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby completes the information reverting operation of the satellite communication signal of narrow some channel.
9. maritime satellite communications signal acceptance method as claimed in claim 8, is characterized in that,
Reception and the dissection process of the satellite communication signal of described the 3rd satellite receiver to reverse application and Traffic Channel, specifically comprise the steps:
Down-converted module Dui Yi road described in described the 3rd fpga chip oppositely applies for that the intermediate-freuqncy signal of the satellite communication signal in the reverse traffic channel of He Yi road carries out mixing operation and move to baseband signal, and the satellite communication signal after Frequency mixing processing is sent to described filtering processing module;
Filtering processing module described in described the 3rd fpga chip is carried out filtering extraction to satellite communication signal and is processed operation, and satellite communication signal after treatment filtering is sent to frequency deviation measurement module;
Described in described the 3rd fpga chip, signalling channel judge module carries out respectively parallel processing to two paths of signals, determines in real time signal source, and signal is delivered in synchronization character matching module;
Described in described the 3rd fpga chip, synchronization character matching module carries out synchronization character matching operation to satellite communication signal, and sends to FIFO processing module;
FIFO processing module described in described the 3rd fpga chip is entered together same dequeue according to the satellite communication signal creation after receiving; According to reducing the signal of communication of each Frame with entering same dequeue, and send to the 3rd dsp chip;
Described two the 3rd dsp chips also send over Yi road to FPGA and oppositely apply for that the satellite communication signal in the reverse traffic channel of He Yi road carries out demodulation, deinterleaving, Turbo decoding, descrambling, CRC check and information analysis processing, thereby complete the information reverting operation of the satellite communication signal of oppositely applying for He Yi road reverse traffic channel in a road.
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