CN104535918B - A kind of cross clock domain lock unit internal constant test circuit and method - Google Patents
A kind of cross clock domain lock unit internal constant test circuit and method Download PDFInfo
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- CN104535918B CN104535918B CN201410811176.5A CN201410811176A CN104535918B CN 104535918 B CN104535918 B CN 104535918B CN 201410811176 A CN201410811176 A CN 201410811176A CN 104535918 B CN104535918 B CN 104535918B
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Abstract
A kind of cross clock domain lock unit internal constant test circuit and method.Test circuit includes：Asynchronous data unit, unit to be detected, the first metastable state counting unit, the second metastable state counting unit, mode selecting unit and timing unit.The invention discloses a kind of test circuit of the lock unit internal constant for carrying out using when cross clock domain lock unit MTBF is assessed and method.Which includes the content that the design of lock unit internal constant test circuit is realized, test operation and data are calculated.The present invention solves the problems, such as that carrying out lock unit internal constant when cross clock domain lock unit MTBF is assessed is difficult to accurately acquisition, can be applicable in the lock unit that the depositors different by master-slave latch technological parameter are constituted, improve the reliability of lock unit internal constant test result.
Description
Technical field
The invention belongs to electronic technology field, more particularly to a kind of cross clock domain lock unit internal constant test circuit and
Method.
Background technology
With the increase and the appearance of SOC(system on a chip) (SOC, System On Chip) of electronic hardware design scale, scene can
Programming gate array (FPGA, Field Programmable Gate Array) and special IC (ASIC, Application
Specific Integrated Circuit) design in cross clock domain signal circuit also accordingly increase, so as to cause in circuit by
The metastable probability that cross clock domain causes also increases.Therefore by two depositor cascades or the cascade structure of more stages depositor
Into synchronous circuit be widely used, as shown in figure 1, the circuit is called lock unit herein.And FPGA, ASIC technique is continuous
Progress is solved to adversely affect to metastable, is greatly degrading the performance of existing lock unit.Cross clock domain in same design
The reliability decrease for increasing the reduction for solving metastable state efficiency with device used, making FPGA circuitry entirety of signal, increased
The risk of design failure.Therefore, can the lock unit used in assessment FPGA meet the reliability requirement of design and seem particularly heavy
Will.
Formula is mainly utilized at presentSynchronize device reliability assessment (wherein FdFor being input into lock unit
Data transition frequency, FcFor the clock frequency of receiving clock-domain, clock cycle of the T for receiving clock-domain, i+1 are in lock unit
The number of depositor, C1、C2For lock unit internal constant：C1For window constant, C2For time constant).Two-stage depositor is constituted
Lock unit is then usedIt is estimated (wherein
C2MFor the time constant of the main latch of depositor in lock unit, C2SThe time from latch for depositor in lock unit is normal
Number, dutycycles of the λ for purpose clock zone clock).Knowable in above-mentioned formula, in order to carry out the mean free error time to lock unit
(MTBF) assess, except knowable F from concrete applicationd, Fc, outside tetra- external action parameters of T, λ, it is necessary to measure C1、C2
Two with the related internal constant of device.Internal constant C can be obtained using test circuit as shown in Figure 2 at present1, C2, wherein
CLK1 is the clock signal of the first clock zone, and CLK2 is the clock signal in second clock domain, and depositor to be tested is to be measured
Depositor B；The output of depositor B to be measured is by depositor C and depositor D respectively after the CLK2 complete periods and half period post-sampling.
When two depositor sampled values are different, metastable state is just detected.As unit B to be tested is half CLK2 clock cycle
Sampled by depositor D afterwards, between the high period of clock, depositor B to be measured only main latch carries out metastable recovery work
Make, therefore the circuit is only capable of time constant C of the main latch for measuring depositor2M, the depositor complete time can not be measured
Constant C2.According to formulaAs the C in depositor2MAnd C2sWhen equal, time constant C2Value
Can be with the C for measuring2MValue substitute.If the main latch of the depositor with from latch technological parameter different when, use C2M's
Value substitutes C2Can then cause lock unit internal constant test result inaccurate, so as to the accuracy for affecting lock unit MTBF to assess.
Content of the invention
In order to solve the above problems, it is an object of the invention to provide a kind of cross clock domain lock unit internal constant test electricity
Road and method.
In order to achieve the above object, the present invention is provided cross clock domain lock unit internal constant test circuit and method bag
Include：Asynchronous data unit, unit to be detected, the first metastable state counting unit, the second metastable state counting unit, mode selecting unit
And timing unit；Wherein：Asynchronous data unit is connected with unit to be detected, and unit to be detected counts single respectively with the first metastable state
Unit is connected with the second metastable state counting unit, and the first metastable state counting unit is connected with mode selecting unit, the second metastable state
Counting unit is connected with mode selecting unit, and mode selecting unit is connected with timing unit；Asynchronous data unit and when first
Clock input signal CLK1 is connected；Mode selecting unit respectively with mode select signal SEL and second clock input signal
CLK2_M1 and the 3rd clock input signal CLK2_M2 are connected.
The first described clock input signal CLK1 and second clock input signal CLK2_M1 be two not homologous asynchronous
Clock, the first clock input signal CLK1 and the 3rd clock input signal CLK2_M2 are also two not homologous asynchronous clocks, the
Exist when two clock input signal CLK2_M1 and the 3rd clock input signal CLK2_M2 are different；Second clock input signal
CLK2_M1 is the slower clock of frequency；3rd clock input signal CLK2_M2 is the very fast clock of frequency, arranges the input of the 3rd clock
Half of the signal CLK2_M2 clock cycle for second clock input signal CLK2_M1.
Described asynchronous data unit 1 includes that the first depositor and the first phase inverter, the output port of the first depositor lead to
Cross the input port that the first phase inverter returns to the first depositor.
Described mode selecting unit mainly includes the first MUX and the second MUX.
The first described metastable state counting unit includes the second depositor and the 3rd depositor, the first configurable Phase delay
Module, the first XOR gate, the 6th depositor and the first metastable state enumerator.
The second described metastable state counting unit includes the 4th depositor, the 5th depositor, the second configurable Phase delay
Module, the second XOR gate, the 7th depositor and the second metastable state enumerator.
The cross clock domain lock unit internal constant method of testing that the present invention is provided includes the following steps for executing in order：
Step 1) generate asynchronous signal the S1 stages：When generating first asynchronous with second clock domain by asynchronous data unit
The output signal of the outfan Q of clock domain digital signal, i.e. the first depositor；
Step 2) select first mode the S2 stages：Pattern is selected by the mode select signal SEL of mode selecting unit
One, treating detector unit main latch carries out main latch time constant test, and now the first metastable state counting unit work has
Effect, and second clock domain clock signal is selected for slower second clock input signal CLK2_M1 of clock frequency；
Step 3) configuration first time delay initial value the S3 stages：First set in the first metastable state counting unit can
The initial value of the time delay of configuration phase Postponement module, as carries out metastable state process using unit main latch to be detected
The initial value of solution time t；
Step 4) the first metastable state counting unit counts to expected number of samples N1 the S4 stages：First metastable state counts single
Unit is counted to metastable state, and when the first metastable state enumerator reaches expected number of samples N1, the 3rd enumerator quits work；
Step 5) record current delay times and timing unit in numerical value the S5 stages：Record the 3rd enumerator numerical value and
The delay time value of the corresponding first configurable phase delay module (Y1)；
Step 6) judge whether testing time reaches the S6 stages of expected sampling number N2：Judge main latch time constant
Whether the number of times of test reaches expected sampling number N2 time, i.e. whether present sample reaches expected sampling number N2；If it is determined that
As a result it is "Yes", then enters the next step S8 stage, otherwise next step enters the S7 stages；
Step 7) configuration the first time delay new value the S7 stages：Reset first in the first metastable state counting unit
The delay time value of configurable phase delay module, next step reenter the S4 stages, continue subsequent cycle test；
Step 8) process test data, obtain time constant C of main latch2MThe S8 stages：At test data
Reason, by record expected N2 timing unit of sampling number value and corresponding first can configure phase delay module delay when
Between, treating the depositor to be measured in test cell carries out time constant C of main latch2MSurvey calculation；
Step 9) select pattern two the S9 stages：Pattern two is selected by the mode select signal SEL of mode selecting unit,
Carry out unit to be detected to test from latch time constant and lock unit window constant, now the second metastable state counting unit work
Effectively, and second clock domain clock signal is selected for clock frequency the 3rd clock input signal CLK2_M2 faster；
Step 10) configuration second time delay initial value the S10 stages：Set second in the second metastable state counting unit
The initial value of the time delay of configurable phase delay module, as carries out metastable state process using unit to be detected from latch
Solution time t initial value；
Step 11) the second metastable state counting unit counts to expected number of samples N1 the S11 stages：Second metastable state is counted
Unit is counted to metastable state, when the second metastable state enumerator reaches expected number of samples N1, stops the 3rd enumerator
Work；
Step 12) record current delay times and timing unit in numerical value the S12 stages：Record the numerical value of the 3rd enumerator
And corresponding second configurable phase delay module delay time value；
Step 13) judge whether testing time reaches the S13 stages of expected sampling number N2：Judge normal from the latch time
Whether the number of times of number test reach expected sampling number N2 time, if it is judged that be "Yes", then entrance next step S15 stage,
Otherwise next step enters the S14 stages；
Step 14) configuration the second time delay new value the S14 stages：Reset in the second metastable state counting unit
The delay time value of two configurable phase delay modules, next step reenter the S11 stages, continue subsequent cycle test；
Step 15) process test data, obtain lock unit internal constant C1, C2The S15 stages：At test data
Reason, by record expected N2 timing unit of sampling number value and corresponding second can configure phase delay module delay when
Between to lock unit in depositor to be measured carry out internal constant C2And C1Survey calculation；This flow process so far terminates.
In the S8 stages, time constant C of described main latch2MComputational methods as follows：According to formulaWherein t is that main latch solves the configurable phase delay module Y1 of time, i.e., first
Above-mentioned formula both sides are taken natural logrithm, are then obtained by value simultaneouslyNow
MTBF can be multiplied by the second clock input signal CLK2_M1 clock cycle by the value of the 3rd enumerator and count divided by the first metastable state
The expected number of samples N1 value of device is calculated；With the first configurable phase delay module time delay t as transverse axis, ln
(MTBF) be the longitudinal axis, N2 point is determined on coordinate axess；With N2 sampling point-rendering straight line, the inverse of the slope k 1 for obtaining is i.e.
For C2M.
In the S15 stages, described lock unit internal constant C1、C2Computational methods as follows：According toWherein t is to solve the configurable Phase delay mould of time, i.e., second from latch
The value of block, λ T are the 3rd clock input signal CLK2_M2 high level times of purpose clock zone clock, to above-mentioned formula both sides simultaneously
Natural logrithm is taken, is then obtainedWherein C2MCan be by
Step 8) calculate, thereforelnFd, lnFcFor known；MTBF now can be multiplied by by the value of the 3rd enumerator
Three clock input signal CLK2_M2 clock cycle were calculated divided by the expected number of samples N1 value of the second metastable state enumerator；
With the second configurable phase delay module t time delay as transverse axis, ln (MTBF) is the longitudinal axis, determines N2 point, is adopted with N2
Sampling point draws straight line, and the k2 reciprocal of the slope for obtaining is time constant C from latch2S；And can obtain drawing straight line and y
Intersection value Yc of axle, then window constant C1Can be byCalculate, the time is normal
Number C2Can be byCalculate.
The invention discloses a kind of survey of the lock unit internal constant for carrying out using when cross clock domain lock unit MTBF is assessed
Examination circuit and method.In which includes that the design realization to lock unit internal constant test circuit, test operation and data are calculated
Hold.The present invention solves the problems, such as that carrying out lock unit internal constant when cross clock domain lock unit MTBF is assessed is difficult to accurately acquisition,
Can be applicable in the lock unit that the depositors different by master-slave latch technological parameter are constituted, improve the survey of lock unit internal constant
The accuracy of test result and the scope of application.
Description of the drawings
Fig. 1 is the cross clock domain synchronizer circuit schematic diagram in prior art.
Fig. 2 is the cross clock domain lock unit internal constant test circuit schematic diagram in prior art.
The cross clock domain lock unit internal constant test circuit composition frame chart that Fig. 3 is provided for the present invention.
The cross clock domain lock unit internal constant test circuit schematic diagram that Fig. 4 is provided for the present invention.
The cross clock domain lock unit internal constant method of testing flow chart that Fig. 5 is provided for the present invention.
Specific embodiment
The cross clock domain lock unit internal constant test circuit for the present invention being provided with specific embodiment below in conjunction with the accompanying drawings
It is described in detail with method.
As shown in figure 3, the cross clock domain lock unit internal constant test circuit that the present invention is provided includes：Asynchronous data unit
1st, unit to be detected 2, the first metastable state counting unit 3, the second metastable state counting unit 4, mode selecting unit 5 and timing unit
6；Wherein：Asynchronous data unit 1 is connected with unit to be detected 2, unit to be detected 2 respectively with the first metastable state counting unit 3 and
Second metastable state counting unit 4 is connected, and the first metastable state counting unit 3 is connected with mode selecting unit 5, the second metastable state meter
Counting unit 4 is connected with mode selecting unit 5, and mode selecting unit 5 is connected with timing unit 6；Asynchronous data unit 1 and first
Clock input signal CLK1 is connected；Mode selecting unit 5 respectively with mode select signal SEL and second clock input signal
CLK2_M1 and the 3rd clock input signal CLK2_M2 are connected.
Asynchronous data unit 1 belongs to the first clock zone；Mode selecting unit 5 is combination logic, it is not necessary to which clock drives；Treat
Detector unit 2, the first metastable state counting unit 3, the second metastable state counting unit 4 and timing unit 6 belong to second clock domain；Mould
Formula select unit 5 for second clock domain Unit selection clock apparatus, and select the first metastable state counting unit 3 output or
The output of the second metastable state counting unit 4 is connected with timing unit 6.
As shown in figure 4, the first clock input signal CLK1 and second clock input signal CLK2_M1 be two not homologous
Asynchronous clock, the first clock input signal CLK1 and the 3rd clock input signal CLK2_M2 also for two not homologous asynchronous when
Exist when clock, second clock input signal CLK2_M1 and the 3rd clock input signal CLK2_M2 are different；In the test master of pattern one
In the case of latch, second clock input signal CLK2_M1 for selecting clock frequency slower is used as input clock；Sub- for improving
Stable state produces frequency, in the case where pattern two is tested from latch, selects clock frequency the 3rd clock input signal faster
CLK2_M2 can arrange for the 3rd clock input signal CLK2_M2 clock cycle for second clock input signal as input clock
The half of CLK2_M1.
Described asynchronous data unit 1 includes the first depositor A1 and the first phase inverter M1, the output of the first depositor A1
Port returns to the input port of the first depositor A1 by the first phase inverter M1；For generating the data letter of the first clock zone
Number, i.e. the output signal of the outfan Q of the first depositor A1.
Described mode selecting unit 5 mainly includes the first MUX X1 and the second MUX X2, for root
Main latch test pattern is determined and from the selection between latch test pattern according to mode select signal SEL；First multi-path choice
Device X1 selects second clock input signal CLK2_M1 or the 3rd clock input signal CLK2_M2 as the input in second clock domain
Clock CLK2；Second MUX X2 selects the first metastable state enumerator J1 or the second metastable state enumerator J2 to reach in advance
The enable signal that output signal during phase number of samples N1 stops counting as the 3rd enumerator J3.
Described unit to be detected 2 is depositor B to be measured.
The first described metastable state counting unit 3 includes the second depositor A2 and the 3rd depositor A3, the first configurable phase
Position Postponement module Y1, the first XOR gate M3, the 6th depositor A6 and the first metastable state enumerator J1；The unit works in pattern one
Effectively, to carrying out the Asia after recovering for the first configurable phase delay module Y1 time delays using depositor B main latch to be measured
Stable state number is counted；The output signal of unit to be detected 2 is in the inversion clock of the former clock in second clock domain and when second
The former clock delay first in clock domain can configure the rising edge of phase delay module Y1 clocks respectively by the 3rd depositor A3 and the
Two depositor A2 are sampled, and output result after the first XOR gate M3 XORs, are input to by second clock domain
After former clock delay first can configure the 6th depositor A6 of rising edge triggering of phase delay module Y1 clocks, metastable by first
State enumerator J1 carries out metastable state counting.
The second described metastable state counting unit 4 includes the 4th depositor A4, the 5th depositor A5, the second configurable phase place
Postponement module Y2, the second XOR gate M4, the 7th depositor A7 and the second metastable state enumerator J2；The unit has in the work of pattern two
Effect, to carrying out half the 3rd clock input signal CLK2_M2 clock cycle using depositor B main latch to be measured, to solve the time extensive
Multiple and its carry out second from latch and can configure metastable state number after phase delay module Y2 recovers time delay being counted；Treat
Reverse clock delay second of the output signal of detector unit 2 in the former clock of the former clock and second clock domain in second clock domain
The rising edge of configurable phase delay module Y2 clocks is sampled by the 5th depositor A5 and the 4th depositor A4 respectively,
Output result after XOR is input to and can configure phase place by the reverse clock delay second of the former clock in second clock domain
After 7th depositor A7 of Postponement module Y2 rising edge clocks triggering, metastable state counting is carried out by the second metastable state enumerator J2.
Timing unit 6 includes the 3rd enumerator J3, and which is respectively to sampling expected hits under pattern one and pattern two
Time needed for N1 metastable state of mesh carries out timing；Clock cycle during test job every a second clock domain is counted to the 3rd
Number device J3 is carried out plus an operation, is adopted when the value of the metastable state enumerator in the metastable state counting unit under associative mode reaches expection
During sample number N 1, generation stopping count enable signal make the 3rd enumerator J3 stop count, and retain initial value constant until
Carry out next test.
In the first described metastable state counting unit 3, metastable states of the first metastable state enumerator J1 to pattern once produces number
Counted, when metastable state reaches expected number of samples N1, the first metastable state enumerator J1 quits work, the stopping meter of generation
Several enable signals makes the 3rd enumerator J3 quit work by mode selecting unit 5.
In the second described metastable state counting unit 4, the second metastable state enumerator J2 produces number to the metastable state under pattern two
Counted, when metastable state reaches expected number of samples N1, the second metastable state enumerator J2 quits work, the stopping meter of generation
Several enable signals makes the 3rd enumerator J3 quit work by mode selecting unit 5.
As shown in figure 5, the above-mentioned cross clock domain lock unit internal constant test circuit of utilization that the present invention is provided carry out across when
The method of clock domain lock unit internal constant test includes the following steps for executing in order：
Step 1) generate asynchronous signal the S1 stages：First asynchronous with second clock domain is generated by asynchronous data unit 1
Clock zone digital signal, the i.e. output signal of the outfan Q of the first depositor A1；
Step 2) select first mode the S2 stages：Pattern is selected by the mode select signal SEL of mode selecting unit 5
One, treating 2 main latch of detector unit carries out main latch time constant test, and now the first metastable state counting unit 3 works
Effectively, and second clock domain clock signal is selected for slower second clock input signal CLK2_M1 of clock frequency；
Step 3) configuration first time delay initial value the S3 stages：Set first in the first metastable state counting unit 3
The initial value of the time delay of configurable phase delay module Y1, as carries out metastable state using 2 main latch of unit to be detected
The initial value of the solution time t of process；
Step 4) the first metastable state counting unit counts to expected number of samples N1 the S4 stages：First metastable state counts single
First 3 pairs of metastable states are counted, and when the first metastable state enumerator J1 reaches expected number of samples N1, the 3rd enumerator J3 stops
Work；
Step 5) record current delay times and timing unit in numerical value the S5 stages：Record the numerical value of the 3rd enumerator J3
And corresponding first configurable phase delay module Y1 delay time value；
Step 6) judge whether testing time reaches the S6 stages of expected sampling number N2：Judge main latch time constant
Whether the number of times of test reaches expected sampling number N2 time, i.e. whether present sample reaches expected sampling number N2；If it is determined that
As a result it is "Yes", then enters the next step S8 stage, otherwise next step enters the S7 stages；
Step 7) configuration the first time delay new value the S7 stages：Reset in the first metastable state counting unit 3
The delay time value of one configurable phase delay module Y1, next step reenter the S4 stages, continue subsequent cycle test；
Step 8) process test data, obtain time constant C of main latch2MThe S8 stages：At test data
Reason, is prolonged by the value and corresponding first configurable phase delay module Y1 of the N2 timing unit of expected sampling number 6 for recording
Late the time, treating the depositor B to be measured in test cell 2 carries out time constant C of main latch2MSurvey calculation；
Step 9) select pattern two the S9 stages：Pattern is selected by the mode select signal SEL of mode selecting unit 5
Two, carry out unit to be detected 2 and test from latch time constant and lock unit window constant, now the second metastable state counting unit
4 work effectively, and select second clock domain clock signal for clock frequency the 3rd clock input signal CLK2_M2 faster；
Step 10) configuration second time delay initial value the S10 stages：Set in the second metastable state counting unit 4
The initial value of the time delay of two configurable phase delay module Y2, is as carried out from latch using unit to be detected 2 metastable
The initial value of the solution time t of state process；
Step 11) the second metastable state counting unit counts to expected number of samples N1 the S11 stages：Second metastable state is counted
Unit 4 is counted to metastable state, when the second metastable state enumerator J2 reaches expected number of samples N1, makes the 3rd enumerator J3
Quit work；
Step 12) record current delay times and timing unit in numerical value the S12 stages：Record the number of the 3rd enumerator J3
Value and the delay time value of corresponding second configurable phase delay module Y2；
Step 13) judge whether testing time reaches the S13 stages of expected sampling number N2：Judge normal from the latch time
Whether the number of times of number test reach expected sampling number N2 time, if it is judged that be "Yes", then entrance next step S15 stage,
Otherwise next step enters the S14 stages；
Step 14) configuration the second time delay new value the S14 stages：Reset in the second metastable state counting unit 4
The delay time value of the second configurable phase delay module Y2, next step reenter the S11 stages, continue subsequent cycle test；
Step 15) process test data, obtain lock unit internal constant C1, C2The S15 stages：At test data
Reason, is prolonged by the value and corresponding second configurable phase delay module Y2 of the N2 timing unit of expected sampling number 6 for recording
Late the time to lock unit in depositor B to be measured carry out internal constant C2And C1Survey calculation；This flow process so far terminates.
In S7 stages and S14 stages, the described concrete grammar for resetting delay time value is by gradually incremental
Principle, its final delay time should not exceed the half period of second clock domain clock.
In the first described metastable state counting unit 3, the first configurable phase delay module Y1 is used for second clock domain
Clock signal carries out the realization of configurable different delays, and second in the second metastable state counting unit 4 can configure Phase delay
Module Y2 is used for the clock signal reverse to second clock domain phase place carries out the realization of configurable different delays；Actual test
In, using the method for loop test；In testing every time, time delay is gradually incremented by, but the final delay time should not exceed
The half period of second clock domain clock.
In the S8 stages, time constant C of described main latch2MComputational methods as follows：According to formula(t is the value that main latch solves the configurable phase delay module Y1 of time, i.e., first),
Natural logrithm is taken simultaneously to above-mentioned formula both sides, is then obtainedMTBF now
The second clock input signal CLK2_M1 clock cycle can be multiplied by divided by the first metastable state enumerator by the value of the 3rd enumerator J3
The expected number of samples N1 value of J1 is calculated；With the first configurable phase delay module Y1 time delay t as transverse axis, ln
(MTBF) be the longitudinal axis, N2 point is determined on coordinate axess；With N2 sampling point-rendering straight line, the inverse of the slope k 1 for obtaining is i.e.
For C2M.
In the S15 stages, described lock unit internal constant C1、C2Computational methods as follows：According to(t is to solve the configurable phase delay module Y2 of time, i.e., second from latch
Value, λ T be the 3rd clock input signal CLK2_M2 high level times of purpose clock zone clock), to above-mentioned formula both sides simultaneously
Natural logrithm is taken, is then obtainedWherein C2MCan be by
Step 8) calculate, thereforelnFd, lnFcFor known；MTBF now can be multiplied by by the value of the 3rd enumerator J3
3rd clock input signal CLK2_M2 clock cycle was calculated divided by the expected number of samples N1 value of the second metastable state enumerator J2
Go out；With the second configurable phase delay module Y2 t time delay as transverse axis, ln (MTBF) is the longitudinal axis, determines N2 point, with N2
Individual sampling point-rendering straight line, the k2 reciprocal of the slope for obtaining are time constant C from latch2S；And can obtain drawing directly
Intersection value Yc of line and y-axis, then window constant C1Can be byCalculate, when
Between constant C2Can be byCalculate；
For ensureing the accurate and effective of test data, can be tested in the diverse location of same device, be taken different tests
The lock unit internal constant C of position1、C2Meansigma methodss carry out MTBF calculating.
The cross clock domain lock unit internal constant test circuit and method that the present invention is provided solves depositor in lock unit
Main latch with from latch technological parameter different when carry out lock unit internal constant needed for MTBF is calculated and be difficult to comprehensively accurately
The problem of measurement；A kind of general lock unit internal constant test circuit and method of testing is provided, can be to normal inside lock unit
Number carries out accurate survey calculation.
Claims (9)
1. a kind of cross clock domain lock unit internal constant test circuit, it is characterised in that：Which includes：Asynchronous data unit (1), treat
Detector unit (2), the first metastable state counting unit (3), the second metastable state counting unit (4), mode selecting unit (5) and timing
Unit (6)；Wherein：Asynchronous data unit (1) is connected with unit to be detected (2), unit (2) to be detected respectively with the first metastable state
Counting unit (3) is connected with the second metastable state counting unit (4), the first metastable state counting unit (3) and mode selecting unit
(5) connect, the second metastable state counting unit (4) is connected with mode selecting unit (5), mode selecting unit (5) and timing unit
(6) it is connected；Asynchronous data unit (1) is connected with the first clock input signal CLK1；Mode selecting unit (5) respectively with mould
Formula selection signal SEL and second clock input signal CLK2_M1 and the 3rd clock input signal CLK2_M2 are connected.
2. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described first
Clock input signal CLK1 and second clock input signal CLK2_M1 are two not homologous asynchronous clocks, and the first clock is input into
Signal CLK1 and the 3rd clock input signal CLK2_M2 are also two not homologous asynchronous clocks, second clock input signal
Exist when CLK2_M1 and the 3rd clock input signal CLK2_M2 is different；Second clock input signal CLK2_M1 is that frequency is slower
Clock；3rd clock input signal CLK2_M2 is the very fast clock of frequency, arranges the 3rd clock input signal CLK2_M2 clocks week
Half of the phase for second clock input signal CLK2_M1.
3. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described is asynchronous
Data cell (1) includes the first depositor (A1) and the first phase inverter (M1), and the output port of the first depositor (A1) passes through the
One phase inverter (M1) returns to the input port of the first depositor (A1).
4. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described pattern
Select unit (5) mainly includes the first MUX (X1) and the second MUX (X2).
5. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described first
Metastable state counting unit (3) includes the second depositor (A2) and the 3rd depositor (A3), the first configurable phase delay module
(Y1), the first XOR gate (M3), the 6th depositor (A6) and the first metastable state enumerator (J1).
6. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described second
Metastable state counting unit (4) includes the 4th depositor (A4), the 5th depositor (A5), the second configurable phase delay module
(Y2), the second XOR gate (M4), the 7th depositor (A7) and the second metastable state enumerator (J2).
7. the cross clock domain synchronization that the cross clock domain lock unit internal constant test circuit described in a kind of utilization claim 1 is carried out
Device internal constant method of testing, it is characterised in that：Described method includes the following steps for executing in order：
Step 1) generate asynchronous signal the S1 stages：When generating first asynchronous with second clock domain by asynchronous data unit (1)
Clock domain digital signal, the i.e. output signal of the outfan Q of the first depositor (A1)；
Step 2) select first mode the S2 stages：Pattern is selected by the mode select signal SEL of mode selecting unit (5)
One, treating detector unit (2) main latch carries out main latch time constant test, now the first metastable state counting unit (3)
Work effectively, and selects second clock domain clock signal for slower second clock input signal CLK2_M1 of clock frequency；
Step 3) configuration first time delay initial value the S3 stages：First set in the first metastable state counting unit (3) can
The initial value of the time delay of configuration phase Postponement module (Y1), is as carried out using unit to be detected (2) main latch metastable
The initial value of the solution time t of state process；
Step 4) the first metastable state counting unit counts to expected number of samples N1 the S4 stages：First metastable state counting unit
(3) metastable state is counted, when the first metastable state enumerator J1 reaches expected number of samples N1, the 3rd enumerator (J3) stops
Only work；
Step 5) record current delay times and timing unit in numerical value the S5 stages：Record the 3rd enumerator (J3) numerical value and
The delay time value of the corresponding first configurable phase delay module (Y1)；
Step 6) judge whether testing time reaches the S6 stages of expected sampling number N2：Judge that main latch time constant is tested
Number of times whether reach expected sampling number N2 time, i.e. whether present sample reaches expected sampling number N2；If it is judged that
For "Yes", then the next step S8 stage is entered, otherwise next step enters the S7 stages；
Step 7) configuration the first time delay new value the S7 stages：Reset first in the first metastable state counting unit (3)
The delay time value of configurable phase delay module (Y1), next step reenter the S4 stages, continue subsequent cycle test；
Step 8) process test data, obtain time constant C of main latch2MThe S8 stages：Test data is processed, is led to
The value of N2 timing unit of the expected sampling number (6) of overwriting and corresponding first configurable phase delay module (Y1) postpone
Time, treating the depositor to be measured (B) in test cell (2) carries out time constant C of main latch2MSurvey calculation；
Step 9) select pattern two the S9 stages：Pattern two is selected by the mode select signal SEL of mode selecting unit (5),
Carry out unit to be detected (2) to test from latch time constant and lock unit window constant, now the second metastable state counting unit
(4) work effectively, and second clock domain clock signal is selected for clock frequency the 3rd clock input signal CLK2_ faster
M2；
Step 10) configuration second time delay initial value the S10 stages：Set second in the second metastable state counting unit (4)
The initial value of the time delay of configurable phase delay module (Y2), as carries out Asia using unit to be detected (2) from latch
The initial value of the solution time t of steady state process；
Step 11) the second metastable state counting unit counts to expected number of samples N1 the S11 stages：Second metastable state counting unit
(4) metastable state is counted, when the second metastable state enumerator (J2) reaches expected number of samples N1, makes the 3rd enumerator
(J3) quit work；
Step 12) record current delay times and timing unit in numerical value the S12 stages：Record the numerical value of the 3rd enumerator (J3)
And corresponding second configurable phase delay module (Y2) delay time value；
Step 13) judge whether testing time reaches the S13 stages of expected sampling number N2：Judge to survey from latch time constant
Whether the number of times of examination reaches expected sampling number N2 time, if it is judged that being "Yes", then enters the next step S15 stage, otherwise
Next step enters the S14 stages；
Step 14) configuration the second time delay new value the S14 stages：Reset in the second metastable state counting unit (4)
The delay time value of two configurable phase delay modules (Y2), next step reenter the S11 stages, continue subsequent cycle test；
Step 15) process test data, obtain lock unit internal constant C1, C2The S15 stages：Test data is processed, is led to
The value of N2 timing unit of the expected sampling number (6) of overwriting and corresponding second configurable phase delay module (Y2) postpone
Time to lock unit in depositor to be measured (B) carry out internal constant C2And C1Survey calculation；This flow process so far terminates.
8. cross clock domain lock unit internal constant method of testing according to claim 7, it is characterised in that：In the S8 stages
In, time constant C of described main latch2MComputational methods as follows：According to formula
Wherein t is the value that main latch solves the configurable phase delay module Y1 of time, i.e., first, and above-mentioned formula both sides are taken from simultaneously
So logarithm, then be obtainedMTBF now can pass through the 3rd enumerator (J3)
Value is multiplied by expected number of samples N1 value of the second clock input signal CLK2_M1 clock cycle divided by the first metastable state enumerator J1
Calculate；With the first configurable phase delay module (Y1) time delay t as transverse axis, ln (MTBF) is the longitudinal axis, in coordinate
N2 point is determined on axle；With N2 sampling point-rendering straight line, the inverse of the slope k 1 for obtaining is C2M.
9. cross clock domain lock unit internal constant method of testing according to claim 7, it is characterised in that：In the S15 stages
In, described lock unit internal constant C1, C2Computational methods as follows：According to
Wherein t is to solve the value that time, i.e., second can configure phase delay module (Y2), λ from latchTFor purpose clock zone clock
Above-mentioned formula both sides are taken natural logrithm, are then obtained by three clock input signal CLK2_M2 high level times simultaneouslyWherein C2MCan be by step 8) calculate, thereforelnFd, lnFcFor known；MTBF now can be multiplied by the 3rd clock input signal by the value of the 3rd enumerator (J3)
The CLK2_M2 clock cycle is calculated divided by the expected number of samples N1 value of the second metastable state enumerator (J2)；Can match somebody with somebody with second
Phase delay module (Y2) t time delay is put for transverse axis, ln (MTBF) is the longitudinal axis, determines N2 point, paints with N2 sampled point
Straight line processed, the k2 reciprocal of the slope for obtaining are time constant C from latch2S；And the friendship that can obtain drawing straight line and y-axis
Point value Yc, then window constant C1Can be byCalculate, time constant C2Can
ByCalculate.
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| CN108958701A (en) * | 2017-05-22 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of data transfer control method, device and storage medium |
| CN110311659B (en) * | 2018-03-27 | 2021-02-12 | 华为技术有限公司 | Trigger and integrated circuit |
| CN112840571B (en) * | 2018-12-29 | 2024-04-23 | 华为技术有限公司 | Cross-clock domain processing circuit |
| CN111262562B (en) * | 2020-03-02 | 2021-08-27 | 上海交通大学 | Metastable state detection circuit |
| CN112036103B (en) * | 2020-09-01 | 2024-03-08 | 深圳市傲立电子有限公司 | Device and method for processing multi-bit data from fast clock domain to slow clock domain |
| CN112416054B (en) * | 2020-10-30 | 2022-11-08 | 山东浪潮科学研究院有限公司 | Method for testing cross-clock-domain signal synchronization of FPGA design |
| CN112953475B (en) * | 2021-02-04 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Multi-bit data clock domain crossing synchronization circuit |
| CN115225043A (en) * | 2022-07-27 | 2022-10-21 | 中国民航大学 | Electromagnetic protection circuit for low-noise amplifier of Beidou receiver |
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