CN103675383B - A kind of circuit measuring waveform - Google Patents
A kind of circuit measuring waveform Download PDFInfo
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- CN103675383B CN103675383B CN201310630327.2A CN201310630327A CN103675383B CN 103675383 B CN103675383 B CN 103675383B CN 201310630327 A CN201310630327 A CN 201310630327A CN 103675383 B CN103675383 B CN 103675383B
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Abstract
The present invention relates to SIC (semiconductor integrated circuit) field, particularly relate to a kind of circuit measuring waveform, delay clock signals is exported after clock signal to be measured being postponed by delay array successively, and utilize marginal detector unit and rising edge detecting unit to detect the rising edge of the delay clock signals of coupling, and the rising edge number that the above-mentioned rising edge detecting unit of counter records detects, and then draw in the time range preset, the quantitative data of the shake of clock signal to be measured, namely this circuit is by utilizing simple integrated circuit, shake and the signal delay of clock signal can be measured accurately, and simplicity of design cost is low.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) field, particularly relate to a kind of circuit measuring waveform.
Background technology
At present, due to large scale integrated circuit (LargeScaleIntegratedCircuit, be called for short LSI) along with there is a large amount of pulse ripples (temporalfluctuation), and then cause the clock signal in circuit (clocksignal) very easily to produce shake (jitter) phenomenon, and then cause inaccurate (incorrectaction) of circuit operation.In order to improve the accuracy of circuit operation, need the shake that in measurement circuit accurately, clock signal produces, but the method that tradition measures shake (jitter) all quantitatively cannot measure (measurequantitatively) to the shake produced, as:
Direct measurement method (Directmeasurement), it requires configuration I/O(RequireveryfastI/O quickly), and be equipped with the system (highaccuracymeasurementsystem) of high measurement accuracy, the measurement to shake could be realized, but its cost is high, paired pulses shake quantitative measurement can not be carried out.
Digital counter method (Digitalcounter), it requires configuration single-slope (Singleslope) analog-digital converter (AnalogtoDigitalConverter, be called for short ADC), but namely its minimum pulse width (Minimumpulsewidth) measured will be at least a clock period (clockperiod) for 100ps(), and design difficulty is very large.
Lag line measures method (delayline), it requires the one or more lag line of configuration, and require to have, for lag line, there is comparatively rich experience, especially require very high to the wiring technique (layouttechnique) of entirety, and then cause design difficulty and cost all higher.
Above-mentioned various method for measurement all need to use high precision measurement system to carry out calibrating (Requirehighaccuracymeasurementsystemforcalibration), further increase process costs.
Chinese patent (publication number: CN101232333A) describes a kind of clock jitter method for measurement and oscillograph, by clock access to be measured being had the oscillographic test channel of delayed trigger function, and measure the measuring error T0 caused due to oscillographic triggering system, arranging oscillographic triggering mode is delayed mode, according to the chattering frequency scope wanting to measure, adjustment delay time value T1; Finding with shot clock edge CLK1 at a distance of the time interval is the clock edge CLK2 of T1, measures the time interval T2 between the most left and rightest point of CLK2 edge on triggering level position, arranges
as clock jitter value; And then eliminate the measuring error brought due to oscillographic triggering system, reach the object simply and effectively reducing clock jitter measuring error.
Summary of the invention
For above-mentioned Problems existing, present invention is disclosed a kind of circuit measuring waveform, wherein, described circuit comprises:
Signal source of clock to be measured, the delay array including at least three delay cells of series connection, edge detecting unit, rising edge detecting unit sum counter;
Described signal source of clock to be measured provides clock signal to the input end of described delay array;
The selection of described delay array postpones output terminal and is connected with the detection signal input end of described edge detecting unit, and the maximum-delay output terminal of described delay array is connected with the reference signal input of described edge detecting unit;
Described counter is connected with the output terminal of described edge detecting unit by described rising edge detecting unit;
Wherein, the cycle being more than or equal to described clock signal time delay of the maximum-delay clock signal of described maximum-delay output terminal output.
The circuit of above-mentioned measurement waveform, wherein, described delay array also comprises a selector switch;
Described selector switch is connected with the output terminal of each described delay cell respectively, selects and exports the detection signal input end of delay clock signals to described edge detecting unit.
The circuit of above-mentioned measurement waveform, wherein, each described delay cell includes the phase inverter of two series connection, and the end points that the phase inverter of two series connection connects is connected with described selector switch through another phase inverter.
The circuit of above-mentioned measurement waveform, wherein, described selector switch comprises a multiplexer, and this multiplexer is connected with the output terminal of each described delay cell respectively, and the inhibit signal that each described delay cell exports is sent to the detection signal input end of described edge detecting unit successively.
The circuit of above-mentioned measurement waveform, wherein, described multiplexer is according to the suitable detection signal the input end successively inhibit signal of each described delay cell being sent to described edge detecting unit of the size of time delay.
The circuit of above-mentioned measurement waveform, wherein, described edge detecting unit comprises the first d type flip flop and the second d type flip flop;
Describedly select to postpone output terminal and to be held with the D of described first d type flip flop respectively by the phase inverter of series connection and the D of the second d type flip flop holds and is connected;
Described maximum-delay output terminal is held with the CP of described first d type flip flop respectively and the CP of the second d type flip flop holds and is connected.
The circuit of above-mentioned measurement waveform, wherein, described select to postpone output terminal hold with the D of described first d type flip flop between circuit in be provided with two phase inverters of connecting, described selection delay output terminal hold with the D of described second d type flip flop between circuit in be provided with four phase inverters of connecting.
The circuit of above-mentioned measurement waveform, wherein, described rising edge detecting unit comprises a phase inverter and a Sheffer stroke gate;
The output terminal of described first d type flip flop is connected with an input end of described Sheffer stroke gate by described phase inverter, the output terminal of described second d type flip flop is connected with another input end of described Sheffer stroke gate, and the output terminal of this Sheffer stroke gate is connected with the input end of described counter.
The circuit of above-mentioned measurement waveform, wherein, the time delay that each described delay cell produces is all identical.
The circuit of above-mentioned measurement waveform, wherein, described maximum-delay clock signal is the signal that described clock signal exports successively after all described delay cell.
In addition, a kind of circuit measuring waveform of the application, on multiple technology platforms such as Logic, can be applicable to >=technique of the multiple technology node such as 130nm, 90nm, 65/55nm, 45/40nm, 32/28nm or≤22nm in.
In sum, a kind of circuit measuring waveform of the present invention, delay clock signals is exported after clock signal to be measured being postponed by delay array (delaycellarray) successively, and utilize marginal detector unit (edgedetector) and rising edge detecting unit (riseedgefinder) to detect the rising edge of the delay clock signals of coupling, and counter (counter) records the rising edge number that above-mentioned rising edge detecting unit detects, and then draw in the time range preset, the quantitative data of the shake (jitter) of clock signal to be measured, namely this circuit is by utilizing simple integrated circuit, shake and the signal delay (signaldelay) of clock signal can be measured accurately, and simplicity of design cost is low.
Accompanying drawing explanation
Fig. 1 is a kind of circuit structure diagram measuring an embodiment in the circuit of waveform of the present invention;
Fig. 2 is the delay clock signals oscillogram that the delay array in Fig. 1 exports;
Fig. 3 is the histogram of clock signal jitter;
Fig. 4 is the edge detecting unit fundamental diagram in Fig. 1;
Fig. 5 is the rising edge cell operation schematic diagram in Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 1 is a kind of circuit structure diagram measuring an embodiment in the circuit of waveform of the present invention; As shown in Figure 1, a kind of circuit measuring waveform, be applied in the design of SIC (semiconductor integrated circuit), this measurement waveform circuit comprises signal source of clock to be measured (not indicating in figure), postpones array (delaycellarray), edge detecting unit (edgedetectorcircuit), rising edge detecting unit (risingedgefinder) sum counter (counter).
Wherein, delay cell comprises n(n > 2, and n is positive integer) delay cell (delaycell) of individual series connection and selector switch (selector), this selector switch comprises multiplexer (multiplexer is called for short MUX) and controls the controller of this multiplexer MUX addressing.
Further, above-mentioned signal source of clock to be measured provides clock signal clk to postpone the input end of display, this clock signal clk is successively after each delay cell, and the maximum-delay output terminal through this delay cell is sent to the reference signal input of edge detecting unit; Each delay cell is also provided with an inhibit signal output terminal, above-mentioned multiplexer is connected with the inhibit signal output terminal of each delay cell respectively, and utilize controller to carry out addressing to this multiplexer, to select corresponding delay cell to export inhibit signal, and through selecting to postpone the detection signal input end that output terminal is sent to edge detecting unit.
Preferably, above-mentioned controller controls the output signal of each delay cell is sent to edge detecting unit by this multiplexer successively detection signal input end according to the size order of time delay.
Preferably, each delay cell includes the phase inverter of two series connection, and the end points place that two phase inverters of this two series connection connect is connected with above-mentioned multiplexer through another phase inverter, and namely as shown in fig. 1, each delay cell includes three phase inverters.
Preferably, time constant (timeconstant) j of above-mentioned each delay units delay is all identical, the time delay of the delay array that delay cell all is accordingly formed is n*j, and n*j >=m*T(m is positive integer, and T is the cycle of the CLK of above-mentioned clock signal); Wherein, m larger measurement clock jitter is more accurate.
Further, edge detecting unit comprises the first trigger D1, the second trigger D2 and some phase inverters, the selection of above-mentioned delay array postpones after delay clock signals that delay cell that multiplexer selects by output terminal exports is sent to and detects detection signal input end, then holds through the D that phase inverter is sent to the first trigger D1 and the second trigger D2 respectively.
Preferably, the delay clock signals that the delay cell that multiplexer is selected exports is sent to the D end of the first trigger D1 through the phase inverter that two are connected, and this delay clock signals is also sent to the D end of the second trigger D2 through four reversers of series connection simultaneously; As shown in Figure 1, structure as identical in above-mentioned delay cell also can be set, the delay selection input end of array is connected with the input end of two delay cells of series connection, the inhibit signal output terminal of one of them delay cell is held with the D of the first trigger D1 and is connected, the inhibit signal output terminal of another delay cell is held with the D of the second trigger D2 and is connected, and clock signal could arrive the D end of this second trigger D2 through two delay cells.
Further, the maximum-delay output terminal of above-mentioned delay array is held with the CP of the first trigger D1 and the second trigger D2 respectively through reference signal input and is connected.
Further, above-mentioned rising edge detecting unit comprises phase inverter and Sheffer stroke gate, the output terminal of the first trigger D1 is connected with an input end of Sheffer stroke gate through this phase inverter, the output terminal of the second trigger D2 is then directly connected with another input end of this Sheffer stroke gate, and the output terminal of this Sheffer stroke gate is connected with the input end of counter.
Preferably, the trigger that counter is connected by several is formed.
As shown in figures 1-4, signal source of clock to be measured provides clock signal clk, multiple delay clock signals is formed after the delayed array of this clock signal, see the known edge detecting unit of Fig. 4 there is the delay clock signals of maximum delay time for reference signal, successively each delay clock signals is compared, to judge that whether this delay clock signals is consistent with the delay clock signals of maximum delay time, the delay clock signals that rising edge detecting unit then exports according to above-mentioned edge detecting unit finds out rising edge signal (shown in Figure 5), counter then records the number of times of the rising edge appearance that above-mentioned rise detection unit exports.
Concrete, signal source of clock to be measured exports a clock signal in delay cell, this delay cell exports two-way inhibit signal, the signal (namely there is the inhibit signal of maximum delay time n*j) exported after an inhibit signal is through all delay cell, another is then controlled by controller the inhibit signal that output selected by multiplexer, and this two paths of signals is transferred into two input ends (reference signal input and detection signal input end) of edge detecting unit respectively; Because above-mentioned clock signal has clock period T, and its oscillogram is the square wave with high level signal and low level signal shown in Fig. 2 in each cycle, if the waveform of this two-way inhibit signal is all consistent with clock T, then edge detecting unit just can detect this consistent edge, and exports rising edge detecting unit to; Wherein, by changing the address of selector switch successively, namely utilizing controller the inhibit signal in multiplexer to be exported successively, can know that the inhibit signal how much delay cell exports is consistent with clock T.
Further, edge detecting unit is by all delay clock signals phase homomorphism (state with having maximum delay time, namely be all high level or level) delay clock signals export, rising edge detecting unit detects the signal that edge detecting unit exports subsequently, and counter (specifiedperiod) within the time of presetting counts the rising edge information that edge detecting unit detects; If the clock signal that signal source of clock to be measured exports is not shaken (jitter), counter exports the histogram of non-jitter as shown in Figure 3, if and the clock signal that signal source of clock to be measured exports has shake (jitter), then counter exports the histogram having shake as shown in Figure 3, can realize the accurately measuring to clock jitter by the histogram finally exported.
Preferably, the application realizes the circuit of measurement waveform of low cost, the high-precision measurement to clock signal jitter, and same also can be used for the signal that measurement does not have cycle (nocycle).
In addition, as shown in Fig. 1 ~ 2, the two paths of signals postponing array output is have the inhibit signal of maximum delay time and select the inhibit signal of output, wherein, the inhibit signal with maximum delay time is the reference signal input being directly sent to edge detection unit, therefore its load capacitance (loadcapacitance) is very little, so its time delay be each delay cell time delay j and delay cell number n product (n*j), and select the inhibit signal exported because the delay cell with other is by node, and the detection signal input end of edge detecting unit will could be arrived after output unit selected by multiplexer etc., so the inhibit signal that this selection exports has extra constant time delay o(o >=0), so, from the inhibit signal of above-mentioned maximum delay time in the previous cycle, rank (stage) p of this delay cell is (T-o)/j, the number (thenumberofdelaycellstageqfromep) of corresponding delay cell from rank p to rank q is p-T/j.
Such as, be 300MHz(and T=1/F=1/300MHz in delay cell incoming frequency F) clock signal, the time constant j of each delay units delay is set as 40ps(picosecond), and Additional delay time constant o is 920ps, then rank (i.e. (T-o)/j=(1/300MHzs-920ps)/40ps=60 of 60 delay cells will be had in the inhibit signal of the maximum delay time previous cycle), consistent 83((1/300MHzs is then had in two cycles before the above-mentioned previous cycle)/40ps=83) rank (1cycleaheadfromthemostdelayedsignalwouldbeequalto60stage ofunitcelldelay.2cyclesaheadfromthepointequalto1cyclebef orecorrespondsto83stagesofunitcelldelay.) of individual delay cell.
In addition, if use crystal oscillator (crystaloscillator) to carry out the input of clock signal, then continuous two cycles occur that the probability of mistake and shake is very little, general is millionth probability (bothcycleerrorandjitterareverysmallandittakesppmorder), and low cost, high-precision crystal oscillator can be adopted as the detection signal source of clock of this circuit.
So, by utilizing foregoing circuit, the quantity (quantity of namely shaking) of delay (delaycell) can be measured accurately within a clock period, and be converted into the value (namely with the address in multiplexer) of delay cell, then clock signal is replaced to be applied in the circuit of the application above-mentioned signal, to measure its change and width (Afterdoingthiscalibration accurately, inputsignalappliedtothiscircuitinsteadofclock, itspointofvariationandwidthcanbemeasuredaccurately).
Because the instability of the oscillation frequency (oscillationfrequency) of crystal oscillator (Crystaloscillator) is very low, namely the shake (jitter) produced is very little, need measurement equipment very accurately just can measure the shake of clock signal, the price of the equipment of existing measurement oscillator jitter is all very high, make the cost measuring clock signal jitter very large, then by simple integrated circuit (IC) design in the present embodiment, just can realize the quantitative measurement (measurementquantitatively) of high precision clock shake and inhibit signal, and easily calibration (calibration).
In sum, owing to have employed technique scheme, the embodiment of the present invention proposes a kind of circuit measuring waveform, delay clock signals is exported after clock signal to be measured being postponed by delay array (delaycellarray) successively, and utilize marginal detector unit (edgedetector) and rising edge detecting unit (riseedgefinder) to detect the rising edge of the delay clock signals of coupling, and counter (counter) records the rising edge number that above-mentioned rising edge detecting unit detects, and then draw in the time range preset, the quantitative data of the shake (jitter) of clock signal to be measured, namely this circuit is by utilizing simple integrated circuit, shake and the signal delay (signaldelay) of clock signal can be measured accurately, and simplicity of design cost is low.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. measure a circuit for waveform, it is characterized in that, described circuit comprises:
Signal source of clock to be measured, the delay array including at least three delay cells of series connection, edge detecting unit, rising edge detecting unit sum counter;
Described signal source of clock to be measured provides clock signal to the input end of described delay array;
The selection of described delay array postpones output terminal and is connected with the detection signal input end of described edge detecting unit, and the maximum-delay output terminal of described delay array is connected with the reference signal input of described edge detecting unit;
Described counter is connected with the output terminal of described edge detecting unit by described rising edge detecting unit;
Wherein, the cycle being more than or equal to described clock signal time delay of the maximum-delay clock signal of described maximum-delay output terminal output.
2. the circuit of measurement waveform according to claim 1, is characterized in that, described delay array also comprises a selector switch;
Described selector switch is connected with the output terminal of each described delay cell respectively, selects and exports the detection signal input end of delay clock signals to described edge detecting unit.
3. the circuit of measurement waveform according to claim 2, is characterized in that, each described delay cell includes the phase inverter of two series connection, and the end points that the phase inverter of two series connection connects is connected with described selector switch through another phase inverter.
4. the circuit of measurement waveform according to claim 2, it is characterized in that, described selector switch comprises a multiplexer, this multiplexer is connected with the output terminal of each described delay cell respectively, and the inhibit signal that each described delay cell exports is sent to the detection signal input end of described edge detecting unit successively.
5. the circuit of measurement waveform according to claim 4, is characterized in that, described multiplexer is according to the suitable detection signal the input end successively inhibit signal of each described delay cell being sent to described edge detecting unit of the size of time delay.
6. according to the circuit of the measurement waveform in Claims 1 to 5 described in any one, it is characterized in that, described edge detecting unit comprises the first d type flip flop and the second d type flip flop;
Describedly select to postpone output terminal and to be held with the D of described first d type flip flop respectively by the phase inverter of series connection and the D of the second d type flip flop holds and is connected;
Described maximum-delay output terminal is held with the CP of described first d type flip flop respectively and the CP of the second d type flip flop holds and is connected.
7. the circuit of measurement waveform according to claim 6, it is characterized in that, described select to postpone output terminal hold with the D of described first d type flip flop between circuit in be provided with two phase inverters of connecting, described selection delay output terminal hold with the D of described second d type flip flop between circuit in be provided with four phase inverters of connecting.
8. the circuit of measurement waveform according to claim 6, is characterized in that, described rising edge detecting unit comprises a phase inverter and a Sheffer stroke gate;
The output terminal of described first d type flip flop is connected with an input end of described Sheffer stroke gate by described phase inverter, the output terminal of described second d type flip flop is connected with another input end of described Sheffer stroke gate, and the output terminal of this Sheffer stroke gate is connected with the input end of described counter.
9. according to the circuit of the measurement waveform in Claims 1 to 5 described in any one, it is characterized in that, the time delay that each described delay cell produces is all identical.
10. according to the circuit of the measurement waveform in Claims 1 to 5 described in any one, it is characterized in that, described maximum-delay clock signal is the signal that described clock signal exports successively after all described delay cell.
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| CN104660240B (en) * | 2015-01-04 | 2017-09-15 | 北京化工大学 | Overspeed delay testing clock generator |
| CN108362990A (en) * | 2016-12-28 | 2018-08-03 | 电子科技大学 | High speed signal jitter test circuit and method in piece |
| CN111443240B (en) * | 2020-03-25 | 2022-04-29 | 科华恒盛股份有限公司 | Method and system for capturing voltage waveform of power grid and inverter |
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|---|---|---|---|---|
| CN101232333A (en) * | 2008-01-16 | 2008-07-30 | 中兴通讯股份有限公司 | Clock shake measuring method and oscilloscope for measuring clock shake |
| CN101655384A (en) * | 2009-09-11 | 2010-02-24 | 清华大学 | Method and device for measuring flight time of ultrasonic echo |
| WO2011059432A1 (en) * | 2009-11-12 | 2011-05-19 | Paul Reed Smith Guitars Limited Partnership | Precision measurement of waveforms |
| CN102435865A (en) * | 2011-10-17 | 2012-05-02 | 无锡东集电子有限责任公司 | Adjustable jitter measurement circuit based on self-reference signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7439724B2 (en) * | 2003-08-11 | 2008-10-21 | International Business Machines Corporation | On-chip jitter measurement circuit |
| US7236555B2 (en) * | 2004-01-23 | 2007-06-26 | Sunrise Telecom Incorporated | Method and apparatus for measuring jitter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232333A (en) * | 2008-01-16 | 2008-07-30 | 中兴通讯股份有限公司 | Clock shake measuring method and oscilloscope for measuring clock shake |
| CN101655384A (en) * | 2009-09-11 | 2010-02-24 | 清华大学 | Method and device for measuring flight time of ultrasonic echo |
| WO2011059432A1 (en) * | 2009-11-12 | 2011-05-19 | Paul Reed Smith Guitars Limited Partnership | Precision measurement of waveforms |
| CN102435865A (en) * | 2011-10-17 | 2012-05-02 | 无锡东集电子有限责任公司 | Adjustable jitter measurement circuit based on self-reference signal |
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