CN104393879B - A kind of air-ground narrow-band communication system for unmanned plane - Google Patents
A kind of air-ground narrow-band communication system for unmanned plane Download PDFInfo
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Abstract
The invention discloses a kind of air-ground narrow-band communication system for unmanned plane, including the transmitting terminal for ground installation and the receiving terminal for ground unmanned plane；Described transmitting terminal includes a FPGA, DAC, filter circuit and radiofrequency emitting module, described receiving terminal includes Receiver Module, intermediate frequency filtering module, ADC and the 2nd FPGA, Receiver Module receives the signal of communication from outside and the control signal from the 2nd FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected by ADC and the 2nd FPGA, the gain control output of the 2nd FPGA is connected with Receiver Module, and the 2nd FPGA is also by internal interface demodulated output data.The present invention, to carrying out perfect by the earth-space communication subsystem in the system of unmanned plane that passes of remote measurement, remote control, number, has that transmitting terminal is low in energy consumption, receiving terminal data process the advantage such as accurately.
Description
Technical field
The present invention relates to a kind of air-ground narrow-band communication system for unmanned plane.
Background technology
Unmanned plane has that cost effectiveness is low, zero injures and deaths and dispose the advantage such as flexibly, can help even to replace the mankind to play a role in a lot of scenes, such as the personnel's search and rescue after calamity, infrastructure supervision etc..No matter in civilian or military domain, unmanned plane all has wide application and development prospect.
The system of unmanned plane that passes of remote measurement, remote control, number can include Air-Ground two-way communication and ground-ground two-way communication two parts, divide according to wire data type, wideband signal communication can be divided into communicate with narrow band signal two types, wherein broadband signal is unmanned plane reconnaissance image data transmission service and unmanned plane telemetry service, narrow band signal is underwater acoustic remote control business between handheld terminal and unmanned plane, communication service between handheld terminal and car-mounted terminal.And narrow band communication includes the transmitting terminal for ground installation and the reception terminal for unmanned plane.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of transmitting terminal is low in energy consumption, receiving terminal data process the accurate air-ground narrow-band communication system for unmanned plane.
It is an object of the invention to be achieved through the following technical solutions: a kind of air-ground narrow-band communication system for unmanned plane, it includes the transmitting terminal for ground installation and the receiving terminal for unmanned plane；
Described transmitting terminal includes a FPGA, DAC, high-frequency filter circuit and radiofrequency emitting module, the data signal output of the oneth FPGA is connected with DAC, the power of the oneth FPGA controls output and is connected with radiofrequency emitting module, the output of DAC is connected with high-frequency filter circuit, and the output of high-frequency filter circuit is connected with radiofrequency emitting module；
A described FPGA includes interleaving block, framing module, convolutional encoder module, QPSK mapping block, molding filtration module, DUC module and power control module, data source input interleaving block, the output of interleaving block is connected with framing module, the output of framing module is connected with convolutional encoder module, the output of convolutional encoder module is connected with QPSK mapping block, the output of QPSK mapping block is connected with molding filtration module, the output of molding filtration module is connected with DUC module, the output of DUC module is connected with DAC, the output of power control module is connected with radiofrequency emitting module；
Described receiving terminal includes Receiver Module, intermediate frequency filtering module, ADC and the 2nd FPGA, Receiver Module receives the signal of communication from outside and the control signal from the 2nd FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with the 2nd FPGA, the clock control output of the 2nd FPGA is connected with ADC, the gain control output of the 2nd FPGA is connected with Receiver Module, and the 2nd FPGA is also by internal interface demodulated output data；
nullThe 2nd described FPGA includes down conversion module、Decimal abstraction module、Thick frequency offset correction module、Narrow-band filtering module、Bit sync module、Essence frequency deviation synchronization module、Decoding/judging module、De-interleaving block and at the uniform velocity buffer module，The input of down conversion module is connected with ADC，The output of down conversion module is connected with decimal abstraction module，The output of decimal abstraction module is connected with thick frequency offset correction module，The output of thick frequency offset correction module is connected with narrow-band filtering module，The output of narrow-band filtering module is connected with bit sync module，The output of bit sync module is connected with essence frequency deviation synchronization module，The output of essence frequency deviation synchronization module is connected with decoding/judging module，The output of decoding/judging module is connected with de-interleaving block，The output of de-interleaving block is connected with at the uniform velocity buffer module，The at the uniform velocity output of buffer module exports demodulation gain by internal interface.
Described molding filtration module uses the root raised cosine filtering of alhpa=0.5, and exponent number scope is 48-52；The parameter of described convolutional encoder module is (2,1,7).
Described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of orthogonal mixting circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, orthogonal mixting circuit output I, Q two paths of signals is to low-pass filter circuit, and low-pass filter circuit output I, Q two paths of signals is to decimal abstraction module.Described digital controlled oscillation circuit uses cordic algorithm, only consumes a small amount of register and adder resource, does not consume RAM, and resource loss is substantially negligible to be disregarded.
The baseband signal that down conversion module is obtained by described decimal abstraction module carries out little several times extraction, and output signal sample value is to thick frequency offset correction module；Described narrow-band filtering module is for further filtering out the out-of-band noise of remnants.
Owing to after despreading, signal bandwidth only has about 180kHz, and high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be outside transnormal phaselocked loop capture zone, so carrier synchronization partial resolution becomes " thick frequency offset correction " and " essence frequency deviation synchronization " two links here.
Described thick frequency offset correction module includes orthogonal mixting circuit, eliminate modulation intelligence circuit, fft circuit, spectral line peak search circuit, calculate frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit receives the signal from the output of decimal abstraction module, the output of orthogonal mixting circuit is connected with narrow-band filtering module and elimination modulation intelligence circuit respectively, the output eliminating modulation intelligence circuit is connected with fft circuit, the output of fft circuit is connected with spectral line peak search circuit, the output of spectral line peak search circuit is connected with calculating frequency deviation circuit, the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.
Input signal is 4 times of symbol sampler rates, enters 4 power computing modules, eliminates the modulation intelligence of QPSK, it is thus achieved that single audio frequency dot information.Through FFT and spectral line peak value searching, thick frequency deviation information can be obtained.Wherein use 2048 points of counting of FFT, it is possible to obtain of a sufficiently low residual frequency deviation, it is ensured that the normal capture of essence frequency deviation synchronization module.After correction once, the thick frequency deviation information that follow-up FFT several times obtains is close, and peak value is enough, then it is assumed that stablized, it is not necessary to correct again；Otherwise it is assumed that system step-out, re-start thick frequency offset correction.
Owing to frequency deviation is relatively big, DDC, enforcement is the filtering in somewhat broadband, it is ensured that signal spectrum is without damage；After thick frequency offset correction completes, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants.Described narrow-band filtering module is for further filtering out the out-of-band noise of remnants.
Owing to the signal bandwidth of narrow band signal is less, do not use the balancing techniques such as SCFDE.
Bit synchronization uses Gardner algorithm, to a small amount of residual frequency deviation insensitive (according to 3kHz maximum frequency deviation, about 4.5Mbaud/s baud rate is calculated, and residual frequency deviation is about about the 0.1% of chip rate), before may be located at frequency synchronization module.After input data carry out little several times interpolation/extraction, obtain the signal of 4 times of symbol sampler rates；4 times of sample value signals are carried out gardner bit timing estimation error, obtains instantaneous error value, after filtering high-frequency noise by loop filter, drive NCO to produce timing interpolation and enable and interpolated parameter；" Farrow timing interpolation " module uses farrow structure, and interpolation obtains bit decision point accurately, eventually through output Buffer output；Described Farrow structure is that a kind of efficient polynomial interpolation realizes structure.
nullDescribed bit sync module includes inputting buffer module、Reg module、Timing error estimate module、Loop filter、Digital controlled oscillation circuit、Regularly interpolation module、Output buffer module and two shift registers，The input of input buffer module is connected with narrow-band filtering module，The output of input buffer module is connected with reg module，The output of reg module is connected with one of them shift register，The output of this shift register is connected with timing interpolation module，Regularly a road output of interpolation module is connected with another shift register，The output of this shift register is connected with timing error module，The output of Timing error estimate module is connected with loop filter，The output of loop filter is connected with digital controlled oscillation circuit，The output of digital controlled oscillation circuit is connected with timing interpolation module，Regularly another road output of interpolation module is by output buffer module output data.
Described smart frequency deviation synchronization module includes orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way is connected with bit sync module, the output of orthogonal mixting circuit is connected with phase error estimation and phase error circuit and decoding/judging module respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.Described digital controlled oscillation circuit practicality DDS algorithm rather than cordic algorithm, because the sequential amount of delay of cordic logic is bigger in FPGA, cause loop delay big, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, it is ensured that loop capturing behavior and the performance of the behavior of tracking.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block is used for realizing simply buffering read-write.
Described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel output of data buffering module is connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular is connected with loop filtering module, the output of loop filtering module is connected with numerical control oscillation module, one tunnel output of numerical control oscillation module is connected with data buffering module, another road output clock signal of numerical control oscillation module.
Described Receiver Module is identical with radiofrequency emitting module structure, including duplexer, transmitting terminal processing module, receiving terminal processing module and driving module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
The invention has the beneficial effects as follows: for transmitting terminal: native system uses frequency division multiple access to work while supporting multi-aircraft, in the case of frequency division multiple access, base band instantaneous modulation speed ratio is relatively low, under same effective speed, the required transient transmission power consumed of aircraft is much lower relative to time division multiple acess and CDMA, and this is very important for the SUAV that volume and power are the most limited；For receiving terminal: the signal of (1) ADC input obtains baseband signal through down coversion, digital controlled oscillation circuit in down coversion uses cordic algorithm to realize, only consuming a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible to be disregarded；(2) baseband signal carries out little several times extraction, obtains the signal sample of 4 times of chip rates, then carries out matched filtering, advantage of this is that the calculating of beneficially matched filtering coefficient；(3) due to despreading after signal bandwidth only have about 180kHz, and high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be outside transnormal phaselocked loop capture zone, so carrier synchronization partial resolution becomes " thick frequency offset correction " and " essence frequency deviation synchronization " two links here；(4) relatively big due to frequency deviation, DDC, enforcement is the filtering in somewhat broadband, it is ensured that signal spectrum is without damage；(5) after thick frequency offset correction completes, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants；(6) narrow band signal signal bandwidth is less, not in use by balancing techniques such as SCFDE, cost-effective；(7) bit information after judgement is through channel decoding, obtains the result after error correction, and in order to support the precise time label of remote measurement, demodulating data will at the uniform velocity export；(8) due to above some, the present invention be just applicable to a kind of can the reception terminal of air-ground narrow-band communication system of unmanned plane that passes of remote measurement, remote control, number, receive terminal and include unmanned plane terminal.
Accompanying drawing explanation
Fig. 1 is present configuration block diagram；
Fig. 2 is transmitting terminal FPGA function module structure chart；
Fig. 3 is receiving terminal FPGA function module structure chart；
Fig. 4 is down conversion module structure chart；
Fig. 5 is thick frequency offset correction function structure chart；
Fig. 6 is bit sync module structure chart；
Fig. 7 is Farrow structured flowchart；
Fig. 8 is essence frequency deviation synchronization module structure chart；
Fig. 9 is at the uniform velocity buffer module structure chart；
Figure 10 is ground surface end radiofrequency emitting module structure chart；
Figure 11 is unmanned plane end Receiver Module structure chart.
Detailed description of the invention
Technical scheme is described in further detail below in conjunction with the accompanying drawings: as it is shown in figure 1, a kind of air-ground narrow-band communication system for unmanned plane, it includes the transmitting terminal for ground installation and the receiving terminal for unmanned plane；
Described transmitting terminal includes a FPGA, DAC, high-frequency filter circuit and radiofrequency emitting module, the data signal output of the oneth FPGA is connected with DAC, the power of the oneth FPGA controls output and is connected with radiofrequency emitting module, the output of DAC is connected with high-frequency filter circuit, and the output of high-frequency filter circuit is connected with radiofrequency emitting module；Signal bandwidth is about 200kHz, and it is-110dBm ~ 30dBm that transmitting terminal launches power controlled range.
As shown in Figure 2, a described FPGA includes interleaving block, framing module, convolutional encoder module, QPSK mapping block, molding filtration module, DUC module and power control module, data source input interleaving block, the output of interleaving block is connected with framing module, the output of framing module is connected with convolutional encoder module, the output of convolutional encoder module is connected with QPSK mapping block, the output of QPSK mapping block is connected with molding filtration module, the output of molding filtration module is connected with DUC module, the output of DUC module is connected with DAC, the output of power control module is connected with radiofrequency emitting module；
Described receiving terminal includes Receiver Module, intermediate frequency filtering module, ADC and the 2nd FPGA, Receiver Module receives the signal of communication from outside and the control signal from the 2nd FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with the 2nd FPGA, the clock control output of the 2nd FPGA is connected with ADC, the gain control output of the 2nd FPGA is connected with Receiver Module, and the 2nd FPGA is also by internal interface demodulated output data；
nullAs shown in Figure 3，The 2nd described FPGA includes down conversion module、Decimal abstraction module、Thick frequency offset correction module、Narrow-band filtering module、Bit sync module、Essence frequency deviation synchronization module、Decoding/judging module、De-interleaving block and at the uniform velocity buffer module，The input of down conversion module is connected with ADC，The output of down conversion module is connected with decimal abstraction module，The output of decimal abstraction module is connected with thick frequency offset correction module，The output of thick frequency offset correction module is connected with narrow-band filtering module，The output of narrow-band filtering module is connected with bit sync module，The output of bit sync module is connected with essence frequency deviation synchronization module，The output of essence frequency deviation synchronization module is connected with decoding/judging module，The output of decoding/judging module is connected with de-interleaving block，The output of de-interleaving block is connected with at the uniform velocity buffer module，The at the uniform velocity output of buffer module exports demodulation gain by internal interface.
Described molding filtration module uses the root raised cosine filtering of alhpa=0.5, and exponent number scope is 48-52；The parameter of described convolutional encoder module is (2,1,7).
As shown in Figure 4, described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of orthogonal mixting circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, orthogonal mixting circuit output I, Q two paths of signals is to low-pass filter circuit, low-pass filter circuit output I, Q two paths of signals uses cordic algorithm to decimal abstraction module, described digital controlled oscillation circuit.Only consuming a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible to be disregarded.Local oscillator module, when initial, arranges 160MHz intermediate frequency mirror image (numerical frequency the is 2 * pi * 3/10) frequency of standard.In despreading acquisition procedure, need the rough frequency deviation value of signal is scanned for, so here with the frequency search parameter input from despreading module.
The baseband signal that down conversion module is obtained by described decimal abstraction module carries out little several times extraction, and output signal sample value is to thick frequency offset correction module；Described narrow-band filtering module is for further filtering out the out-of-band noise of remnants.
Owing to after despreading, signal bandwidth only has about 180kHz, and high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be outside transnormal phaselocked loop capture zone, so carrier synchronization partial resolution becomes " thick frequency offset correction " and " essence frequency deviation synchronization " two links here.
As shown in Figure 5, described thick frequency offset correction module includes orthogonal mixting circuit, eliminate modulation intelligence circuit, fft circuit, spectral line peak search circuit, calculate frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit receives the signal from the output of decimal abstraction module, the output of orthogonal mixting circuit is connected with narrow-band filtering module and elimination modulation intelligence circuit respectively, the output eliminating modulation intelligence circuit is connected with fft circuit, the output of fft circuit is connected with spectral line peak search circuit, the output of spectral line peak search circuit is connected with calculating frequency deviation circuit, the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.
Input signal is 4 times of symbol sampler rates, enters 4 power computing modules, eliminates the modulation intelligence of QPSK, it is thus achieved that single audio frequency dot information.Through FFT and spectral line peak value searching, thick frequency deviation information can be obtained.Wherein use 2048 points of counting of FFT, it is possible to obtain of a sufficiently low residual frequency deviation, it is ensured that the normal capture of essence frequency deviation synchronization module.After correction once, the thick frequency deviation information that follow-up FFT several times obtains is close, and peak value is enough, then it is assumed that stablized, it is not necessary to correct again；Otherwise it is assumed that system step-out, re-start thick frequency offset correction.
Owing to frequency deviation is relatively big, DDC, enforcement is the filtering in somewhat broadband, it is ensured that signal spectrum is without damage；After thick frequency offset correction completes, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants.Described narrow-band filtering module is for further filtering out the out-of-band noise of remnants.
Owing to the signal bandwidth of narrow band signal is less, do not use the balancing techniques such as SCFDE.
Bit synchronization uses Gardner algorithm, to a small amount of residual frequency deviation insensitive (according to 3kHz maximum frequency deviation, about 4.5Mbaud/s baud rate is calculated, and residual frequency deviation is about about the 0.1% of chip rate), before may be located at frequency synchronization module.After input data carry out little several times interpolation/extraction, obtain the signal of 4 times of symbol sampler rates；4 times of sample value signals are carried out gardner bit timing estimation error, obtains instantaneous error value, after filtering high-frequency noise by loop filter, drive NCO to produce timing interpolation and enable and interpolated parameter；" Farrow timing interpolation " module uses farrow structure, and interpolation obtains bit decision point accurately, eventually through output Buffer output；Described Farrow structure is that a kind of efficient polynomial interpolation realizes structure, as shown in Figure 7.
nullAs shown in Figure 6，Described bit sync module includes inputting buffer module、Reg module、Timing error estimate module、Loop filter、Digital controlled oscillation circuit、Regularly interpolation module、Output buffer module and two shift registers，The input of input buffer module is connected with narrow-band filtering module，The output of input buffer module is connected with reg module，The output of reg module is connected with one of them shift register，The output of this shift register is connected with timing interpolation module，Regularly a road output of interpolation module is connected with another shift register，The output of this shift register is connected with timing error module，The output of Timing error estimate module is connected with loop filter，The output of loop filter is connected with digital controlled oscillation circuit，The output of digital controlled oscillation circuit is connected with timing interpolation module，Regularly another road output of interpolation module is by output buffer module output data.
As shown in Figure 8, described smart frequency deviation synchronization module includes orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way is connected with bit sync module, the output of orthogonal mixting circuit is connected with phase error estimation and phase error circuit and decoding/judging module respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.Described digital controlled oscillation circuit practicality DDS algorithm rather than cordic algorithm, because the sequential amount of delay of cordic logic is bigger in FPGA, cause loop delay big, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, it is ensured that loop capturing behavior and the performance of the behavior of tracking.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block is used for realizing simply buffering read-write.
As shown in Figure 9, described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel output of data buffering module is connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular is connected with loop filtering module, the output of loop filtering module is connected with numerical control oscillation module, one tunnel output of numerical control oscillation module is connected with data buffering module, another road output clock signal of numerical control oscillation module.
As shown in Figure 10, described Receiver Module is identical with radiofrequency emitting module structure, including duplexer, transmitting terminal processing module, receiving terminal processing module and driving module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
As shown in Figure 10, at transmission channel, 70
The up remote signal of MHz() after intermediate-freuqncy signal enters this module, through fading to the up remote signal of 1430MHz(with the mixing of frequency conversion local oscillator) it is interior that (each unmanned plane takies 7MHz bandwidth, totally 5 groups of unmanned planes, frequency range is spaced about 10MHz, i.e. take 80MHz bandwidth), amplified carrying out numerical control attenuation, attenuation range is 30dB, makes signal have 30dB dynamic range.Then signal is amplified and export as upward signal.Wherein numerical-control attenuator needs 5 parallel-by-bit codes to control, and local oscillator needs SPI code to control.
As shown in figure 11, receive passage, the up remote signal of 1430MHz() signal through low noise amplify post filtering amplify again, be mixed to 70 ± 2MHz.Exporting after being amplified by intermediate frequency, power output is-5dBm～0dBm.
Claims (8)
1. the air-ground narrow-band communication system for unmanned plane, it is characterised in that: it includes the transmitting terminal for ground installation and the receiving terminal for unmanned plane；
Described transmitting terminal includes a FPGA, DAC, high-frequency filter circuit and radiofrequency emitting module, the data signal output of the oneth FPGA is connected with DAC, the power of the oneth FPGA controls output and is connected with radiofrequency emitting module, the output of DAC is connected with high-frequency filter circuit, and the output of high-frequency filter circuit is connected with radiofrequency emitting module；
A described FPGA includes interleaving block, framing module, convolutional encoder module, QPSK mapping block, molding filtration module, DUC module and power control module, data source input interleaving block, the output of interleaving block is connected with framing module, the output of framing module is connected with convolutional encoder module, the output of convolutional encoder module is connected with QPSK mapping block, the output of QPSK mapping block is connected with molding filtration module, the output of molding filtration module is connected with DUC module, the output of DUC module is connected with DAC, the output of power control module is connected with radiofrequency emitting module；
Described receiving terminal includes Receiver Module, intermediate frequency filtering module, ADC and the 2nd FPGA, the gain control that Receiver Module receives from outside signal of communication and from the 2nd FPGA exports, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with the 2nd FPGA, the clock control output of the 2nd FPGA is connected with ADC, the gain control output of the 2nd FPGA is connected with Receiver Module, and the 2nd FPGA is also by internal interface demodulated output data；
nullThe 2nd described FPGA includes down conversion module、Decimal abstraction module、Thick frequency offset correction module、Narrow-band filtering module、Bit sync module、Essence frequency deviation synchronization module、Decoding/judging module、De-interleaving block and at the uniform velocity buffer module，The input of down conversion module is connected with ADC，The output of down conversion module is connected with decimal abstraction module，The output of decimal abstraction module is connected with thick frequency offset correction module，The output of thick frequency offset correction module is connected with narrow-band filtering module，The output of narrow-band filtering module is connected with bit sync module，The output of bit sync module is connected with essence frequency deviation synchronization module，The output of essence frequency deviation synchronization module is connected with decoding/judging module，The output of decoding/judging module is connected with de-interleaving block，The output of de-interleaving block is connected with at the uniform velocity buffer module，The at the uniform velocity output of buffer module exports demodulation gain by internal interface.
A kind of air-ground narrow-band communication system for unmanned plane the most according to claim 1, it is characterised in that: described molding filtration module uses the root raised cosine filtering of alhpa=0.5, and exponent number scope is 48-52；The parameter of described convolutional encoder module is (2,1,7).
A kind of air-ground narrow-band communication system for unmanned plane the most according to claim 1, it is characterized in that: described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of orthogonal mixting circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, orthogonal mixting circuit output I, Q two paths of signals is to low-pass filter circuit, low-pass filter circuit output I, Q two paths of signals uses cordic algorithm to decimal abstraction module, described digital controlled oscillation circuit.
A kind of air-ground narrow-band communication system for unmanned plane the most according to claim 1, it is characterized in that: described thick frequency offset correction module includes orthogonal mixting circuit, eliminate modulation intelligence circuit, fft circuit, spectral line peak search circuit, calculate frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit receives the signal from the output of decimal abstraction module, the output of orthogonal mixting circuit is connected with narrow-band filtering module and elimination modulation intelligence circuit respectively, the output eliminating modulation intelligence circuit is connected with fft circuit, the output of fft circuit is connected with spectral line peak search circuit, the output of spectral line peak search circuit is connected with calculating frequency deviation circuit, the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.
nullA kind of air-ground narrow-band communication system for unmanned plane the most according to claim 1，It is characterized in that: described bit sync module includes inputting buffer module、Register module、Timing error estimate module、Loop filter、Digital controlled oscillation circuit、Regularly interpolation module、Output buffer module and two shift registers，The input of input buffer module is connected with narrow-band filtering module，The output of input buffer module is connected with register module，The output of register module is connected with one of them shift register，The output of this shift register is connected with timing interpolation module，Regularly a road output of interpolation module is connected with another shift register，The output of this shift register is connected with timing error module，The output of Timing error estimate module is connected with loop filter，The output of loop filter is connected with digital controlled oscillation circuit，The output of digital controlled oscillation circuit is connected with timing interpolation module，Regularly another road output of interpolation module is by output buffer module output data.
A kind of air-ground narrow-band communication system for unmanned plane the most according to claim 1, it is characterized in that: described smart frequency deviation synchronization module includes orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way is connected with bit sync module, the output of orthogonal mixting circuit is connected with phase error estimation and phase error circuit and decoding/judging module respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit, described digital controlled oscillation circuit practicality DDS algorithm.
A kind of air-ground narrow-band communication system for unmanned plane the most according to claim 1, it is characterized in that: described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel output of data buffering module is connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular is connected with loop filtering module, the output of loop filtering module is connected with numerical control oscillation module, one tunnel output of numerical control oscillation module is connected with data buffering module, another road output clock signal of numerical control oscillation module.
A kind of air-ground narrow-band communication system for unmanned plane the most according to claim 1, it is characterized in that: described Receiver Module is identical with radiofrequency emitting module structure, including duplexer, transmitting terminal processing module, receiving terminal processing module and driving module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
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