CN104317728B - A kind of method and apparatus of safety reset storage device - Google Patents
A kind of method and apparatus of safety reset storage device Download PDFInfo
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- CN104317728B CN104317728B CN201410539190.4A CN201410539190A CN104317728B CN 104317728 B CN104317728 B CN 104317728B CN 201410539190 A CN201410539190 A CN 201410539190A CN 104317728 B CN104317728 B CN 104317728B
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Abstract
The invention discloses a kind of method and apparatus of safety reset storage device, to solve under prior art, circuit board is not protected before reset to the related data for being related to storage device, so as to cause reset after system overall operation mistake the problem of.This method includes：After programming device reception reset signal interrupt signal is sent to central processor CPU；CPU performs interrupt processing operation, and programming device is notified after interrupt processing operation is completed, and the interrupt processing is operated for carrying out emergent management to the system task for being currently not carried out finishing；After programming device receives the notice, perform the reset signal and complete to reset.
Description
Technical field
The application is related to electronic device field, more particularly to a kind of method and apparatus of safety reset storage device.
Background technology
It is growing with information technology, it is desirable to communication equipment can handle and preserve increasing data, so
Circuit board in communication equipment has been generally designed associated storage device, such as hard disk, electric board, CF cards.In the fortune of circuit board
It is essential to carry out the operation of some circuit sheet resets during row, such as the reset of software release upgrade, watchdog reset, press
Key reset etc..A problem is thus brought, these "abnormal" of circuit board in the process of running reset, particularly system or use
Family is reset while accessing storage device, and after often there is system restarting, system can not normally access storage device, table
It is now Bad Track, accesses phenomena such as overtime, file system is destroyed.Above-mentioned signified " exceptional reset ", it is understood that be hard
Resetting, the reboot system commands carried different from (SuSE) Linux OS, it does not carry out protection processing before any reset, it
The operation irregularity of storage device internal circuit block can be caused, either Bad Track or file system are destroyed, and easy data
Lose；And reboot orders can carry out some software pretreatments before resetting processor, as performed the system script before resetting, killing
Fall into journey and preserve data etc., these exceptional resets can be referred both to safety reset system, reset as referred to herein.
Under prior art, the reseting logic of circuit board is as shown in Figure 1.General circuit plate can all pass through field-programmable gate array
Arrange (Field Programmable Gate Array, FPGA)/CPLD (Complex
Programmable Logic Device, CPLD) carry out control process reset signal.First, reset signal enters FPGA/CPLD,
Then by it come the reset of control processor, internal memory and peripheral hardware (including storage device).As button reset, watchdog reset,
Logic reset (is such as resetted) by software control FPGA/CPLD control whole plates, can not carry out what similar linux system carried
The performed protection act of reboot orders, so, it may result in above-mentioned Bad Track, access time-out, file system destruction etc.
Phenomenon.Existing circuit board resetting technique, its focus concentrates on the processing of hardware circuit reset signal, before not accounting for reset
Protection to storage device, thus have the following disadvantages：
First, if performing above-mentioned reset operation, especially resetted while storage device is accessed, above-mentioned magnetic can be caused
Disk bad track, access phenomena such as time-out, file system destruction.
Secondly, if performing above-mentioned reset operation when storage device is accessed, it is also possible to cause system operation mistake.
Such as (SuSE) Linux OS has a kind of mechanism for referred to as writing (write-back) from the background, i.e. data are not straight
Connect and write (write-through) and enter into hard disk, but first write in caching, again by rear after kernel meets some requirements
Platform writes hard disk.Backstage write-in is more more effective than writing direct hard disk, but also easily error, if data are prominent before not writing hard disk
Above-mentioned reset operation is so performed, then the data in caching will lose, may if the data lost contain important information
Mean that file system (if any) is imperfect, so as to cause system overall operation mistake.
The content of the invention
The embodiment of the present invention provides a kind of method and apparatus of safety reset storage device, to solve under prior art,
Circuit board is not protected before reset to the related data for being related to storage device, so as to cause system overall operation after resetting
The problem of mistake.
Concrete technical scheme provided in an embodiment of the present invention is as follows：
On the one hand, the present invention passes through one embodiment in the application, there is provided following technical scheme：
A kind of method of safety reset storage device, methods described include：
After programming device reception reset signal interrupt signal is sent to central processor CPU；
CPU performs interrupt processing operation, and notifies programming device, the interrupt processing after interrupt processing operation is completed
Operate for carrying out emergent management to the system task for being currently not carried out finishing；
After programming device receives the notice, perform the reset signal and complete to reset.
The interrupt processing operation specifically includes：
Signal out of service is sent to all processes；
By the data write storage device in caching；
Perform in interrupt processing operating process, all processes are being sent with signal out of service, and by the data in caching
Write storage device and then secondary sent to all processes force signal out of service, and again write the data in caching
Enter storage device.
In interrupt processing operation, before signal out of service is sent to all processes, in addition to interruption at
Reason operation carries out locking operation.
Alternatively, in interrupt processing operation, before signal out of service is sent to all processes, in addition to：
Send and notify to specified process, the instruction specified process performs the emergent management operation before resetting.
On the other hand, the present invention passes through one embodiment in the application, there is provided following technical scheme：
A kind of device of safety reset storage device, it is characterised in that including programming device and central processor CPU,
Wherein,
Programming device, interrupt signal is sent to CPU after reset signal for receiving, and complete interrupt processing in CPU
Reset signal is performed after operation to complete to reset；
CPU, operated for execution interrupt processing after receiving the interrupt signal sent by programming device, and complete to interrupt
Programming device is notified after processing operation, the interrupt processing operates tight for being carried out to the system task for being currently not carried out finishing
Anxious processing.
When processing of breaking in commission operates, the CPU is specifically used for：
Signal out of service is sent to all processes；
By the data write storage device in caching；
Before sending signal out of service to all processes, send and notify to specified process, instruction is described specify into
Emergent management operates before Cheng Zhihang resets.
CPU is further used for：
All processes are being sent with signal out of service, and by after the data write storage device in caching, to all
Process, which is sent, forces signal out of service, again by the data write storage device in caching.
Before signal out of service is sent to all processes, the interrupt processing is operated and performs locking operation.
Programming device is on-site programmable gate array FPGA or complex programmable logic device (CPLD).
The present invention has the beneficial effect that：
First, before circuit sheet reset, by the data cached write storage device in system, number is cached after avoiding reset
According to storage device data caused by loss it is asynchronous, further result in the problem of system overall operation exception.
Secondly, the protection before being resetted using interrupt processing operation to the related data for being related to storage device, without people
To intervene.
Brief description of the drawings
Fig. 1 is the reseting logic figure of circuit board under prior art；
Fig. 2 is the reseting logic figure of the circuit board in the embodiment of the present application；
Fig. 3 is the flow chart of the safety reset storage device method in the embodiment of the present application；
Fig. 4 is a concrete application scene flow chart of the safety reset storage device method in the embodiment of the present application；
Fig. 5 is the apparatus structure schematic diagram for being used for safety reset storage device in the embodiment of the present application.
Embodiment
In order that the application the technical staff in the technical field is more clearly understood that the application, below in conjunction with the accompanying drawings,
Technical scheme is described in detail by specific embodiment.
The reseting logic of circuit board in the application is as shown in Fig. 2 wherein, programmable device FPGA/CPLD and CPU, deposit
Storage equipment is connected with the reset pin of other peripheral hardwares, and is also connected with CPU interrupt pin.Reseting logic includes：
After FPGA/CPLD receives reset signal, reset signal directly is not sent to coupled equipment, but
CPU interrupt pin is connected and produces interrupt signal；
CPU is operated after receiving interrupt signal by CPU execution interrupt processings, and interrupt processing operation will be data cached in system
Write storage device, so as to keep the data syn-chronization of storage device；
CPU notifies FPGA/CPLD, FPGA/CPLD are sent to coupled equipment to reset after completing interrupt processing operation
Signal is completed to reset.
As shown in fig.3, in the embodiment of the present invention, the idiographic flow of safety reset storage device is as follows：
Step 300：After programming device reception reset signal interrupt signal is sent to CPU；
Step 310：CPU performs interrupt processing operation, and notifies programming device after interrupt processing operation is completed, its
In, interrupt processing is operated for carrying out emergent management to the system task for being currently not carried out finishing；Interrupt processing operates.
Specifically include：
In the present embodiment, when performing step 310, interrupt processing is operated perform locking operation first, and remove interruption
Processing mark, so processing are in order to avoid interrupt processing operation is not disturbed by other interruptions in the process of implementation, make interruption
Processing operation is normal to be performed.
After locking operation is carried out to interrupt processing operation, begin to perform and the data for being related to storage device are protected
The key operation of shield, specifically, CPU can send signal out of service to all processes, so that it is guaranteed that the stopping pair of all processes
Deposit several equipment to be written and read, then by the data write storage device in caching, so processing is in order to ensure resetting the moment, depositing
Be to cache it is central i.e. will the data of write storage device be veritably written with storage device, rather than only mark data
The data structure of storage location has updated, but data do not write really before reset, so as to which the synchronization of data be effectively ensured.
,, can be according to mark number when process accesses storage device again after completing to reset operation by aforesaid operations
Storage device is correctly accessed according to the data structure of storage location.
Under some application scenarios in practical application, there can be part and have the ability to ignore entering for system " signal out of service "
Journey, the influence that can not retract is caused to such process in order to avoid resetting operation, can before performing and resetting operation, to it is all enter
Journey sends " forcing signal out of service ", and operation can be also forcibly stopped by ignoring the process of system " signal out of service ".
After sending " forcing signal out of service " to all processes, CPU can perform corresponding data cached write-in again
The operation of storage device, so, the synchronization of data can be again ensured that, without by any process before reset operation is performed
Disturbed, the safe write storage device of the data in all cachings, it is asynchronous so as to avoid occurring the data in storage device,
Process accesses the problem of storage device malfunctions after further resulting in reset, and then has ensured the safe to use of storage device.
In above process, if some processes can not be forced to forbid, in order to ensure such process not because forcing to stop
And its key operation that must be completed is not completed, preferably, before " forcing signal out of service " is sent to above-mentioned process, also
Need to send " notice " to such process, indicate the process perform reset before emergent management operation, and receive specify into
When journey feedback emergent management operates successful message, then start to send signal out of service to above-mentioned all processes, so that it is guaranteed that
Important process will not malfunction because of forced interruption, effectively prevent the abnormal conditions occurred because forcing to stop.
Step 320：After programming device receives above-mentioned notice, perform reset signal and complete to reset.
Explaination in detail is made further to above-mentioned flow using a specific application scenarios below, as shown in fig.4, tool
It is as follows that body resets flow：
Step 400：After programming device (e.g., FPGA/CPLD) receives reset signal, by the interruption in programming device
The respective interrupt pin current potential for the CPU being connected with FPGA/CPLD is set low triggering and interrupted by generation unit.
Step 401：CPU carries out locking operation to interrupt processing operation.
Step 402：It is SIGTERM signals that CPU sends signal out of service to all processes.
Preferably, this operation can be passed by calling kernel function sys_kill functions using SIGTERM signals as parameter
Enter the realization of sys_kill functions.
Step 403：CPU is by the data write storage device in caching.
Preferably, this operation can be by calling kernel function sys_sync () function to realize.
Step 404：CPU sends SIGKILL signals to all processes.
Preferably, this operation can be by calling kernel function sys_kill functions to realize, using SIGKILL signals as ginseng
The incoming sys_kill functions of number are realized.
Step 405：CPU is by the data write storage device in caching.
Preferably, this operation can be by calling kernel function sys_sync () to realize.
Step 406：After programming device receives the notice that interrupt processing operation terminates, perform reset signal and complete again
Position.
In the application truth example, preferably, operating system is (SuSE) Linux OS, therefore the CPU referred in the present embodiment
Interruption service handler in the interrupt processing operation specially (SuSE) Linux OS of execution, above-mentioned steps 402 to step
405 belong to interrupt handling routine, and similarly, the signal referred in above-mentioned steps is also linux kernel signal.
Interruption service processing operation in (SuSE) Linux OS, which is divided into interrupting top half and interrupting bottom half two parts, holds
OK, wherein top half is used for handling the work that as early as possible and can be rapidly completed, and otherwise can block the arrival of other interruptions and release
Cpu resource is put to user or process；And bottom half is used for handling time-consuming task, performs, keep away within the system safer time
Exempt to cause system congestion or CPU to discharge.
The characteristics of based on Linux interrupt mechanisms, in the interrupt processing operation in the present embodiment, interrupt processing is operated and carried out
The top half that operation is locked in interrupt processing processing operation performs, and is related to the pass protected to the related data of storage device
Key operation 402 performs to step 405 in the bottom half for interrupting interrupt processing processing operation.
As shown in fig.5, in the embodiment of the present invention, the device for safety reset storage device include programming device and
CPU, wherein,
Programming device 50, interrupt signal is sent to CPU after reset signal for receiving, and completed in CPU at interruption
Reset signal is performed after reason operation to complete to reset；
CPU51, operate, and complete for execution interrupt processing after receiving the interrupt signal sent by programming device 50
Programming device 50 is notified after interrupt processing operation, wherein, interrupt processing is operated for appointing to the system for being currently not carried out finishing
Business carries out emergent management.
When processing of breaking in commission operates, CPU51 is specifically used for：
Signal out of service is sent to all processes；
By the data write storage device in caching.
Before sending signal out of service to all processes, send and notify to specified process, it is multiple to indicate that specified process performs
Emergent management operates before position.
CPU51 is further used for：
All processes are being sent with signal out of service, and by the data write storage device in caching and then it is secondary to
All processes, which are sent, forces signal out of service, and again by the data write storage device in caching.
CPU51 is further used for：
Before signal out of service is sent to all processes, interrupt processing is operated and performs locking operation.
In truth example of the present invention, programming device is FPGA or CPLD.
In summary, in the embodiment of the present invention, in being operated in the reset of circuit board, for being related to depositing on circuit board
The related data of storage equipment is protected, therefore ensures storage device normal work after obtaining circuit sheet reset, further really
Protect the technique effect of whole system normal work.
It should be understood by those skilled in the art that, embodiments of the invention can be provided as method, system or computer program
Product.Therefore, the present invention can use the reality in terms of complete hardware embodiment, complete software embodiment or combination software and hardware
Apply the form of example.Moreover, the present invention can use the computer for wherein including computer usable program code in one or more
The computer program production that usable storage medium is implemented on (including but is not limited to magnetic disk storage, CD-ROM, optical memory etc.)
The form of product.
The present invention is the flow with reference to method according to embodiments of the present invention, equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that can be by every first-class in computer program instructions implementation process figure and/or block diagram
Journey and/or the flow in square frame and flow chart and/or block diagram and/or the combination of square frame.These computer programs can be provided
The processors of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices is instructed to produce
A raw machine so that produced by the instruction of computer or the computing device of other programmable data processing devices for real
The device for the function of being specified in present one flow of flow chart or one square frame of multiple flows and/or block diagram or multiple square frames.
These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that the instruction being stored in the computer-readable memory, which produces, to be included referring to
Make the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one square frame of block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that counted
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented processing, so as in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then can make other change and modification to these embodiments.So appended claims be intended to be construed to include it is excellent
Select embodiment and fall into having altered and changing for the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification without departing from this hair to the embodiment of the present invention
The spirit and scope of bright embodiment.So, if these modifications and variations of the embodiment of the present invention belong to the claims in the present invention
And its within the scope of equivalent technologies, then the present invention is also intended to comprising including these changes and modification.
Claims (5)
- A kind of 1. method of safety reset storage device, it is characterised in that methods described includes：After programming device reception reset signal interrupt signal is sent to central processor CPU；CPU performs interrupt processing operation, and programming device is notified after interrupt processing operation is completed, the interrupt processing operation For carrying out emergent management to the system task for being currently not carried out finishing；After programming device receives the notice, perform the reset signal and complete to reset；Wherein, the interrupt processing operation includes：Send and notify to specified process, the instruction specified process execution is tight before resetting All processes are sent signal out of service, by the data write storage device in caching by anxious processing operation；To can not force to prohibit Process only sends notice, it is determined that when the process execution emergent management that can not force to forbid is operated successfully, to all processes Send and force signal out of service, by the data write storage device in caching.
- 2. the method as described in claim 1, it is characterised in that the interrupt processing operation also includes：Before signal out of service is sent to all processes, the interrupt processing is operated and performs locking operation.
- A kind of 3. device of safety reset storage device, it is characterised in that including programming device and central processor CPU, its In,Programming device, interrupt signal is sent to CPU after reset signal for receiving, and complete interrupt processing operation in CPU Reset signal is performed afterwards to complete to reset；CPU, operated for execution interrupt processing after receiving the interrupt signal sent by programming device, and complete interrupt processing Programming device is notified after operation, the interrupt processing operates promptly to be located for the system task to being currently not carried out finishing Reason；Wherein, the interrupt processing operation includes：Send and notify to specified process, the instruction specified process execution is tight before resetting All processes are sent signal out of service, by the data write storage device in caching by anxious processing operation；To can not force to prohibit Process only sends notice, it is determined that when the process execution emergent management that can not force to forbid is operated successfully, to all processes Send and force signal out of service, by the data write storage device in caching.
- 4. device as claimed in claim 3, it is characterised in that the CPU is further used for：Before signal out of service is sent to all processes, the interrupt processing is operated and performs locking operation.
- 5. device as claimed in claim 3, it is characterised in that the programming device be on-site programmable gate array FPGA or It is complex programmable logic device (CPLD).
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| CN201410539190.4A CN104317728B (en) | 2014-10-13 | 2014-10-13 | A kind of method and apparatus of safety reset storage device |
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| CN201410539190.4A CN104317728B (en) | 2014-10-13 | 2014-10-13 | A kind of method and apparatus of safety reset storage device |
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| CN104317728B true CN104317728B (en) | 2018-03-23 |
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| KR102020997B1 (en) * | 2016-09-21 | 2019-09-11 | 선전 구딕스 테크놀로지 컴퍼니, 리미티드 | Reset Method for Single-Chip and Single-Chip Computer Systems |
| CN113535441B (en) * | 2020-04-13 | 2023-01-31 | 烽火通信科技股份有限公司 | Embedded system fault diagnosis device and method |
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| CN1215865A (en) * | 1997-10-27 | 1999-05-05 | 摩托罗拉公司 | Circuit and method for retaining data in DRAM in portable electronic device |
| US6381680B1 (en) * | 1984-01-23 | 2002-04-30 | Hitachi, Ltd. | Data processing system with an enhanced cache memory control |
| CN1725706A (en) * | 2005-05-24 | 2006-01-25 | 杭州华为三康技术有限公司 | Reset processing method and device for system |
-
2014
- 2014-10-13 CN CN201410539190.4A patent/CN104317728B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6381680B1 (en) * | 1984-01-23 | 2002-04-30 | Hitachi, Ltd. | Data processing system with an enhanced cache memory control |
| CN1215865A (en) * | 1997-10-27 | 1999-05-05 | 摩托罗拉公司 | Circuit and method for retaining data in DRAM in portable electronic device |
| CN1725706A (en) * | 2005-05-24 | 2006-01-25 | 杭州华为三康技术有限公司 | Reset processing method and device for system |
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