CN104035904B

CN104035904B - FPGA-based interconnection device among chips

Info

Publication number: CN104035904B
Application number: CN201410315571.4A
Authority: CN
Inventors: 秦刚; 刘强; 孙大军; 李长志
Original assignee: Shandong Chaoyue Digital Control Electronic Co Ltd
Current assignee: Shandong Chaoyue CNC Electronics Co Ltd
Priority date: 2014-07-04
Filing date: 2014-07-04
Publication date: 2017-01-25
Anticipated expiration: 2034-07-04
Also published as: CN104035904A

Abstract

The invention relates to the technical field of chip interconnection, in particular to an FPGA-based interconnection device among chips. According to the FPGA-based interconnection device among the chips, a dynamic clock adjusting module, a low-voltage differential signal sending module and a low-voltage differential signal receiving module are arranged in each FPGA chip so that information transmission between the FPGA chips can be achieved. The interconnection device has the advantages of being adjustable in speed and high in flexibility.

Description

A kind of chip chamber interconnect device based on fpga

Technical field

The present invention relates to chip interconnection technique field, particularly to a kind of chip chamber interconnect device based on fpga.

Background technology

Fpga(field programmable gate array) chip is a kind of programmable logical device, it is short to have a construction cycle, reliable The high feature of property.

Its chip chamber be mutually associated with a lot of techniques available, lvds(low-voltage differential signaling Low Voltage Differential Signal) interface, there is the features such as low noise, low-power consumption, two-forty, low cost, be not too high in rate requirement In the case of (generally these chips do not have integrated serdes serializer), often as the interconnecting interface of chip chamber, existing Technology in be typically all not involved with that a kind of transmission data is reliable and transfer rate adjustable lvds interface.

Content of the invention

In order to solve problem of the prior art, the invention provides a kind of chip chamber interconnect device based on fpga, its tool There is speed adjustable, the high feature of flexibility.

The technical solution adopted in the present invention is as follows:

A kind of chip chamber interconnect device based on fpga, is that setting clock is dynamically adjusted in programmable gate array chip at the scene Mould preparation block, Low Voltage Differential Signal sending module, Low Voltage Differential Signal receiver module, wherein,

The timing parameter that the dynamic adjusting module of described clock will configure calculates, and is written to by Serial Peripheral Interface (SPI) In the dynamic replacement port module of field programmable gate array chip, the clock of field programmable gate array chip is adjusted with this Management module, the clock required for output；

Described Low Voltage Differential Signal sending module comprises to send First Input First Output module, framing module and parallel-serial conversion Module, described Low Voltage Differential Signal sending module receives the feedback signal of opposite end and processes to carry out flowing control；

Described Low Voltage Differential Signal receiver module comprises serioparallel exchange module, solution frame module and receipts First Input First Output mould Block, described Low Voltage Differential Signal receiver module sends to transmitting terminal and receives ready signal to carry out flowing control process.

Low Voltage Differential Signal sending module receive opposite end feedback signal come to carry out flow control process comprise the concrete steps that:

A, the ready signal of opposite end chip one data of transmission, when preparing receiving data to end module, send first to enter First dequeue module can be read once to send the data in First Input First Output module every the cycle of data bit width；

B, read data can be through framing module, according to header, data length, valid data and data check and bag The protocol format framing of tail；

C, from framing module data out after parallel serial conversion module, be converted into serial data and be sent to opposite end core Piece；

D, send data while, Low Voltage Differential Signal sending module can produce data synchronizing signal and make to opposite end chip It is easy to data syn-chronization during the receiving data of opposite end.

Low Voltage Differential Signal receiver module sends to transmitting terminal and receives ready signal to carry out flowing the concrete steps that control is processed It is:

A, Low Voltage Differential Signal receiver module synchronize to data according to the synchronizing signal that opposite end sends；

Data after b, synchronization is converted into parallel data through serioparallel exchange module；

C, process solution frame module extract valid data, and valid data are sent in reception First Input First Output module, Receive the storage threshold value that data is set in First Input First Output module, represent that receiving terminal is not yet ready for connecing after reaching threshold value Receive data, this signal back transmitting terminal can be made transmitting terminal stop sending valid data by Low Voltage Differential Signal receiver module, It is less than threshold value until receiving the data storage in First Input First Output module.

A kind of chip chamber interconnect device based on fpga of the present invention, is that setting clock dynamically adjusts mould in fpga chip Block, lvds sending module, lvds receiver module.

Cpu is by the spi(serial peripheral interface-- serial peripheral with fpga) interface dynamic configuration The interface clock rate of lvds, after the completion for the treatment of clock configuration, data is from transmission fifo(First Input First Output) write data, when right After end chip sends data receiver instruction, required for reading from fifo according to certain cycle, the data of transmission, data is pressed According to the protocol format framing of header, data length, valid data and data check and bag tail, by the Frame organized through simultaneously String modular converter is converted into serial data and is sent in the chip of opposite end；After opposite end chip receives data, send according to transmitting terminal The synchronizing signal coming over carries out data syn-chronization, carries out serioparallel exchange to serial data after synchronously completing, the data after serioparallel exchange Carry out solving frame through data solution frame module according to the good frame format of predefined, the data write out of solution frame receives in fifo, Certain storage threshold value is set in fifo, when the data of fifo storage reaches threshold value, a differential signal can be sent toward opposite end Tell and end data is not ready for, at this moment opposite end lvds sending module stopping transmission valid data prepare again until receiving terminal Good receiving data.

The speed of dynamic configuration lvds interface it is simply that wanting the clock of dynamic configuration lvds, the timing parameter meter that will configure Calculate, port dynamically reset by the drp(that spi interface is written to fpga) in module, the Clock management of fpga is adjusted with this Module, the clock required for output.

Technical scheme provided in an embodiment of the present invention has the benefit that

By a kind of chip chamber interconnect device based on fpga of the present invention, the information being capable of fpga chip chamber passes Pass, this device has that speed is adjustable, the high feature of flexibility.

Brief description

For the technical scheme being illustrated more clearly that in the embodiment of the present invention, will make to required in embodiment description below Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings Accompanying drawing.

Fig. 1 is a kind of structure block architecture diagram of chip chamber interconnect device based on fpga of the present invention.

Specific embodiment

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention Formula is described in further detail.

Embodiment one

As shown in Figure 1, a kind of chip chamber interconnect device based on fpga, in fpga chip, setting clock dynamically adjusts Module, lvds sending module, lvds receiver module.

The dynamic adjusting module of clock:

For realizing dynamically can joining of speed again, using dynamically can timing clock again scheme, pass through cpu and fpga phase outside The dynamic adjusting module of clock that the timing parameter again joined is sent in fpga by spi or iic interface even in real time, clock moves The clock of state adjusting module output is the clock of whole device.

Lvds sending module:

Opposite end chip can send the ready signal of data, and when preparing receiving data to end module, fifo can be every Read the data in a fifo every the cycle of data bit width, the data of reading can be through framing module, and according to packet header, data is long Degree, the protocol format framing of valid data and data check and bag tail, from framing module data out through parallel-serial conversion After module, it is converted into serial data and is sent to opposite end chip, while sending data, it is same that lvds sending module can produce data Step signal makes to be easy to data syn-chronization during the receiving data of opposite end to opposite end chip.

Lvds receiver module:

Receiver module synchronizes to data according to the synchronizing signal that opposite end sends, and the data after synchronization is through serioparallel exchange Module is converted into parallel data, extracts valid data through solution frame module, and valid data are sent in reception fifo, are receiving The storage threshold value of data is set in fifo, represents that receiving terminal is not yet ready for receiving data after reaching threshold value, lvds receives This signal back transmitting terminal can be made transmitting terminal stop transmission data storage in fifo for the valid data and be less than by module Threshold value.

The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and Within principle, any modification, equivalent substitution and improvement made etc., should be included within the scope of the present invention.

Claims

1. a kind of chip chamber interconnect device based on fpga, is that setting clock dynamically adjusts in programmable gate array chip at the scene Module, Low Voltage Differential Signal sending module and Low Voltage Differential Signal receiver module, wherein,

The timing parameter that the dynamic adjusting module of described clock will configure calculates, and is written to scene by Serial Peripheral Interface (SPI) In the dynamic replacement port module of programmable gate array chip, the Clock management of field programmable gate array chip is adjusted with this Module, the clock required for output；

Described Low Voltage Differential Signal sending module comprises to send First Input First Output module, framing module and parallel-serial conversion mould Block, described Low Voltage Differential Signal sending module receives the feedback signal of opposite end and processes to carry out flowing control；

Described Low Voltage Differential Signal receiver module comprises serioparallel exchange module, solution frame module and receives First Input First Output mould Block, described Low Voltage Differential Signal receiver module sends to transmitting terminal and receives ready signal to carry out flowing control process.

2. a kind of chip chamber interconnect device based on fpga according to claim 1 is it is characterised in that described low voltage difference Sub-signal sending module receive opposite end feedback signal come to carry out flow control process comprise the concrete steps that:

A, the ready signal of opposite end chip one data of transmission, when preparing receiving data to end module, send FIFO Queue module can be read once to send the data in First Input First Output module every the cycle of data bit width；

B, the data reading can be through framing modules, according to header, data length, valid data and data check and bag tail Protocol format framing；

C, from framing module data out after parallel serial conversion module, be converted into serial data and be sent to opposite end chip；

D, send data while, Low Voltage Differential Signal sending module can produce data synchronizing signal and make opposite end to opposite end chip It is easy to data syn-chronization during receiving data.

3. a kind of chip chamber interconnect device based on fpga according to claim 1 is it is characterised in that described low voltage difference Sub-signal receiver module to transmitting terminal send receive ready signal to carry out flow control process comprise the concrete steps that:

C, process solution frame module extract valid data, and valid data are sent in reception First Input First Output module, are receiving The storage threshold value of data is set in First Input First Output module, represents that receiving terminal is not yet ready for receiving number after reaching threshold value According to, this signal back transmitting terminal can be made transmitting terminal stop sending valid data by Low Voltage Differential Signal receiver module, until The data storage receiving in First Input First Output module is less than threshold value.