CN104022758B - A kind of band resets the power consumption equilibrium trigger of set port - Google Patents

Abstract

A kind of band resets the power consumption equilibrium trigger of set port, including by prime latch module connected in series, intermediate circuit and rear class latch module；Prime latch module and rear class latch module all use the dynamic difference circuit of single clock control；Intermediate circuit includes middle independent set module, data isolation module and data memory module, middle independent set module carries out initial state setting by independent set signal to trigger, data isolation module include two groups of clock transmission gates to isolate evaluation signal and set signal, data memory module includes that pair of cross coupled inverters is to carry out data storage；At clock first half cycle, prime latch module carries out evaluation, rear class latch module carries out pre-charge state；In the clock later half cycle, prime latch module carries out pre-charge state, rear class latch module carries out evaluation output.The present invention has the advantages such as power consumption harmony is good, area overhead is little, performance is higher, sequencing contro is simple.

Description

A kind of band resets the power consumption equilibrium trigger of set port

Technical field

The present invention relates to IC design field, be specifically related to a kind of power consumption resetting set port for anti-power consumption attack equal Weighing apparatus trigger.

Background technology

The level of informatization is promoted to improve constantly along with computer network, microelectronics and related science technology develop rapidly, information Safety becomes the topic that all trades and professions are paid close attention to most.Therefore being encrypted important information to become protects information security the most direct Method, in recent years along with the development of integrated circuit, crypto chip is good with its closure, crack difficulty big, crack difficulty High feature is used for realizing information encryption by numerous industries.But being as the fast development of microelectronic industry, crypto chip bypass is attacked Hitting technology (Side-Channel Leakage) and become the threat that crypto chip is maximum, Fig. 1 is that bypass attack implements schematic diagram, Understand crypto chip according to diagram and can produce substantial amounts of bypass message when being encrypted computing (such as the power consumption of leakage, electricity during encryption Magnetic radiation and operation time etc.), therefore assailant can pass through sample bypass information and carry out mass data statistical analysis, can have The enforcement cipher key attacks of effect.In numerous crypto chip bypass attacks, attack efficiency is high, intrusion scene is low, in fact with it for power consumption attack Execute difficulty to be relatively easier to the most slowly become the attack means that attack crypto chip is the most frequently used.As shown in Fig. 2 a, Fig. 2 b, with instead The generation source of power consumption in circuit, owing to the mobility of hole and electronics has difference, therefore phase inverter PMOS are described as a example by phase device Managing different with the width of NMOS tube, drain capacitance is the most different, and formula (1) is counting circuit dynamic power consumption equation；Formula (2) For load capacitance C_LProduced energy within the unit interval.

P_dyn=C_LVDD²f_0→1 (1)

$E_{\mathrm{VDD}}={\∫}_0^{\∞}{i}_{\mathrm{vdd}}{\left(t\right)}^{*}{\mathrm{VDDd}}_t=C_t*\mathrm{VDD}{\∫}_0^{\mathrm{vdd}}{d}_{\mathrm{vout}}=C_L{\mathrm{VDD}}^2---\left(2\right)$

Understand when load capacitance C according to formula (2)_LWhen being charged by PMOS, output voltage rises to VDD from 0, now Certain energy is drawn from power supply.A part for this energy is with form of thermal energy consumption in PMOS, and remaining just leaves load in In electric capacity.When there is the saltus step of 0-1 in input signal, load capacitance C_LOn electric charge will be let go, wherein another part is also It is consumed with the form of heat energy.For the angle that electric charge moves, no matter at charging stage or discharge regime, each is opened The pass cycle, (by height on earth or from low to high) was required for the energy i.e. C of a fixed qty_LVDD², and necessary in real work Consider the switching frequency f of device_0→1(representing catabiotic toggle frequency).Dynamic power consumption is affected by (1) formula can be seen that Factor in addition to node capacitor, supply voltage also have input signal toggle frequency.The switch activity of one circuit is with defeated The essence and the statistical property that enter signal are relevant, if input signal keeps constant, then any switch will not occur, the most dynamically Power consumption is zero, otherwise the signal of velocity variations can cause multiple switching and power consumption.Thereby ensure that all produce under any different input change Raw identical power consumption becomes the core concept of power consumption logic of Equilibrium design.

At present, dynamic double track precharge structure is used to be implemented as the main body in order to design in the logical design of power consumption equilibrium trigger Thought, the power consumption equilibrium trigger that present stage proposes mainly includes SDDL FF, MSDDL FF, TDPL, as shown in Figure 3. SDDL FF (Single Dynamic Different Logic flip-flop) is made up of two common d type flip flops and two nor gates, The input of two of which d type flip flop is Differential Input, and nor gate input is control signal and d type flip flop outfan, or non- Door mainly completes the generation work of combinational circuit precharging signal.When control signal each cycle carries out saltus step, nor gate all can present Going out to be pre-charged to the change of evaluation, and the input of nor gate, outfan are all differential signal, therefore nor gate each cycle consumes Power consumption be just as.But d type flip flop can not show power consumption equalization characteristic, owing to control signal can not make trigger Each cycle all carries out being pre-charged to the change of evaluation, thus when d type flip flop input be 0 to 1 change (transitional states) and 0 to 0 change time (hold mode) power consumption of being consumed be different.As shown in Figure 4, for SDDL four kinds of inputs By analysis, electric current matching waveform under Bian Hua, can be seen that current waveform has notable difference, therefore SDDL FF can not realize Power consumption equalizes.MSDDL FF (Master-Slave Dynamic Different Logic flip-flop) uses and is touched by 4 common D Sending out device to cascade two-by-two, constitute pipeline organization, precharge controls the logical design input at MSDDL, such preliminary filling telecommunications Number and evaluation signal can replace in two pairs of triggers propagate so that each trigger can periodically complete precharge and ask Value Operations, therefore MSDDL FF can arrive preferable power consumption harmony.But cascade two-by-two due to 4 d type flip flops so Input signal could export through two all after dates, so control signal to carry out frequency dividing could meet the work shape of MSDDL State, this causes greater loss to aspect of performance, and MSDDL has bigger area overhead simultaneously.TDPL as shown in Figure 6 (three-phase dual-rail pre-charge logic) realizes have employed three stage structure, and prime, late-class circuit use identical dynamic State difference channel structure, but TDPL forward and backward level dynamic difference structure needs to realize circuit function by three control signals, as Shown in Fig. 5.This make the inclusion relation between control signal more complicated and also in dynamic logic designs the signal packet of this complexity Bigger short circuit current can be produced containing relation thus cause serious power consumption to reveal.The data holding circuit of TDPL uses NAND gate S-R latch, according to Fig. 2, owing to static NAND gate circuit structure there are differences itself, outfan is producing logical one The transistor size turned on time " 0 " all differences therefore produced power consumption also has larger difference, so TDPL cannot be real Now preferably power consumption is harmonious.Table 1 is that existing power consumption equalizes trigger comparison in terms of area, performance, power consumption.

In sum, although but SDDL FF has advantage in terms of area cannot accomplish that power consumption equalizes；Although MSDDL FF Preferable power consumption can be reached harmonious, however it is necessary that and realize with 4 standard static triggers are connected in series, performance is relatively low, Area overhead is too big, does not have advantage in Project Realization；Although TDPL uses syllogic to achieve precharge and evaluation parallel Operation, but the prime of TDPL, rear class dynamic difference circuit sequence control complicated and intermediate data storage circuit employing NAND gate S-R latch structure, itself there are differences, so outfan exists seeing as static NAND gate circuit structure according to described in Fig. 2 Produce power consumption produced by logical one and " 0 " and there is larger difference, when carrying out the cryptographic calculation of multicycle by this body structure Produced power consumption difference will be exaggerated this and have lethal challenge to crypto chip, and owing to NAND gate itself exists the sky of structure So defect cannot realize the equilibrium of preferable power consumption, and more complicated this of sequencing contro of TDPL also has bigger difficulty to global design.

Summary of the invention

The technical problem to be solved in the present invention is that, the technical problem existed for prior art, and the present invention provides a kind of power consumption Harmony is good, area overhead is little, performance is higher, the power consumption equilibrium trigger of sequencing contro simple band clearing set port.

A kind of band resets the power consumption equilibrium trigger of set port, including by prime latch module connected in series, intermediate circuit And rear class latch module, three modules are all using differential signal as input, generation difference output；Described prime latch module and after Level latch module all uses the dynamic difference circuit of single clock control；Described intermediate circuit includes middle independent set module, number According to isolation module and data memory module, the independent set in described centre module carries out initial state by independent set signal to trigger Arrange, described data isolation module include two groups of clock transmission gates to isolate evaluation signal and set signal, described data storage mould Block includes that pair of cross coupled inverters is to carry out data storage；At clock first half cycle, described prime latch module carry out evaluation, Rear class latch module carries out pre-charge state；In the clock later half cycle, described prime latch module carries out pre-charge state, rear class Latch module carries out evaluation output, it is achieved the parallel work-flow of three modules within a cycle.

As a further improvement on the present invention: described prime latch module and rear class latch module all use SABL dynamic difference to tie Structure and there is data latch function.

As a further improvement on the present invention: described centre independent set module includes the PMOS realizing set function With a NMOS and be used for realizing the phase inverter with single-ended control signal of data inversion function.

Compared with prior art, it is an advantage of the current invention that:

1, the present invention is capable of working with clock cycle same frequency, improves flip-flop operation performance.

2, the power consumption equilibrium trigger of the present invention has distinctive set function.

3, in the present invention, prime latches, rear class latches, intermediate circuit all uses symmetric difference circuit structure, and all modules are all For Differential Input, difference output, therefore the power consumption of this trigger is harmonious more preferably.

4, the trigger of the present invention has that power consumption is harmonious preferably, area overhead is less, performance is higher, trigger controls simpler Advantage.

Accompanying drawing explanation

Fig. 1 is the principle schematic that in prior art, bypass attack is implemented.

Fig. 2 is the principle schematic that in prior art, phase inverter power consumption produces；Wherein, Fig. 2 (a) is that outfan occurs 0-1 to become Schematic diagram during change；Fig. 2 (b) is schematic diagram during outfan generation 1-0 change.

Fig. 3 is SDDL FF and the electrical block diagram of MSDDL FF in prior art.

Fig. 4 is SDDL FF trigger electric current matching schematic diagram under four kinds of input changes in prior art.

Fig. 5 is the schematic diagram of TDPL forward and backward level circuit structure in prior art.

Fig. 6 is the structural representation of TDPL circuit in prior art.

Fig. 7 is the structural representation of prime in the present invention, late-class circuit.

Fig. 8 is the working state schematic representation of prime in the present invention, late-class circuit.

Fig. 9 is forward and backward level latch module electric current matching waveform diagram under two kinds of input changes in the present invention.

Figure 10 is the electrical block diagram of independent set module in the present invention.

Figure 11 is independent set module set signal and clock signal restriction relation schematic diagram in the present invention.

Figure 12 is the structural representation of the present invention.

Figure 13 is internal node operation principle schematic diagram in the present invention.

Figure 14 is the electric current matching waveform diagram that the present invention produces under four kinds of different input changes.

Detailed description of the invention

Below with reference to Figure of description and specific embodiment, the present invention is described in further details.

As shown in figure 12, a kind of band of the present invention resets the power consumption equilibrium trigger (abbreviation: TSSDDL FF is i.e. of set port Three-step Separate Set Dynamic Different Logic flip-flop), use three stage structure, including by serial even Prime latch module, intermediate circuit and the rear class latch module connect, three modules are all using differential signal as input, generation difference Output, therefore total power consumption produced by each cycle trigger is the same；Prime latch module and rear class latch module all use same A kind of difference channel structure, intermediate circuit includes middle independent set module, data isolation module and data memory module, three Full symmetric circuit structure is all used to realize.Middle independent set module carries out initial state by independent set signal to trigger and sets Putting, data isolation module uses two groups of clock transmission gates to isolate evaluation signal and set signal, and data memory module uses a pair The cross coupling inverter of minimum dimension realizes data storage.The power consumption equilibrium trigger of the present invention realized a clock cycle Precharge and the parallel work-flow of evaluation, at clock first half cycle, prime latch module carries out evaluation, rear class latch module carries out pre- Charging produces (0.0) state；In the clock later half cycle, prime latch module carries out being pre-charged (0.0) state, rear class latches mould Block carries out evaluation output, thus the parallel work-flow of three modules in realizing a cycle.

In the present embodiment, prime latch module, rear class latch module all use SABL dynamic difference structure to equalize to realize power consumption, And circuit has data latch function.

In the present embodiment, middle independent set module uses an a PMOS and NMOS to realize set function, data inversion Function uses the phase inverter with single-ended control signal to realize.

In other words, when specifically applying, in order to not reduce the operating frequency of encrypted circuit, trigger of the present invention be designed with three Level circuit realiration.First order circuit and tertiary circuit (prime latch module and rear class latch module) are all by a dynamic latch Module composition, difference is that first order phase inverter is to be controlled by the original signal of clock, and the third level is controlled by the inverted signal of clock.In Between circuit include set module, the transmission gate of two trailing edge conductings and the cross-linked feedback that two special circuits are constituted Loop, wherein RESET_MOD1 realizes the function of NOR；RESET_MOD2 realizes the function of NAND.When set is believed Time number effective, middle independent set module carries out initialization operation to trigger and makes outfan unrelated with D and Dn, two The transmission gate that clock falling edge is opened is used for propagating in the past clock at trailing edge in the data that CP is high level holding, and leads to Data are stored by the feedback circuit crossing a low level conducting.The duty of this trigger is mainly by clock CLK and set Two signals of signal reset control.

As it is shown in fig. 7, in the present embodiment, prime latch module, rear class latch module all can use SABL (Sense Amplifier Based Logic) realization of dynamic difference circuit structure.Input signal X and Xn are differential input signal, and Q, Qn are that difference is defeated Going out signal, this circuit has a three below feature:

(1) in gate uses dynamic operation mode, each cycle, circuit is pre-charged and evaluation operation.Circuit structure In between net1 and net2 connect a NMOS tube, the most whole circuit precharge and evaluation can accomplish fully charged Discharge completely.

(2) due to the existence of n6 pipe, in the evaluation stage, circuit samples after data enter high level defeated at rising edge clock Go out end to be changed by any change of input, thus reach data latch function.

(3) in circuit, cross-linked phase inverter is used for producing one group of difference output between high period.

Circuit working state is divided into two stages: be pre-charged (Pre_charge) and evaluation (evalue), in pre-charging stage CLK For low level, by P3, P0, electric capacity C1 and C2 is charged to VDD so that outfan Q, Qn are low level, from And meet the working method of double track precharge logical.Output signal is determined according to the value of input signal X, Xn in the evaluation stage. Transistor n6 realizes discharging two electric capacity C1 and C2 in the evaluation stage and reaches the total power consumption equilibrium of circuit.By n0, The pair of cross coupled inverters of n1, p1, p2 composition is used for keeping output data.

As shown in Figure 8, for the circuit fundamental diagram of prime latch module, rear class latch module in the present embodiment, Xn=1 is worked as Node relationships time within, when CLK is low level, net3, net4 be all pre-charged to VDD make export Q and Qn be (0.0), owing to being that between low period, the grid of n0 and n1 and drain electrode are all VDD at CLK, in order to meet transistor work Condition V in saturation region_DS＞ V_GS-V_th, so the node level of net1 and net2 is not up to the full amplitude of oscillation.When CLK is high electricity Flat period circuit is in evaluation discharge regime, it is assumed that during dual-rail output signal X=0, Xn=1, electric capacity C2 carries out electric discharge and makes Q end defeated Going out is 1, owing to the existence electric capacity C1 of n6 pipe can be discharged to GND through n0, n6, n3 and n4, so being high at CLK Level period net1 and net2 can be in 0 current potential.When net1 and net2 is 0 current potential, the change of input is to outfan Do not result in impact, therefore make net3 jump to 1 current potential and make Qn when C2 is 0 by cross-linked phase inverter The jump in potential of end is to 0, and at this moment any change of input is all without affecting the result of outfan, thus is high level at CLK Period keeps data stabilization, can be clearly seen that input and the inverted relationship of output and have between high period from sequential chart Data are had to keep function.Owing between clock high period, outfan has data holding function, meet as long as making to input data Certain sets up the time, and single dynamic latch module also has the function that data latch.

As it is shown in figure 9, be dynamic latch module produced electric current matching ripple under two kinds of different inputs employed in the present embodiment Shape, in can be seen that same time period by waveform, two kinds of current waveforms are almost completely superposed, therefore in the case of explanation two kinds dynamically The power consumption that latch module produces is identical.

As shown in Figure 10 and Figure 11, in the present embodiment, the independent set logic of middle independent set module uses independent reset control End processed realizes, and in Figure 10, RESET_MOD1 realizes NOR function, RESET_MOD2 realizes NAND function, puts Position logic is realized by a NMOS and a PMOS.When set signal reset is high, module is in set shape State, prime input can be isolated with outfan, therefore export Q and Qn and be always maintained at difference output by clock phase inverter.When When reset is low, set signal turns off and clock phase inverter turning circuit is in normal evaluation state.Meanwhile, reset becomes from set Certain constraints is there is with clock signal to during evaluation state.According to Fig. 8 to prime latch module, rear class latch module work Making the description of principle, input signal must before rising edge clock effectively, as long as and evaluation state ensures that set signal is in standard It is in disarmed state before the standby rising edge clock carrying out evaluation.Give reset signal and clock signal as shown in Figure 10 The setup time-constrain that should meet, table 2 is the truth table of independent set logic.

A	An	reset	reset_n	Q	Qn
						x	x	1	0	0	1
0	1	0	1	1	0
						1	0	0	1	0	1

Can be seen that two modules of RESET_MOD1, RESET_MOD2 use single MOS except set logic by analysis Realizing, remaining structure is full symmetric.Owing in actual encryption algorithm, trigger SM set mode simply carries out initial state to trigger And setting time is relatively short, therefore the power consumption difference in NMOS tube produced by SM set mode and PMOS can't be made Serious power consumption is become to reveal.When independent set module is in evaluation scheme, RESET_MOD1, RESET_MOD2 are for the most right The circuit structure claimed, therefore two modules of evaluation stage are substantially equally in total power consumption produced by each cycle.

As shown in figure 13, for the operation principle schematic diagram of TSSDDL FF of the present invention, a complete job of TSSDDL FF State can be divided into two stages, and the first stage is pre-charging stage；Second stage is the evaluation stage.Pre-charging stage CP1=1, CPn=0, prime latch module enters the evaluation stage and rear class latch module is pre-charging stage, therefore exports in pre-charging stage End can produce full 0 signal.At this moment the result that prime latch module can sample input is transferred to net_c and net_d (preliminary filling The electricity stage)；As it is shown in fig. 7, the description to prime latch module, rear class latch module understands, data have after carrying out evaluation The function that data latch, therefore at CP1=1, during CPn=0, prime latch module is in data and keeps the stage.

Trigger can be by the data of prime latch module by clock falling edge (CP1=1 in entering evaluation phase process；CPn=0) The transmission gate opened travels to net_c and net_d, then by feedback circuit (CP1=0；CPn=1) latch by data. At this moment prime latch module enters again pre-charging stage and transmission gate turns off and any change of input D and Dn will not be brushed The data that new feedback latches, the rear class latch module that CPn controls simultaneously enters the evaluation stage (CP1=0, CPn=1) and is adopted The signal of sample is net_c and 2 signals kept of net_d.

Trigger set function judges according to reset signal, works as reset1=1, reset_n=0；Set module can persistently export (1.0) Signal, works as reset1=0, and during reset_n=1, set module enters evaluation scheme.

According to above-mentioned analysis, the trigger of the present invention within a clock cycle before half clock cycle, rear class carries out pre- Charge in order to produce full 0 signal and prime carries out sampling and data being latched；In second half of the cycle, prime carries out again pre- Charging is used for carrying out discharge and recharge next time and rear class is in the evaluation stage, the output signal of rear class latch module according to net_c and The current potential of net_d point is changed.Therefore, the trigger of the present invention will can be pre-charged and evaluation two within a clock cycle Stage pipeline operates without carrying out frequency multiplication.

As shown in figure 13, in figure, F (Front) represents prime latch module, and B (Back) represents rear class latch module.Pass through Upper figure can show that the result of trigger outfan when set signal is effective and input are incoherent, the fixing output of outfan (0.1).When, after set invalidating signal, prime latch module carries out sampling and rear class latch module is in precharge, so output End Q and Qn keeps (0.0) pre-charge state within the cycle of F_eval, B_prec.In the clock falling edge moment, pass through The data dissemination that prime is kept by transfer tube is to the input of rear class latch module, and therefore in Figure 12, the data of relatively extreme deficiency syndrome wire frame are front The sampled result of level.Within the cycle of F_prec, B_eval, prime latch module is that pre-charge state is output as (0.0), so The node voltage of net_a is 0；The node voltage of net_b is 1.By foregoing description, the power consumption equilibrium of the present embodiment design triggers Device achieves precharge and two operating process of evaluation within a complete clock cycle, and no matter input signal is in saltus step The inside level of state or hold mode trigger is all differential state, thus reaches power consumption equilibrium purpose.

In the present embodiment, experimental situation uses Hspice to be simulated, and the clock cycle is 1ns, and CMOS technology is 65nm, temperature Degree is 125 degree, and supply voltage is 1.2v；And all spice_modle is to be simulated in the case of SS.Data pass through mould Intend 100 ns and feature simulation 0-1 saltus step, 1-0 saltus step, 0-0 saltus step and 1-1 saltus step these four according to trigger input Situation, as shown in figure 14, carries out precharge and the current waveform of evaluation operation for TLSSDDL of the present invention in same period.

In sum, present invention utilizes three stage structure and realize precharge and the parallel work-flow of evaluation, but prime in the present invention, Rear class latch module only needs single clock to be controlled, and therefore the circuit structure prime relative to TDPL, post-module are simpler. Meanwhile, the present invention with the addition of to trigger set function, and intermediate circuit uses symmetrical structure to realize completely, so triggers Device does not results in the leakage of any power consumption difference in the evaluation stage.See electric current under four kinds of different input conditions given by Figure 14 to intend Close waveform, it can be seen that in precharge and the almost matching completely of four kinds of waveforms of evaluation stage.

Below being only the preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-described embodiment, all belongs to Technical scheme under thinking of the present invention belongs to protection scope of the present invention.It should be pointed out that, the ordinary skill for the art For personnel, some improvements and modifications without departing from the principles of the present invention, should be regarded as protection scope of the present invention.

Claims (3)

1. the power consumption equilibrium trigger of a band clearing set port, it is characterised in that include prime latch module, intermediate circuit and rear class latch module, by connected in series between three modules, three modules are all using differential signal as input, generation difference output；Described prime latch module and rear class latch module all use the dynamic difference circuit of single clock control；Described intermediate circuit includes middle independent set module, data isolation module and data memory module, the independent set in described centre module carries out initial state setting by independent set signal to trigger, described data isolation module include two groups of clock transmission gates to isolate evaluation signal and set signal, described data memory module includes that pair of cross coupled inverters is to carry out data storage；At clock first half cycle, described prime latch module carries out evaluation, rear class latch module carries out pre-charge state；In the clock later half cycle, described prime latch module carries out pre-charge state, rear class latch module carries out evaluation output, it is achieved the parallel work-flow of three modules within a cycle.

Band the most according to claim 1 resets the power consumption equilibrium trigger of set port, it is characterised in that described prime latch module and rear class latch module all use SABL dynamic difference structure and have data latch function.

Band the most according to claim 1 resets the power consumption equilibrium trigger of set port, it is characterized in that, a PMOS that described centre independent set module includes realizing a set function and NMOS and for realizing the phase inverter with single-ended control signal of data inversion function.