CN112597720B - Method and device for collecting power consumption data - Google Patents
Method and device for collecting power consumption data Download PDFInfo
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- CN112597720B CN112597720B CN202011587142.4A CN202011587142A CN112597720B CN 112597720 B CN112597720 B CN 112597720B CN 202011587142 A CN202011587142 A CN 202011587142A CN 112597720 B CN112597720 B CN 112597720B
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Abstract
The embodiment of the application discloses a method and a device for collecting power consumption data, relates to the technical field of integrated circuits, and aims to improve the accuracy of power consumption analysis of an upper-layer circuit. The method comprises the following steps: respectively collecting dynamic power consumption of each input signal on an internal logic chain of a target module in the target module; the logic chain comprises independent logic chains and common logic chains, wherein each independent logic chain corresponds to one path of input signals, and each common logic chain is related to at least two paths of different input signals; the dynamic power consumption includes: a first power consumption caused by each input signal jumping on the corresponding independent logic chain and a second power consumption caused by each input signal jumping on the corresponding common logic chain; and correcting the second power consumption according to the logic relation among all the input signals related to the common logic chain to obtain third power consumption corresponding to the input signals. The application is applicable to integrated circuit design.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for collecting power consumption data.
Background
In a complex system-on-chip design, analysis of power consumption is very important. Based on the design scale of the system-on-chip, it is not realistic to extract the parasitic parameters of the whole to obtain the power consumption data. Usually, a plurality of sub-modules are divided according to module functions, power consumption analysis is performed on each sub-module, and finally each sub-module provides respective power consumption data according to a liberty format. When the system level chip performs power consumption analysis, the power consumption of each submodule is analyzed corresponding to different application scenes, and then the power consumption is added to obtain the total power consumption. The accuracy of the power consumption data of each sub-module is crucial.
However, in a sub-module (target module), the internal logic of an input signal is often very complex, and basically, the input signal has mutually crossing logic and a common path, the power consumption data of each input signal obtained based on the above method is inconsistent with the power consumption of a module corresponding to an upper layer circuit in an actual application scenario, and the power consumption data of each input signal obtained based on the above method is written into a power consumption file, so that the accuracy of the power consumption data in the power consumption file is low, and thus, the accuracy of the power consumption analysis of the upper layer circuit is low when the upper layer circuit performs the power consumption analysis according to the power consumption data in the power consumption file.
Disclosure of Invention
In view of this, embodiments of the present application provide a method and an apparatus for collecting power consumption data, which are convenient to improve accuracy of performing power consumption analysis on an upper layer circuit.
In a first aspect, an embodiment of the present application provides a method for collecting power consumption data, including: respectively collecting dynamic power consumption of each input signal on an internal logic chain of a target module in the target module; the logic chain comprises independent logic chains and common logic chains, wherein each independent logic chain corresponds to one path of input signals, and each common logic chain is related to at least two paths of different input signals; the dynamic power consumption includes: a first power consumption caused by each input signal jumping on the corresponding independent logic chain and a second power consumption caused by each input signal jumping on the corresponding common logic chain; and correcting the second power consumption according to the logic relation among all the input signals related to the common logic chain to obtain third power consumption corresponding to the input signals.
According to a specific implementation manner of the embodiment of the present application, after the second power consumption is corrected according to a logical relationship between the input signals related to the common logic chain and a third power consumption corresponding to the input signal is obtained, the method further includes: and writing the logic chain division rule, the first power consumption and the third power consumption of the target module into a power consumption file so as to analyze the power consumption of the target module and an upper circuit system thereof by using the power consumption file.
According to a specific implementation manner of the embodiment of the application, after the logic chain division rule, the first power consumption and the third power consumption of the target module are written into a power consumption file, the method further includes: sequentially utilizing the combination of a plurality of groups of input signals to carry out circuit integral simulation on the target module to obtain the circuit simulation power consumption of the target module; calculating mathematical calculation power consumption of the target module under the combination of each group of the input signals in sequence by using the power consumption file; and correcting the logic chain division rule of the target module according to the difference between the circuit simulation power consumption corresponding to each group of input signals and the mathematical calculation power consumption.
According to a specific implementation manner of the embodiment of the present application, sequentially utilizing combinations of multiple groups of input signals to simulate the target module, obtaining the circuit simulation power consumption of the target module includes: writing an input excitation file by using a Verilog language, wherein the input excitation file comprises a plurality of groups of combinations of the input signals; compiling the input excitation file by using a Verilog compiler to obtain a corresponding numerical value vector file; and loading the numerical vector file by using a simulation tool, and simulating the target module to obtain the circuit simulation power consumption of the target module.
According to a specific implementation manner of the embodiment of the application, sequentially calculating, by using the power consumption file, the mathematically-calculated power consumption of the target module under the combination of each group of the input signals includes: writing a power consumption excitation file by using a Verilog language, wherein the power consumption excitation file comprises a plurality of groups of combinations of the input signals; and searching the power consumption of the working mode of the target module, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump and the logic relation among the input signals, and the static power consumption of the target module in the power consumption file according to the combination of each group of input signals in the power consumption excitation file to calculate the total power consumption.
In a second aspect, an embodiment of the present application provides an apparatus for collecting power consumption data, including: the dynamic power consumption collection module is used for respectively collecting the dynamic power consumption of each input signal in the target module on the internal logic chain of the target module; the logic chain comprises independent logic chains and common logic chains, wherein each independent logic chain corresponds to one path of input signals, and each common logic chain is related to at least two paths of different input signals; the dynamic power consumption includes: a first power consumption caused by each input signal jumping on the corresponding independent logic chain and a second power consumption caused by each input signal jumping on the corresponding common logic chain;
and the correcting module is used for correcting the second power consumption according to the logic relation among all the input signals related to the common logic chain to obtain third power consumption corresponding to the input signals.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: and the writing module is used for writing the logic chain division rule of the target module, the first power consumption and the third power consumption into a power consumption file so as to analyze the power consumption of the target module and an upper circuit system thereof by utilizing the power consumption file.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: the circuit simulation power consumption module is used for sequentially utilizing the combination of a plurality of groups of input signals to carry out circuit overall simulation on the target module so as to obtain the circuit simulation power consumption of the target module; the mathematical calculation power consumption module is used for sequentially calculating the mathematical calculation power consumption of the target module under the combination of each group of the input signals by using the power consumption file; and the correction module is used for correcting the logic chain division rule of the target module according to the difference between the circuit simulation power consumption corresponding to each group of input signals and the mathematical calculation power consumption.
According to a specific implementation manner of the embodiment of the present application, the circuit emulation power consumption module includes: the compiling submodule is used for compiling an input excitation file by utilizing a Verilog language, and the input excitation file comprises a plurality of groups of combinations of the input signals; the compiling submodule is used for compiling the input excitation file by using a Verilog compiler to obtain a corresponding numerical vector file; and the circuit simulation power consumption submodule is used for loading the numerical vector file by using a simulation tool, simulating the target module and obtaining the circuit simulation power consumption of the target module.
According to a specific implementation manner of the embodiment of the present application, the mathematical computation power consumption module includes: the compiling submodule is used for compiling a power consumption incentive file by utilizing a Verilog language, and the power consumption incentive file comprises a plurality of groups of combinations of the input signals; and the total power consumption calculation submodule is used for searching the power consumption of the working mode of the target module, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump and the logic relationship among the input signals in the power consumption file and the static power consumption of the target module according to the combination of each group of input signals in the power consumption excitation file, and calculating the total power consumption.
According to the method and the device for collecting power consumption data, dynamic power consumption of each input signal on an internal logic chain of a target module in the target module is collected respectively; the logic chain comprises independent logic chains and common logic chains, each independent logic chain corresponds to one path of input signals, each common logic chain is related to at least two paths of different input signals, and the dynamic power consumption comprises the following steps: the method comprises the steps of generating a common logic chain, generating a first power consumption and a second power consumption, wherein the first power consumption is caused by each path of input signals jumping on the corresponding independent logic chain, the second power consumption is caused by each path of input signals jumping on the corresponding common logic chain, the second power consumption is corrected according to the logic relation between the paths of input signals related to the common logic chain, and the third power consumption corresponding to the input signals is obtained.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of sub-module partitioning;
FIG. 2 is a simple logic path diagram;
fig. 3 is a schematic flowchart of a method for collecting power consumption data according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a power consumption data collection method according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a power consumption data collection method according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a power consumption data collection apparatus according to an embodiment of the present application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the early module power consumption documents, power consumption data was simply listed for several modes of operation, which were only related to the module enable signal and clock signal edges, with other signals jumping in a particular manner. The use of such power consumption data is greatly limited. When the upper module analyzes, signals except the enable signal and the clock edge signal are not consistent with the state of the submodule when collecting power consumption data, and an error is formed. Especially, the application scenarios of the sub-modules are different, the jump states of the signals are very many, and accurate power consumption data cannot be obtained for each kind of the signals.
Fig. 1 is a schematic diagram of sub-module division, and when power consumption data of a sub-module is collected, the sub-module is divided into 3 parts, namely an input latch decoding combinational logic part, an internal timing control part and a data output part, according to a power consumption division method. The logic inside the input latch decoding combination logic part is very complex, and basically, the logic and the common path are mutually crossed. In the prior art, the power consumption collection of the input latch decoding combinational logic part is mainly to make one path of input signals jump and keep other paths of input signals unchanged, so as to simulate the power consumption caused by the path of input signals. After simulating the power consumption caused by each input signal, the power consumption data can be written into a power consumption file (such as a liberty format). The power consumption analysis can be performed on the application of the power consumption data in the upper-layer circuit system according to the power consumption data recorded in the power consumption file and the specific input signal combination condition in the circuit.
When the power consumption of the input latch decoding combinational logic part is collected, one path of input signals jumps while the other paths of input signals are kept unchanged, and the power consumption caused by the path of input signals is simulated. After power consumption caused by each path of input signals is simulated, power consumption data can be written into a power consumption file. When the power consumption of the circuit is analyzed, the corresponding power consumption can be added according to the power consumption data recorded in the power consumption file and the specific input signal combination condition in the circuit.
However, in sub-modules, the logic within the input signal is often very complex, essentially having inter-crossing logic and common paths.
Fig. 2 is a simple logic path diagram in which the input block has only 2 signal inputs, signals A1 and B1, in addition to the clock, with logic and common paths that cross each other inside the input block. In collecting power consumption data of the input signal A1, when CLK =0, the signal A1 jumps (0 becomes 1, or 1 becomes 0), and when the other signals are stationary, power consumption by the IP is consumed. Similarly, the power consumption data for the signal B1 is the power consumption consumed by the IP when the signal A1 makes a transition (0 becomes 1, or 1 becomes 0) when CLK =0 and the other signals are stationary. Because the signal A1 and the signal B1 have mutual logic at an input module and have a common path, the power consumption when the A1 and the B1 jump simultaneously is not equal to the power consumption of the A1 plus the power consumption of the B1, and an error exists.
First error: when the power consumption of the signal A1 is collected, the signal B1 is maintained to be 0, the output of ND2 is always unchanged, no power consumption exists on a Pc path, and the total power consumption is the power consumption of a logic chain Pa. When the power consumption of the signal B1 is collected, the signal A1 is maintained to be 0, the output of ND2 is always unchanged, no power consumption exists on the Pc path, and the total power consumption is the power consumption of the logic chain Pb. When the power consumption of the upper module is analyzed, and the signals A1 and B1 jump simultaneously, the power consumption in the actual circuit is the sum of the power consumptions consumed on the logic chains Pa, pb and Pc, and the value is larger than the sum of the power consumption of the signal A1 and the power consumption of the signal B1 in the power consumption file.
Second error: when the power consumption of the signal A1 is collected, the output jump of the signal B1 is maintained to be 1,ND2, the power consumption of the signal A is the power consumption on the logic chains Pa and Pc, similarly, when the power consumption of the signal B1 is collected, the output jump of the signal A1 is maintained to be 1,ND2, and the power consumption of the signal B is the power consumption on the paths Pb and Pc. When the upper module analyzes the power consumption, and the signals A1 and B1 jump simultaneously, the actual power consumption is Pa, pb and Pc, which is less than the sum of the power consumption of the signal A1 and the power consumption of the signal B1 in the power consumption file.
The accuracy of the power consumption data of the input signal obtained based on the method is low, so that the power consumption analysis of an upper module is influenced.
In order to obtain more accurate power consumption of input signals, the inventor finds in research that in the prior art, when power consumption of an input latch decoding combinational logic part is collected, cross logic and a common path existing in a module are not considered, so that in order to improve the accuracy of collecting power consumption data, when power consumption of each signal is collected, circuit design and logic relationship can be researched, independent logic chain power consumption of each signal and common logic chain power consumption related to other signals are obtained in a segmented mode, and the mutual relationship and the power consumption data of the common logic chain are written into a power consumption file, so that when an upper-layer module carries out power consumption analysis, power consumption under various application excitation can be accurately analyzed according to the mutual logic relationship among the signals.
In order to make those skilled in the art better understand the technical concepts, embodiments and advantages of the examples of the present application, the following detailed description is given by way of specific examples.
Fig. 3 is a schematic flow diagram of a method for collecting power consumption data according to an embodiment of the present application, and as shown in fig. 3, the method for collecting power consumption data according to the embodiment may include:
s101, respectively collecting dynamic power consumption of each input signal in a target module on an internal logic chain of the target module; the logic chain comprises independent logic chains and common logic chains, wherein each independent logic chain corresponds to one input signal, and each common logic chain is related to at least two different input signals; the dynamic power consumption includes: a first power consumption caused by each input signal jumping on the corresponding independent logic chain and a second power consumption caused by each input signal jumping on the corresponding common logic chain.
The target block may be various circuit blocks in a system-on-chip, and in one example, the target block may be an input latch decode block.
The dynamic power consumption refers to the power consumption generated when a transistor is in a jump state when a chip works;
a logical link, which may also be referred to as a logical link, adds hardware and software to the link that implements some procedure for controlling data transfer, and may constitute a data link to the same data pipe.
The independent logic chain may be a chain corresponding to one input signal and independent of the other input signals.
The common logic chain is associated with at least two different input signals, and there may be at least two input signals passing through the common logic chain.
When each path of input signal passes through the independent logic chain, jumping on the independent logic chain, generating first power consumption, jumping on the corresponding common logic chain, and generating second power consumption.
When the target module corresponds to multiple input signals, the first power consumption and the second power consumption corresponding to each input signal are respectively calculated, and the first power consumption and the second power consumption corresponding to each group of input signals are calculated.
And S102, correcting the second power consumption according to the logic relation among all the input signals related to the common logic chain to obtain third power consumption corresponding to the input signals.
When the logic relation between each path of input signals related to a common logic chain is a logic and relation, and each input signal is 1, correcting the second power consumption corresponding to each path of input signals, specifically multiplying the second power consumption by a coefficient smaller than 1, if two paths of input signals are related to a common logic chain, multiplying the second power consumption corresponding to each path of input signals by 0.5, and obtaining a third power consumption which is half of the second power consumption; if four input signals are related to a common logic chain, the second power consumption corresponding to each input signal can be multiplied by 0.25, and the obtained third power consumption is one fourth of the second power consumption.
In this embodiment, dynamic power consumption of each input signal in a target module on an internal logic chain of the target module is collected respectively; the logic chain comprises independent logic chains and common logic chains, each independent logic chain corresponds to one path of input signals, each common logic chain is related to at least two paths of different input signals, and the dynamic power consumption comprises the following steps: the method comprises the steps of generating a common logic chain, generating a first power consumption and a second power consumption, wherein the first power consumption is caused by each path of input signals jumping on the corresponding independent logic chain, the second power consumption is caused by each path of input signals jumping on the corresponding common logic chain, the second power consumption is corrected according to the logic relation between the paths of input signals related to the common logic chain, and the third power consumption corresponding to the input signals is obtained.
Fig. 4 is a flowchart illustrating a method for collecting power consumption data according to another embodiment of the present application, as shown in fig. 4, the method for collecting power consumption data according to another embodiment of the present application is basically the same as the above embodiment, except that, after the second power consumption is modified according to a logic relationship between the input signals related to a common logic chain to obtain a third power consumption of the corresponding input signal (S102), the method further includes:
s103, writing the logic chain division rule, the first power consumption and the third power consumption of the target module into a power consumption file, and analyzing the power consumption of the target module and an upper circuit system of the target module by using the power consumption file.
The logic chain partitioning rules can include which logic chains are independent from other logic chains, which logic chains are interrelated with other logic chains in the target module, which logic chains correspond to only one input signal, which logic chains are related to at least two different input signals, and so on.
Each input signal may have a first power consumption and a third power consumption corresponding thereto.
The power consumption file comprises a logic chain division rule of the target module, and a first power consumption and a third power consumption corresponding to each input signal.
In one example, the upper circuitry of the target module may be circuitry corresponding to a system-on-chip.
The power consumption analysis of the target module and its upper circuit system can be performed according to the data recorded in the power consumption file. When the upper-layer circuit system performs power consumption analysis, the power consumption file of the target module can be used for performing power consumption analysis on various different application scenes in the upper-layer circuit system, or the application scenes are independently constructed, and the power consumption file is used for performing power consumption analysis on the target module.
In this embodiment, the logic chain division rule, the first power consumption and the third power consumption of the target module are written into the power consumption file, so that the target module and the upper circuit system thereof can be conveniently subjected to power consumption analysis by using the power consumption file, and the accuracy of the power consumption analysis of the target module and the upper circuit system thereof can be conveniently improved on the basis that the obtained logic chain division rule, the first power consumption and the third power consumption are accurate.
The present application further includes, substantially the same as the above embodiments, a difference that the method for collecting power consumption data of the present embodiment, after writing the logic chain division rule, the first power consumption, and the third power consumption of the target module into the power consumption file (S103), further includes:
and S104, sequentially utilizing the combination of the plurality of groups of input signals to carry out circuit overall simulation on the target module to obtain the circuit simulation power consumption of the target module.
When the input signal has three paths of A, B and C, the corresponding combination can be combination A and B, combination B and C, combination A and C, and combination A, B and C.
The method can apply excitation to the target module according to various combinations of input signals to obtain the circuit simulation power consumption of the target module, wherein the power consumption comprises the power consumption of the working mode of the target module, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump, the logic relation among all paths of input signals and the static power consumption of the target module.
In some examples, sequentially simulating the target module using combinations of the plurality of sets of input signals to obtain the circuit simulated power consumption of the target module (S104) includes:
s104a, writing an input excitation file by using a Verilog language, wherein the input excitation file comprises a plurality of groups of input signals.
Verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form, and can be used to represent logic circuit diagrams, logic expressions, and logic functions performed by digital logic systems.
And S104b, compiling the input excitation file by using a Verilog compiler to obtain a corresponding numerical value vector file.
The Verilog compiler may translate Verilog language to a low-level language.
And compiling the combination of a plurality of groups of input signals in the input excitation file by using a Verilog compiler to obtain a numerical vector file corresponding to the input excitation.
The Verilog excitation file can obtain a waveform file and a numerical vector file of the input signal through a Verilog compiler, wherein the format of the waveform file can be fsdb, vcd format and the like, and the file format of the numerical vector file is vec format and the like. The signal states of the waveform file and the numeric vector file are consistent.
The input waveform and digital vector files for verification are derived from the same input excitation file, the waveform file records the signal value change condition, and most waveform tools support the vcd format, so that the state and jump of each signal can be conveniently checked to see whether the state and jump are in accordance with expectations.
And (3) using the numerical vector file (vec) for netlist simulation, and simulating power consumption data in different working states in each period by using a simulation tool.
The vcd format file records the signal value change condition. Most waveform tools support the VCD format and can easily check whether the state and transition of each signal are expected.
And S104c, loading the numerical vector file by using a simulation tool, and simulating the target module to obtain the circuit simulation power consumption of the target module.
The simulation tool may be a finesim; and loading the numerical vector file to obtain input excitation, and simulating the target module by using the input excitation to obtain the circuit simulation power consumption of the target module.
In the embodiment, the input excitation file is written in the Verilog language, so that the state of the signal line is conveniently adjusted, the input excitation of different application scenes is easily input, the interrelation between signals and power consumption data are conveniently verified for many times, the power consumption error reason can be quickly found, the excitation during power consumption data collection is corrected, and correct power consumption data are obtained again.
And S105, calculating mathematical calculation power consumption of the target module under the combination of each group of input signals in sequence by using the power consumption file.
The power consumption file comprises logic chain division rules of the target module, power consumption of each input signal, power consumption of the target module in a working mode, power consumption of each output signal and mutual relations among the signals.
The power consumption of each input signal and the power consumption of each output signal may be specifically determined according to a state of each signal and a transition ratio (toggle rate).
In some examples, sequentially calculating a mathematically calculated power consumption of the target module for each set of the combination of input signals using the power consumption file (S105) includes:
and S105a, writing a power consumption excitation file by utilizing a Verilog language, wherein the power consumption excitation file comprises a plurality of groups of input signals.
Verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form, and can be used to represent logic circuit diagrams, logic expressions, and logic functions performed by digital logic systems.
The combination of the plurality of groups of input signals included in the power consumption excitation file can be respectively and correspondingly equal to the combination of the plurality of groups of input signals included in the input excitation file.
S105b, according to the combination of each group of input signals in the power consumption excitation file, searching the power consumption of the working mode of the target module, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump and the logic relation among all paths of input signals in the power consumption file, and calculating the total power consumption of the target module.
The power consumption file comprises a logic chain division rule of the target module, the power consumption of each input signal, the power consumption of the target module in a working mode, the power consumption of each output signal and the mutual relation among the signals, and the power consumption of the working mode where the target module is located, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump, the logic relation among all paths of input signals and the static power consumption of the target module can be searched in the power consumption file according to the combination of each group of input signals in the power consumption excitation file, so that the total power consumption is calculated.
And S106, correcting the logic chain division rule of the target module according to the difference between the circuit simulation power consumption corresponding to each group of input signals and the mathematical calculation power consumption.
When the difference value between the circuit simulation power consumption and the mathematical calculation power consumption corresponding to each group of input signals is within a preset threshold range, the logic chain division rule of the corresponding target module can be written into a power consumption file, and other data in the power consumption file can be used for carrying out power consumption analysis on the target module and an upper layer circuit system of the target module.
The following describes the implementation of the technical solution of the present application in detail with a specific example.
Fig. 5 is a schematic diagram of a power consumption data collection method according to an embodiment of the present application.
Referring to fig. 5, in a large sub-module, it is difficult to accurately cut out a common logic chain with other signals at a time for a complicated circuit design. In order to improve the accuracy of the data, the power consumption data needs to be subjected to data verification, and after multiple times of optimization and iterative input excitation, the accurate power consumption data of each independent logic chain and the power consumption data of the related common logic chain are obtained.
Step 1, obtaining a waveform file and a numerical vector file corresponding to input excitation through input signal combination in an input excitation file.
And 2, loading the numerical vector file by using a simulation tool, and simulating the target module to obtain the circuit simulation power consumption of the target module.
And 3, calculating mathematical calculation power consumption according to the combination of the input signals in the power consumption excitation file, specifically, searching the power consumption of the working mode of the target module, the dynamic power consumption of the input signals, the dynamic power consumption of the output jump, the logic relation among all paths of input signals and the static power consumption of the target module in the power consumption file, and calculating the total power consumption.
The combination of input signals in the power consumption stimulus file is the same as the combination of input signals in the input stimulus file.
If the data of the circuit simulation power consumption is inconsistent with the data of the mathematical computation power consumption, the power consumption excitation file can be optimized to check which data in the power consumption file is incorrect, the input excitation for collecting the power consumption data is readjusted, and the simulation is carried out again to obtain correct data.
It should be noted that the circuit simulation power consumption is actual circuit power consumption, and may be based on the circuit simulation power consumption, and optimize data in the power consumption excitation file, including logic chain division rules of the target module, input excitation combinations, power consumption of each input signal, and the like.
Fig. 6 is a schematic structural diagram of a power consumption data collecting device according to an embodiment of the present application, and as shown in fig. 6, the power consumption data collecting device according to the embodiment may include: the dynamic power consumption collecting module 11 is configured to collect dynamic power consumption of each input signal in a target module on an internal logic chain of the target module; the logic chain comprises independent logic chains and common logic chains, wherein each independent logic chain corresponds to one path of input signals, and each common logic chain is related to at least two paths of different input signals; the dynamic power consumption includes: a first power consumption caused by each input signal jumping on the corresponding independent logic chain and a second power consumption caused by each input signal jumping on the corresponding common logic chain; and a correcting module 12, configured to correct the second power consumption according to a logic relationship between the input signals related to the common logic chain, so as to obtain a third power consumption corresponding to the input signal.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, which are not described herein again.
The device of the embodiment collects the dynamic power consumption of each input signal on the internal logic chain of the target module in the target module respectively; the logic chain comprises independent logic chains and common logic chains, each independent logic chain corresponds to one path of input signals, each common logic chain is related to at least two paths of different input signals, and the dynamic power consumption comprises the following steps: the method comprises the steps of generating a common logic chain, generating a first power consumption and a second power consumption, wherein the first power consumption is caused by each path of input signals jumping on the corresponding independent logic chain, the second power consumption is caused by each path of input signals jumping on the corresponding common logic chain, the second power consumption is corrected according to the logic relation between the paths of input signals related to the common logic chain, and the third power consumption corresponding to the input signals is obtained.
As an optional implementation, the apparatus further includes: and the writing module is used for writing the logic chain division rule of the target module, the first power consumption and the third power consumption into a power consumption file so as to analyze the power consumption of the target module and an upper circuit system thereof by using the power consumption file.
As an optional implementation, the apparatus further includes: the circuit simulation power consumption module is used for sequentially utilizing the combination of a plurality of groups of input signals to carry out circuit overall simulation on the target module so as to obtain the circuit simulation power consumption of the target module; the mathematical calculation power consumption module is used for sequentially calculating the mathematical calculation power consumption of the target module under the combination of each group of the input signals by using the power consumption file; and the correction module is used for correcting the logic chain division rule of the target module according to the difference between the circuit simulation power consumption corresponding to each group of input signals and the mathematical calculation power consumption.
As an optional implementation, the circuit emulation power consumption module includes: the compiling submodule is used for compiling an input excitation file by utilizing a Verilog language, and the input excitation file comprises a plurality of groups of combinations of the input signals; the compiling submodule is used for compiling the input excitation file by using a Verilog compiler to obtain a corresponding numerical vector file; and the circuit simulation power consumption submodule is used for loading the numerical vector file by using a simulation tool, simulating the target module and obtaining the circuit simulation power consumption of the target module.
As an optional implementation, the mathematical computation power consumption module includes: the compiling submodule is used for compiling a power consumption incentive file by utilizing a Verilog language, and the power consumption incentive file comprises a plurality of groups of combinations of the input signals; and the total power consumption calculation submodule is used for searching the power consumption of the working mode of the target module, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump and the logic relationship among the input signals in the power consumption file and the static power consumption of the target module according to the combination of each group of input signals in the power consumption excitation file, and calculating the total power consumption.
The apparatus in the foregoing embodiment may be configured to implement the technical solutions in the foregoing method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations when the present application is implemented.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. A method of collecting power consumption data, comprising:
respectively collecting dynamic power consumption of each input signal on an internal logic chain of a target module in the target module; the logic chain comprises independent logic chains and common logic chains, wherein each independent logic chain corresponds to one path of input signals, and each common logic chain is related to at least two paths of different input signals; the dynamic power consumption includes: a first power consumption caused by each input signal jumping on the corresponding independent logic chain and a second power consumption caused by each input signal jumping on the corresponding common logic chain;
correcting the second power consumption according to the logic relation among all the input signals related to the common logic chain to obtain third power consumption corresponding to the input signals;
and writing the logic chain division rule, the first power consumption and the third power consumption of the target module into a power consumption file so as to analyze the power consumption of the target module and an upper circuit system thereof by using the power consumption file.
2. The method of claim 1, wherein after writing the logic chain partitioning rule, the first power consumption, and the third power consumption of the target module into a power consumption file, the method further comprises:
sequentially utilizing the combination of a plurality of groups of input signals to carry out circuit overall simulation on the target module to obtain the circuit simulation power consumption of the target module;
calculating mathematical calculation power consumption of the target module under the combination of each group of the input signals in sequence by using the power consumption file;
and correcting the logic chain division rule of the target module according to the difference between the circuit simulation power consumption corresponding to each group of input signals and the mathematical calculation power consumption.
3. The method of claim 2, wherein the sequentially simulating the target module with the combination of the plurality of sets of input signals to obtain the circuit simulated power consumption of the target module comprises:
writing an input excitation file by utilizing a Verilog language, wherein the input excitation file comprises a plurality of groups of combinations of the input signals;
compiling the input excitation file by using a Verilog compiler to obtain a corresponding numerical value vector file;
and loading the numerical vector file by using a simulation tool, and simulating the target module to obtain the circuit simulation power consumption of the target module.
4. The method of claim 2, wherein the using the power consumption file to sequentially calculate the mathematically calculated power consumption of the target module for each set of the combination of input signals comprises:
writing a power consumption excitation file by using a Verilog language, wherein the power consumption excitation file comprises a plurality of groups of combinations of the input signals;
and searching the power consumption of the working mode of the target module, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump and the logic relation among the input signals, and the static power consumption of the target module in the power consumption file according to the combination of each group of input signals in the power consumption excitation file to calculate the total power consumption.
5. An apparatus for collecting power consumption data, comprising:
the dynamic power consumption collection module is used for respectively collecting the dynamic power consumption of each input signal in the target module on the internal logic chain of the target module; the logic chain comprises independent logic chains and common logic chains, wherein each independent logic chain corresponds to one path of input signals, and each common logic chain is related to at least two paths of different input signals; the dynamic power consumption includes: a first power consumption caused by each input signal jumping on the corresponding independent logic chain and a second power consumption caused by each input signal jumping on the corresponding common logic chain;
the correction module is used for correcting the second power consumption according to the logic relation among all the input signals related to the common logic chain to obtain third power consumption corresponding to the input signals;
and the writing module is used for writing the logic chain division rule of the target module, the first power consumption and the third power consumption into a power consumption file so as to analyze the power consumption of the target module and an upper circuit system thereof by utilizing the power consumption file.
6. The apparatus of claim 5, further comprising:
the circuit simulation power consumption module is used for carrying out circuit overall simulation on the target module by sequentially utilizing the combination of a plurality of groups of input signals to obtain the circuit simulation power consumption of the target module;
the mathematical calculation power consumption module is used for sequentially calculating the mathematical calculation power consumption of the target module under the combination of each group of the input signals by using the power consumption file;
and the correction module is used for correcting the logic chain division rule of the target module according to the difference between the circuit simulation power consumption corresponding to each group of input signals and the mathematical calculation power consumption.
7. The apparatus of claim 6, wherein the circuit emulates a power consumption module comprising:
the compiling submodule is used for compiling an input excitation file by utilizing a Verilog language, and the input excitation file comprises a plurality of groups of combinations of the input signals;
the compiling submodule is used for compiling the input excitation file by using a Verilog compiler to obtain a corresponding numerical vector file;
and the circuit simulation power consumption submodule is used for loading the numerical vector file by using a simulation tool, simulating the target module and obtaining the circuit simulation power consumption of the target module.
8. The apparatus of claim 6, wherein the mathematical computation power consumption module comprises:
the compiling submodule is used for compiling a power consumption incentive file by utilizing a Verilog language, and the power consumption incentive file comprises a plurality of groups of combinations of the input signals;
and the total power consumption calculation sub-module is used for searching the power consumption of the working mode of the target module, the dynamic power consumption of each input signal, the dynamic power consumption of each output jump and the logic relationship among the input signals in the power consumption file according to the combination of each group of input signals in the power consumption excitation file, and calculating the total power consumption of the target module according to the static power consumption of the target module.
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