CN104009014B - Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method - Google Patents
Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method Download PDFInfo
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- CN104009014B CN104009014B CN201410173160.6A CN201410173160A CN104009014B CN 104009014 B CN104009014 B CN 104009014B CN 201410173160 A CN201410173160 A CN 201410173160A CN 104009014 B CN104009014 B CN 104009014B
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- wiring layer
- metal wiring
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- glass substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to an integrated passive device wafer-level packaging three-dimensional stacked structure and a manufacturing method. The integrated passive device wafer-level packaging three-dimensional stacked structure comprises a wafer-level packaging chip and an IPD chip. The IPD chip comprises a glass substrate, wherein an IPD device and a metal wiring layer are arranged on the front surface of the glass substrate, the back surface of the glass substrate is etched to form TGV holes, back surface metal wiring layers are arranged on the back surface of the glass substrate and the inner surfaces of the TGV holes, a welding ball is arranged on a welding pad of each back surface metal wiring layer, and the welding balls are connected with a PCB. The manufacturing method of the three-dimensional stacked structure comprises the following steps that (1) the wafer-level packaging chip and the IPD chip of the glass substrate are stacked; (2) the back surface of the IPD chip is etched to form the TGV holes, the back surface metal wiring layer is manufactured on the back surface of the glass substrate; (3) the back surface metal wiring layer is etched into two insulated parts; the welding pads and welding balls are manufactured on the two parts of the back surface metal wiring layer, and the welding balls are connected with the PCB. By means of the integrated passive device wafer-level packaging three-dimensional stacked structure and the manufacturing method, short-distance interconnection between the chip and the IPD device is achieved, and the electric quality is improved.
Description
Technical field
The present invention relates to a kind of wafer-level packaging three-dimensional stacking structure, especially a kind of integrated passive devices wafer-level packaging
Three-dimensional stacking structure and preparation method, belong to high-density electronic package technical field.
Background technology
Wafer-level packaging is different from traditional packaged type to be, traditional chip package is first to cut seal again survey, encapsulation
Area afterwards at least increases by 20% than former chip size；And wafer-level packaging is then first packaging and testing to be carried out on full wafer wafer,
Then scribing segmentation again, therefore, the volume after encapsulation is equivalently-sized with bare chip, and the chip size after encapsulation can be greatly reduced.
Wafer stage chip encapsulation is provided and can substitute current bonding wire BGA（Ball Grid Array, the PCB of ball grid array structure）With
The low cost of flip-chip BGA package, high-performance integration packaging.The wiring of the signal, electric power and ground wire of wafer-level packaging is direct
By wafer scale RDL（Wiring layer again）Technique is realized, it is no longer necessary to which wafer convex point is prepared and base plate for packaging, so as to reduce being packaged into
This, and the electrical functions better than tradition bonding wire BGA and flip-chip BGA package can be provided.
Thin-film integration passive techniques generally can provide most excellent functional density, and highest integrated level and minimum volume.
However, the passive device of conventional films integrating passive is deposited metal on Si wafers, and in high-frequency circuit, the meeting of Semiconductor substrate Si
High-frequency vortex phenomenon is produced, causing the performance of circuit reduces, it is impossible to meet high-frequency circuit, particularly RF（Radio frequency）The performance of device
Require.And the passive device of integrating passive in glass substrate, the electric capacity quality factor q run in Si integrated passive devices can be solved
It is worth relatively low, inductance narrower bandwidth and high-frequency vortex problem, meets the performance requirement of high-frequency circuit, particularly RF devices.
In prior art, the maximum weak point of wafer stage chip encapsulation and the passive passive device of thin-film integration is integrated level
It is relatively low.Generally, wafer stage chip encapsulates the not passive device of integrating passive, and matched passive device is occupied about
80% board area and 70% assembling product cost.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of integrated passive devices wafer-level packaging
Three-dimensional stacking structure and preparation method, by wafer stage chip encapsulation and the passive device of glass integrating passive（IPD）By wafer scale
Bonding technology bonds together, and realizes the short distance interconnection between chip and IPD devices, improves electricity quality.
According to the technical scheme that the present invention is provided, the making side of integrated passive devices wafer-level packaging three-dimensional stacking structure
Method, is characterized in that, comprise the following steps：
（1）The IPD chips of wafer-level packaging chip and glass substrate are stacked, the metal line of IPD chip front sides
Layer is connected with the chip signal port of wafer-level packaging chip；
（2）TGV holes are obtained in the back-etching of IPD chips, TGV holes are by the back-etching of glass substrate to positive metal
Wiring layer；
（3）In the back spatter metal of glass substrate, the inner surface at the back side of glass substrate, TGV holes obtains back-side gold
Category wiring layer；
（4）Back metal wiring layer is performed etching, back metal wiring layer is etched into into two parts of mutually insulated；
（5）Pad is made respectively on the back metal wiring layer of two parts insulation, makes soldered ball respectively on pad；
（6）Said structure is interconnected by soldered ball with pcb board, integrated passive devices wafer-level packaging three-dimensional heap is completed
The making of stack structure.
The thermal coefficient of expansion of the glass substrate is more than silicon substrate, less than pcb board.
The IPD devices and metal wiring layer are concordant with the front of IPD chips.
The present invention is three-dimensionally integrated there is provided a set of efficient with the passive passive device of thin-film integration for wafer stage chip encapsulation
Solution, is that electronic product continues minification, increases one of solution of function, meets portable type electronic product " more
Hurry up, it is less, lighter " trend, and cost performance improve constantly.The present invention realizes chip and passive passive integrated device（IPD）It
Between short distance interconnection, improve electricity quality；Meanwhile, the passive device of glass integrating passive is compared with the passive device of Si integrating passives
Resonant circuit quality factor Q value has greatly lifting；Also, the thermal coefficient of expansion of glass IPD chips is carried between Si chips and PCB
Between plate（Thermal coefficient of expansion Si<Glass<PCB）, present invention achieves thermal coefficient of expansion putting step by step in packaging body Z-direction
Greatly, the Si chips for the superiors provide good stress buffer protective effect.The enforcement of the present invention meets electronic product development
Trend, match with existing production technology, be the three-dimensional integration scheme of a set of compact size high reliability.
Description of the drawings
Fig. 1～Fig. 6 is the schematic diagram of the manufacture process of three-dimensional stacking structure of the present invention.
Fig. 1 is wafer-level packaging chip and IPD chip-stacked schematic diagram.
Fig. 2 is the schematic diagram that TGV holes are made on IPD chips.
Fig. 3 is to make the schematic diagram of back metal wiring layer at the glass substrate back side.
Fig. 4 is the schematic diagram performed etching to back metal wiring layer.
Fig. 5 is the schematic diagram for making soldered ball.
Fig. 6 is the schematic diagram of integrated passive devices wafer-level packaging three-dimensional stacking structure of the present invention.
Specific embodiment
With reference to concrete accompanying drawing, the invention will be further described.
As shown in Figure 6：The integrated passive devices wafer-level packaging three-dimensional stacking structure includes pcb board 1, wafer-level packaging
Chip 2, IPD chips 3, glass substrate 4, IPD devices 5, metal wiring layer 6, TGV holes 7, back metal wiring layer 8, pad 9, weldering
Ball 10, chip signal port 11 etc..
As shown in fig. 6, three-dimensional stacking structure of the present invention is packaged on pcb board 1, including the He of wafer-level packaging chip 2
IPD chips 3；The IPD chips 3 include glass substrate 4, and in the front of glass substrate 4 IPD devices 5 and connection IPD devices are arranged
5 metal wiring layer 6, IPD devices 5 and metal wiring layer 6 it is concordant with the front of IPD chips 3, metal wiring layer 6 and wafer scale
The chip signal port 11 of encapsulation chip 2 connects；TGV holes 7 are formed in the back-etching of the glass substrate 4, TGV holes 7 are gone directly
Metal wiring layer 6；In the back side of the glass substrate 4 and the inner surface setting back metal wiring layer 8 in TGV holes 7, back metal
8 points of two parts for mutually insulated of wiring layer, two parts back metal wiring layer 8 is connected respectively with metal wiring layer 6, and point
Soldered ball 10 is not set on the pad 9 of two parts back metal wiring layer 8, and soldered ball 10 is connected with pcb board 1；
The thermal coefficient of expansion of the glass substrate 4 is more than silicon substrate, less than pcb board 1, in the three-dimensional stacking structure of the present invention
In, step by step amplification of the hot expansion system in packaging body Z-direction is realized, the silicon for the superiors provides good stress
Buffer protection function.
As shown in Fig. 1～Fig. 6, the making side of integrated passive devices wafer-level packaging three-dimensional stacking structure of the present invention
Method, comprises the following steps：
（1）As shown in figure 1, the IPD chips 3 of wafer-level packaging chip 2 and glass substrate 4 are stacked, IPD chips 3
Positive metal wiring layer 6 is connected with the chip signal port 11 of wafer-level packaging chip 2, realizes IPD chips 3 and wafer scale envelope
Signal connection between cartridge chip 2；
（2）As shown in Fig. 2 the back-etching in IPD chips 3 obtains TGV（Through Glass Via）Hole 7, TGV holes 7
By the back-etching of glass substrate 4 to positive metal wiring layer 6；
（3）As shown in figure 3, in the back spatter metal of glass substrate 4, such as copper or tungsten, the back side of glass substrate 4,
The inner surface in TGV holes 7 obtains back metal wiring layer 8, and the thickness of back metal wiring layer 8 is 1～30 micron；
（4）As shown in figure 4, performing etching to back metal wiring layer 8, back metal wiring layer 8 is etched into mutually absolutely
Two parts of edge；The effect of two parts back metal wiring layer 8 is that TGV holes are re-assigned to into other positions, with convenient
It is interconnected with pcb board 1；
（5）As shown in figure 5, making pad 9 respectively on the back metal wiring layer 8 of two parts insulation, divide on pad 9
Zhi Zuo not soldered ball 10, realization and outside function connects；
（6）As shown in fig. 6, said structure is interconnected by soldered ball 10 with pcb board 1, integrated passive devices are completed brilliant
Circle level encapsulates the making of three-dimensional stacking structure.
Claims (3)
1. a kind of preparation method of integrated passive devices wafer-level packaging three-dimensional stacking structure, is characterized in that, comprise the following steps：
（1）By wafer-level packaging chip（2）And glass substrate（4）IPD chips（3）Stacked, IPD chips（3）It is positive
Metal wiring layer（6）With wafer-level packaging chip（2）Chip signal port（11）Connection；
（2）In IPD chips（3）Back-etching obtain TGV holes（7）, TGV holes（7）By glass substrate（4）Back-etching to just
The metal wiring layer in face（6）；
（3）In glass substrate（4）Back spatter metal, in glass substrate（4）The back side, TGV holes（7）Inner surface carried on the back
Face metal wiring layer（8）；
（4）To back metal wiring layer（8）Perform etching, by back metal wiring layer（8）It is etched into two parts of mutually insulated；
（5）In the back metal wiring layer of two parts insulation（8）It is upper to make pad respectively（9）, in pad（9）It is upper to make weldering respectively
Ball（10）；
（6）Said structure is passed through into soldered ball（10）With pcb board（1）It is interconnected, completes integrated passive devices wafer-level packaging three
The making of dimension stacked structure.
2. the preparation method of integrated passive devices wafer-level packaging three-dimensional stacking structure as claimed in claim 1, is characterized in that：
The glass substrate（4）Thermal coefficient of expansion more than silicon substrate be less than pcb board（1）.
3. the preparation method of integrated passive devices wafer-level packaging three-dimensional stacking structure as claimed in claim 1, is characterized in that：
IPD devices（5）And metal wiring layer（6）With IPD chips（3）Front it is concordant.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410173160.6A CN104009014B (en) | 2014-04-26 | 2014-04-26 | Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method |
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| CN201410173160.6A CN104009014B (en) | 2014-04-26 | 2014-04-26 | Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method |
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| CN104009014A CN104009014A (en) | 2014-08-27 |
| CN104009014B true CN104009014B (en) | 2017-04-12 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104486907B (en) * | 2014-12-10 | 2017-08-11 | 华进半导体封装先导技术研发中心有限公司 | The three-dimensionally integrated wafer level packaging structure of high-frequency I PD modules and method for packing |
| US9768133B1 (en) | 2016-09-22 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
| CN108335986B (en) * | 2017-09-30 | 2021-04-06 | 中芯集成电路（宁波）有限公司 | Wafer level system packaging method |
| CN113443602B (en) * | 2021-06-02 | 2023-12-08 | 中国科学院地质与地球物理研究所 | Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof |
Citations (2)
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| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
| CN103119703A (en) * | 2010-09-23 | 2013-05-22 | 高通Mems科技公司 | Integrated passives and power amplifier |
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| US7183176B2 (en) * | 2004-08-25 | 2007-02-27 | Agency For Science, Technology And Research | Method of forming through-wafer interconnects for vertical wafer level packaging |
| US8362599B2 (en) * | 2009-09-24 | 2013-01-29 | Qualcomm Incorporated | Forming radio frequency integrated circuits |
| CN102163603B (en) * | 2011-01-30 | 2013-11-06 | 南通富士通微电子股份有限公司 | Packaging structure for system level fan-out wafer |
| CN102176418B (en) * | 2011-03-22 | 2013-02-20 | 南通富士通微电子股份有限公司 | Fan-out system-in-package (SIP) method |
| CN202384323U (en) * | 2011-12-14 | 2012-08-15 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure |
| US9564415B2 (en) * | 2012-09-14 | 2017-02-07 | Maxim Integrated Products, Inc. | Semiconductor package device having passive energy components |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
| CN103119703A (en) * | 2010-09-23 | 2013-05-22 | 高通Mems科技公司 | Integrated passives and power amplifier |
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