CN103888148B - A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal - Google Patents

A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal Download PDF

Info

Publication number
CN103888148B
CN103888148B CN201410105530.2A CN201410105530A CN103888148B CN 103888148 B CN103888148 B CN 103888148B CN 201410105530 A CN201410105530 A CN 201410105530A CN 103888148 B CN103888148 B CN 103888148B
Authority
CN
China
Prior art keywords
hard decision
threshold
ldpc code
sequence
bit reversal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410105530.2A
Other languages
Chinese (zh)
Other versions
CN103888148A (en
Inventor
高美洲
李峰
张洪柳
刘大铕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Sinochip Semiconductors Co Ltd
Original Assignee
Shandong Sinochip Semiconductors Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong Sinochip Semiconductors Co Ltd filed Critical Shandong Sinochip Semiconductors Co Ltd
Priority to CN201410105530.2A priority Critical patent/CN103888148B/en
Publication of CN103888148A publication Critical patent/CN103888148A/en
Priority to PCT/CN2014/001171 priority patent/WO2015139160A1/en
Application granted granted Critical
Publication of CN103888148B publication Critical patent/CN103888148B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1108Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping

Abstract

The invention discloses a kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal, determine an initial turn threshold T, use dynamic threshold, namely dynamic turn threshold, turn threshold is become dynamic threshold and can reduce the probability of upset by mistake, decreasing the iterations of decoding, the bit-flipping decoding making LDPC code is more efficient;Also improving the error correcting capability of LDPC code, the present invention has strengthened than the error correcting capability of the bit reversal method of standard simultaneously.

Description

A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal
Technical field
The present invention relates to a kind of LDPC (Low Density Parity Check, low density parity check code) hard decision translate The bit reversal building method of code device.
Background technology
In the various application needing to carry out signal transmission, often can use error correcting code (ECC, Error Correcting Code), when can make signal transmission errors, righted the wrong at receiving terminal and obtained correct signal.
Error correcting code can apply in many systems, in a communications system, and may be by channel effect during signal transmission And the interference of interchannel noise, thus cause the data stored in flash memory device the most incorrect.In flash memory device The data stored are the data after error correcting code device code, and for flash memory storage controls device, error correcting code is must The functional unit needed.
Along with the technique of memorizer is increasingly advanced, memory cell volume is more and more less, and memory element is stored Data the most gradually increase, cause flash memories read during produce error probability constantly raise.Therefore, flash memory The error correcting code error correcting capability of storage control device is to determine the key factor that storage control device is the most qualified.But, Flash memory storage controls to use stronger error correcting code to need higher operand and relatively Long operation time in device, thus increases flash memory The application of storage control device is very restricted.
LDPC code is that Robert Gallager has sparse check matrix in the one that 1962 propose in thesis for the doctorate Packeting error-correcting code.Being suitable for almost all of channel, its performance approaches shannon limit, and describes and realize simple, decoding letter Single and practicable parallel work-flow, is suitable for hardware and realizes.
LDPC code has huge application potential, at deep space communication, fiber optic communication, satellite communication, satellite digital video, number Word watermark, magnetic optical/Hologram Storage, movement and fixed radio communication, cable modulating/demodulating and digital subscriber obtain extensively should With.
Technique according to flash memory device is increasingly advanced, and flash memories controls the error correction energy of the error correcting code in device Power is also required to strengthen.In current flash memories controls device, main error correcting code is BCH code, along with the increasing of error probability Height, BCH code space requirement and operational capability are also gradually increased;Along with the raising of flash memory storage technique, the error correction energy of BCH code Power is the most gradually not suitable for the development of flash technology, so needing the higher error correcting code of error correcting capability.LDPC code is selected to replace BCH code is that comparison is appropriate.
In the Hard decision decoding device of LDPC code, the setting of bit reversal threshold value T, rises the Hard decision decoding of LDPC code Vital effect, it affects error correcting capability and its decoding rate of LDPC code.
If what bit reversal threshold value T set crosses conference increases the iterations of decoding, thus affects decoding rate.
If the too small meeting that bit reversal threshold value T sets causes upset by mistake thus to increase the iterations of decoding, Thus affect decoding rate.
For irregular check matrix, choose fixing bit reversal threshold value T, the biggest mistake can be caused like that Overturn probability thus considerably increase the iterations of decoding, cause decoding failure in severe cases.
When in sequence Z, the error rate of code element reaches certain value, fixing bit reversal threshold value T is used to decode, No matter decoder iteration is big all without successfully decoding often.
Summary of the invention
Based on dynamic threshold, the LDPC code hard decision that it is an object of the invention to provide a kind of dynamic threshold bit reversal is translated Code method, improves decoding rate and error correcting capability.
The present invention is by the following technical solutions:
A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal, determines an initial turn threshold T, bag Include following steps:
1) read codeword sequence, calculate syndrome according to codeword sequence;
2) judge whether syndrome is zero, if zero, then stop iteration, output codons sequence;Otherwise enter step 3);
3) each symbol bits to code word each in codeword sequence, calculate the participation of this symbol bits is unsatisfactory for verification The number of equation;
4) turn threshold is calculated: along with increasing of iterations, turn threshold T successively decreases, and obtains current turn threshold;
5) if the number of ungratified check equations is more than current turn threshold, corresponding symbol bits overturns, And calculate the syndrome of codeword sequence corresponding after upset;
6) repeat step 1), 2), 3), 4) and 5), until successfully decoded, or when reaching maximum iteration time, output is translated Code failure.
The LDPC code Hard decision decoding method of above-mentioned dynamic threshold bit reversal, current turn threshold T:
T=j (b-c d)/a;
In formula: d represents current for which time iteration, j be corresponding to symbol bits when prostatitis row weight, a, b, c are experience Normal number.
The LDPC code Hard decision decoding method of above-mentioned dynamic threshold bit reversal, determines an initial turn threshold T, repeatedly In Dai, the step of upset is as follows:
A) according to hard decision sequence Z=[z0, z1..., zN-1] calculate syndrome S=[s0, s1..., sM-1]:
s m = Σ n = 0 N - 1 H m n z n T mod 2 , m = 0 , 1 , ... , M - 1 ;
Wherein HmnTest matrix, if syndrome S=0, stops iteration, and output hard decision sequence Z also shows successfully decoded, Otherwise enter b);
B) to each symbol bits zn, calculate number f of its ungratified check equations participated inn:
f n = Σ m = 0 M - 1 s m H m n , n = 0 , 1 , ... , N - 1
If fn> T, then overturn zn, obtain new hard decision sequence Z;
C) repeat a) and b) until successfully decoded, or reach maximum iteration time and show decoding failure;
Hard decision sequence is step 5) codeword sequence that obtains after upset;
Wherein M represents the line number of test matrix, and N represents the columns of test matrix.
According to the present invention, using dynamic threshold, namely dynamic turn threshold, turn threshold is become dynamic threshold can To reduce the probability of upset by mistake, decreasing the iterations of decoding, the bit-flipping decoding making LDPC code is more efficient;The most also Improve the error correcting capability of LDPC code, the present invention has strengthened than the error correcting capability of the bit reversal method of standard.
Accompanying drawing explanation
Fig. 1 is the theory diagram of flash memories memory control device.
Fig. 2 is LDPC code unit bit-flipping decoding flow chart.
Detailed description of the invention
LDPC code is the one of linear block codes, and it has all of characteristic of linear block codes.LDPC code can be divided into rule The then big class hypothesis check matrix H of (regular-LDPC) and irregular (irregular-LDPC) two0For m × n rank matrix, rule LDPC code can be denoted as (n, j, k), wherein n is code length, j be check matrix each column weight (i.e. row in 1 number, be called for short row Weight (column weight), k is the weight (at once, the number of 1, is called for short row weight (row weight)) that check matrix is often gone, And typically have j > 2, k > j and the number of the 1 of the check matrix each row and column of irregular LDPC codes is incomplete same.
The iterative decoding method of LDPC code is broadly divided into two kinds: one is hard-decision method, and one is soft decision method. What hard-decision bits method for turning transmitted in an iterative process is binary system hard information, and soft decision method passes in an iterative process Pass is the real number Soft Inform ation with probability correlation.Hard-decision method is simple to operate, it is easy to hardware realizes, but error-correcting performance one As;Soft decision method better performances, but implementation complexity is higher.This programme improves mainly for Hard decision decoding device and carries Its error correction energy ability high.The detailed process of the hard-decision bits upset interpretation method of LDPC code is introduced as follows.
Bit reversal method is often being taken turns in iteration, first calculates the value of syndrome according to last round of hard decision sequence.As The most all of syndrome is 0, then stop iteration, and show successfully decoded, otherwise calculates the syndrome that each bit participates in It is the number of the check equations of 1, participation is unsatisfactory for check equations number and turns over more than the bit of certain predetermined threshold threshold value T Turn, obtain a new hard decision sequence, subsequently into next round iteration, until successfully decoded or reach maximum iteration time And show decoding failure.Properly select the size of threshold value T, can reach optimal decoding performance.
Hard decision sequence is the sequence of the needs decoding that decoder receives sequence after bit reversal method overturns.
Fig. 1 is the functional block diagram after an embodiment simplification of flash memory storage control device.In flash memory storage controller Comprise LDPC code decoder.Flash memory storage controller is mainly responsible for the read-write of data and the storage of data and other function.
Flash memory storage controller obtains data from main frame and carries out encoding operation through LDPC code decoder and the data that produce Store in flash memories.Flash memory storage controller is needed to come from sudden strain of a muscle if main frame goes for the data in flash memories Deposit in memorizer and read out, be decoded computing through LDPC code decoder and produce data and input to main frame.
Fig. 2 is dynamic threshold (dynamic threshold, turn threshold, dynamic turn threshold and bit reversal threshold value in literary composition Representing that same threshold value uses the title under environment in difference, those skilled in the art is easy to understand) LDPC of bit reversal Code coding method flow chart.Obtaining codeword sequence by flash memory storage controller from flash memories, ldpc code decoder reads This codeword sequence.The whole decoding process of LDPC code as can be seen from Figure 2.Determine an initial turn threshold T, thus its process As follows:
(1), after reading codeword sequence, syndrome is calculated according to codeword sequence;
(2) judging whether syndrome S is zero, stop iteration if zero, output codons sequence also shows successfully decoded, Otherwise enter (3);
(3) each symbol bits to each code word in each codeword sequence, calculates being unsatisfactory for of its participation The number of check equations;
(4) mode successively decreased is used to determine new turn threshold;
(5) if ungratified check equations number is more than new turn threshold, corresponding code word overturns;
(6) repeat (1), (2), (3), (4) and (5) until successfully decoded, or reach maximum iteration time and display is translated Code failure.
Code element: usually represent a binary digit with the symbol that time interval is identical in digital communication, such Signal in time interval is referred to as (binary system) code element.And this interval is referred to as Baud Length.Code word (code word) is then It is made up of some code elements.
It is the Essential Terms of this area about used term, it is not explained in detail, such as syndrome, according to communication (n, k) syndrome of code, if the error correcting capability of this yard is t, then weight is little for the general explanation of principle, i.e. Linear codes In or have unique syndrome (syndrome) corresponding therewith equal to all error patterns of t.
About turn threshold, using given formula to successively decrease, amount of calculation is smaller, but representative bad, it is impossible to have Effect represents the present situation of decoding.
On the basis of the method for the bit-flipping decoding of LDPC code, the LDPC code of a kind of dynamic threshold bit reversal of proposition Interpretation method.Principle is, LDPC code is when carrying out bit-flipping decoding, and its turn threshold is a fixed value, is decoding Journey easily causes the upset of mistake, thus the iterations adding decoder makes decoding time long.In order to more effectively Utilizing the bit-flipping decoding of LDPC code, this case proposes the Hard decision decoding side of the LDPC code of a kind of dynamic threshold bit reversal Method.Idiographic flow is as shown in Figure 2.
In the Hard decision decoding device of LDPC code, the setting of bit reversal threshold value T, rises the Hard decision decoding of LDPC code Vital effect, it affects error correcting capability and its decoding rate of LDPC code.
If what bit reversal threshold value T set crosses conference increases the iterations of decoding, thus affects decoding rate.
If the too small meeting that bit reversal threshold value T sets causes upset by mistake thus to increase the iterations of decoding, Thus affect decoding rate.
For irregular check matrix, choose fixing bit reversal threshold value T, the biggest mistake can be caused like that Overturn probability thus considerably increase the iterations of decoding, cause decoding failure in severe cases.
When in sequence Z, the error rate of code element reaches certain value, fixing bit reversal threshold value T is used to decode, No matter decoder iteration is big all without successfully decoding often.
The Hard decision decoding method of the LDPC code of a kind of dynamic threshold bit reversal that this programme proposes can effectively be kept away Exempt from above-mentioned problem.The interpretation method of this patent can reduce the iterations of decoding, thus adds decoding rate;Can also carry High error correcting capability, can entangle more mistake in sequence Z.
The formula of dynamic threshold: T=j (b-c d)/a.Wherein T is threshold value, and which time iteration d is, j is row weight, a, b, c For experience normal number (mistake that constant entangles with the technique of flash memories and needs is relevant).
Wherein a, b, c are empirical, for constant, do not affect dynamic threshold " dynamically " characteristic in formula, and as initial Threshold value is i.e. regarded as the fixed threshold under normal condition, the fixed threshold that those skilled in the art determines therefrom that, by with The dependency of row weight and iterations obtains the dynamic threshold directly related with iterations and row weight, it is thus possible to effectively drop Low amount of calculation, improves decoding efficiency.Owing to experience Changshu is on " dynamically " not impact, therefore, do not repeat them here.
The row of dynamic threshold T and check matrix weigh j, which time number of times of iteration decoder is, empirical is closely bound up. The row of check matrix are heavily the ultimate values of dynamic threshold, and decoder iteration number of times more Larger Dynamic threshold value T change space is the least, experience Constant is needed the erroneous decision corrected by flash memories technique and sequence Z.The iteration of decoder each time, the code in sequence Z Unit can carry out judgement according to the dynamic threshold of each code element and decide whether to overturn, and carries out multiple code element every time and turns over Turn.
Syndrome is check matrix HmnFormula s is seen below with the result of sequence Z transposition productm
Bit reversal method specifically comprises the following steps that
A () is according to hard decision sequence Z=[z0, z1..., zN-1] calculate syndrome S=[s0, s1..., sM-1]:
s m = Σ n = 0 N - 1 H m n z n T mod 2 , m = 0 , 1 , ... , M - 1
Wherein HmnTest matrix, if syndrome S=0, stops iteration, and output hard decision sequence Z also shows successfully decoded, Otherwise enter (b).
B () is to each symbol bits zn, calculate number f of its ungratified check equations participated inn:
f n = Σ m = 0 M - 1 s m H m n , n = 0 , 1 , ... , N - 1
If fn> T, then overturn zn, obtain new hard decision sequence Z.
C () repeats (a) and (b) until successfully decoded, or reach maximum iteration time and show decoding failure;
Wherein M represents the line number of test matrix, and N represents the columns of test matrix.
It can be seen that bit reversal method is simple hard-decision method, it is only necessary to logical operations, it is achieved the simplest.

Claims (3)

1. a LDPC code Hard decision decoding method for dynamic threshold bit reversal, determines an initial turn threshold T, and it is special Levy and be, comprise the following steps:
1) read codeword sequence, calculate syndrome according to codeword sequence;
2) judge whether syndrome is zero, if zero, then stop iteration, output codons sequence;Otherwise enter step 3);
3) each symbol bits to code word each in codeword sequence, calculate the participation of this symbol bits is unsatisfactory for check equations Number;
4) turn threshold is calculated: along with increasing of iterations, turn threshold T successively decreases, and obtains current turn threshold;
5) if the number of ungratified check equations is more than current turn threshold, corresponding symbol bits overturns, and counts The syndrome of codeword sequence corresponding after calculating upset;
6) repeat step 1), 2), 3), 4) and 5), until successfully decoded, or when reaching maximum iteration time, output decoding failure.
The LDPC code Hard decision decoding method of dynamic threshold bit reversal the most according to claim 1, it is characterised in that when Front turn threshold T:
In formula: d represents current for which time iteration, j be corresponding to symbol bits when prostatitis row weight, a, b, c are experience normal number.
The LDPC code Hard decision decoding method of dynamic threshold bit reversal the most according to claim 1 and 2, determines at the beginning of one The turn threshold T begun, it is characterised in that in iteration, the step of upset is as follows:
A) according to hard decision sequenceCalculate syndrome:
WhereinTest matrix, if syndrome, stopping iteration, output hard decision sequence Z also shows successfully decoded, no Then enter b);
B) to each symbol bits, calculate the number of its ungratified check equations participated in:
If, then overturn, obtain new hard decision sequence Z;
C) repeat a) and b) until successfully decoded, or reach maximum iteration time and show decoding failure;
Hard decision sequence is the codeword sequence obtained after step 5) overturns;
Wherein M represents the line number of test matrix, and N represents the columns of test matrix.
CN201410105530.2A 2014-03-20 2014-03-20 A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal Active CN103888148B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201410105530.2A CN103888148B (en) 2014-03-20 2014-03-20 A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal
PCT/CN2014/001171 WO2015139160A1 (en) 2014-03-20 2014-12-25 Hard decision decoding method for ldpc code of dynamic threshold bit-flipping

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410105530.2A CN103888148B (en) 2014-03-20 2014-03-20 A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal

Publications (2)

Publication Number Publication Date
CN103888148A CN103888148A (en) 2014-06-25
CN103888148B true CN103888148B (en) 2016-10-26

Family

ID=50956887

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410105530.2A Active CN103888148B (en) 2014-03-20 2014-03-20 A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal

Country Status (2)

Country Link
CN (1) CN103888148B (en)
WO (1) WO2015139160A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632780B (en) * 2016-12-30 2018-08-11 慧榮科技股份有限公司 Decoding method and related apparatus

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103888148B (en) * 2014-03-20 2016-10-26 山东华芯半导体有限公司 A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal
CN104283571B (en) * 2014-09-06 2018-04-03 复旦大学 It is a kind of based on the ldpc decoder calculated at random
KR20170101368A (en) * 2016-02-26 2017-09-06 에스케이하이닉스 주식회사 Error correction circuit and error correction method
US20170288698A1 (en) * 2016-03-29 2017-10-05 Silicon Motion Inc. Power saving for bit flipping decoding algorithm in ldpc decoder
CN107423161B (en) * 2017-07-24 2019-07-02 山东华芯半导体有限公司 Applied to the adaptive LDPC code error-correcting code system and method in flash memory
US10523236B2 (en) * 2017-11-21 2019-12-31 Silicon Motion, Inc. Method employed in LDPC decoder and the decoder
US10389388B2 (en) 2017-12-28 2019-08-20 Apple Inc. Efficient LDPC decoding with predefined iteration-dependent scheduling scheme
CN110391815B (en) * 2018-04-18 2023-08-18 深圳大心电子科技有限公司 Decoding method and storage controller
CN108563534B (en) * 2018-04-24 2021-09-14 山东华芯半导体有限公司 LDPC decoding method suitable for NAND flash memory
CN109412611B (en) * 2018-09-12 2022-06-10 珠海妙存科技有限公司 Method for reducing LDPC error code flat layer
CN109347485A (en) * 2018-09-29 2019-02-15 山东存储之翼电子科技有限公司 Construct the method and LDPC code Compilation Method of LDPC check matrix
CN109660263B (en) * 2018-11-22 2022-07-05 华中科技大学 LDPC code decoding method suitable for MLC NAND flash memory
CN111435838B (en) * 2019-01-14 2022-06-14 华为技术有限公司 Decoding method, device and equipment
CN110166056B (en) * 2019-05-13 2023-04-11 武汉纺织大学 Hard decision decoding method of LDPC code based on matching pursuit
CN110752850B (en) * 2019-08-27 2023-04-07 广东工业大学 Method for quickly iterating LDPC code of MLC flash memory chip
CN110572164B (en) * 2019-09-29 2023-02-10 深圳忆联信息系统有限公司 LDPC decoding method, apparatus, computer device and storage medium
CN110661532B (en) * 2019-11-12 2023-02-10 西安电子科技大学 Symbol flipping decoding method based on multivariate LDPC code noise enhancement
US11146291B2 (en) * 2020-03-02 2021-10-12 Micron Technology, Inc. Configuring iterative error correction parameters using criteria from previous iterations
CN113364471B (en) 2020-03-05 2024-04-12 华为技术有限公司 Decoding system, decoding controller and decoding control method
CN111611101B (en) * 2020-04-22 2023-09-29 珠海妙存科技有限公司 Method and device for adjusting flash memory read data throughput rate
CN111654292B (en) * 2020-07-20 2023-06-02 中国计量大学 Dynamic threshold-based split simplified polarization code continuous elimination list decoder
CN112054809A (en) * 2020-08-28 2020-12-08 杭州华澜微电子股份有限公司 Improved TPC error correction algorithm and apparatus
CN112003626B (en) * 2020-08-31 2023-11-10 武汉梦芯科技有限公司 LDPC decoding method, system and medium based on navigation message known bits
CN113037299A (en) * 2021-03-01 2021-06-25 中国人民解放军海军航空大学航空作战勤务学院 LDPC code sparse check matrix reconstruction method and device based on iterative decoding
CN113067583B (en) * 2021-03-01 2022-05-03 中国人民解放军海军航空大学航空作战勤务学院 LDPC code length and code word starting point identification method based on minimum error decision criterion
CN114050898A (en) * 2021-11-08 2022-02-15 南京理工大学 QKD negotiation method constructed based on HLS and LDPC codes
CN114513593B (en) * 2022-01-25 2024-04-16 重庆医药高等专科学校 Mass picture acquisition working method
CN114785353A (en) * 2022-03-24 2022-07-22 山东岱微电子有限公司 Low density parity check code decoding method, system, device, apparatus and medium
CN117331743A (en) * 2022-06-24 2024-01-02 华为技术有限公司 Decoding method, chip and related device
CN116192166B (en) * 2023-04-28 2023-08-01 南京创芯慧联技术有限公司 Iterative decoding method, iterative decoding device, storage medium and electronic equipment
CN116505961B (en) * 2023-06-29 2023-09-29 深圳大普微电子科技有限公司 Decoding method and related device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004053656A1 (en) * 2004-09-10 2006-03-30 Technische Universität Dresden Signal processing system for signals with block based error protection codes has LDPC decoder in receiver end encoder in transmitter module
CN102970047A (en) * 2012-12-01 2013-03-13 电子科技大学 Low density parity check (LDPC) code weighting gradient descent bit flipping and decoding algorithm based on average amplitude
CN103281090A (en) * 2013-05-29 2013-09-04 华南理工大学 Mixed modified weighted bit-flipping LDPC decoding algorithm

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7831895B2 (en) * 2006-07-25 2010-11-09 Communications Coding Corporation Universal error control coding system for digital communication and data storage systems
CN103888148B (en) * 2014-03-20 2016-10-26 山东华芯半导体有限公司 A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004053656A1 (en) * 2004-09-10 2006-03-30 Technische Universität Dresden Signal processing system for signals with block based error protection codes has LDPC decoder in receiver end encoder in transmitter module
CN102970047A (en) * 2012-12-01 2013-03-13 电子科技大学 Low density parity check (LDPC) code weighting gradient descent bit flipping and decoding algorithm based on average amplitude
CN103281090A (en) * 2013-05-29 2013-09-04 华南理工大学 Mixed modified weighted bit-flipping LDPC decoding algorithm

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632780B (en) * 2016-12-30 2018-08-11 慧榮科技股份有限公司 Decoding method and related apparatus
US10320417B2 (en) 2016-12-30 2019-06-11 Silicon Motion Inc. Decoding method and related apparatus

Also Published As

Publication number Publication date
WO2015139160A1 (en) 2015-09-24
CN103888148A (en) 2014-06-25

Similar Documents

Publication Publication Date Title
CN103888148B (en) A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal
US20200177208A1 (en) Device, system and method of implementing product error correction codes for fast encoding and decoding
CN100581064C (en) Low density parity check code decoder and method thereof
CN106888026B (en) Segmented polarization code coding and decoding method and system based on LSC-CRC (least significant likelihood-Cyclic redundancy check) decoding
CN102412847B (en) Method and apparatus for decoding low density parity check code using united node processing
US7949932B2 (en) Strengthening parity check bit protection for array-like LDPC codes
CN102138282B (en) Reduced complexity LDPC decoder
US20090292966A1 (en) Method for recovery of lost and/or corrupted data
WO2017194013A1 (en) Error correction coding method and device
CN101405944B (en) Deletion-correcting decoding method and system of LDPC code
CN100592639C (en) Low density parity check coding method, device and parity check matrix generating method
EP2573943A1 (en) Power-optimized decoding of linear codes
US20130151932A1 (en) Method for recovery of lost data and for correction of corrupted data
US10606697B2 (en) Method and apparatus for improved data recovery in data storage systems
CN101355366B (en) Method and apparatus for decoding low density parity check code
CN102301603B (en) Coding and decoding using LDPC quasi-cyclic codes
Grinchenko et al. Improving performance of multithreshold decoder over binary erasure channel
US20160049962A1 (en) Method and apparatus of ldpc encoder in 10gbase-t system
CN109787641B (en) Method, device and storage medium for decoding sta-irecase code
CN102801432A (en) Serial FHT-BP (Fast Hartley Transform-Back Propagation) decoding method and device of multi-system LDPC (Low Density Parity Check)
US6986097B1 (en) Method and apparatus for generating parity bits in a forward error correction (FEC) system
US9350390B2 (en) Encoder, decoder and semiconductor device including the same
CN101931415B (en) Encoding device and method, decoding device and method as well as error correction system
CN101436864A (en) Method and apparatus for decoding low density parity check code
CN108234069B (en) Low-bit-rate data sending method and device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant