CN103885034A - Digital signal processing device for radar - Google Patents
Digital signal processing device for radar Download PDFInfo
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- CN103885034A CN103885034A CN201410067085.5A CN201410067085A CN103885034A CN 103885034 A CN103885034 A CN 103885034A CN 201410067085 A CN201410067085 A CN 201410067085A CN 103885034 A CN103885034 A CN 103885034A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9004—SAR image acquisition techniques
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
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- Radar, Positioning & Navigation (AREA)
- Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention belongs to the technical field of radar data processing and discloses a digital signal processing device for radar. The device comprises an FPGA chip, a first DSP chip, a second DSP chip, a third DSP chip, a fourth DSP chip, a power module and a clock module, wherein the FPGA chip is electrically connected with the first DSP chip, the second DSP chip, the third DSP chip and the fourth DSP chip through SRIO buses respectively, the first DSP chip is electrically connected with the third DSP chip through a PCI-E bus, the second DSP chip is electrically connected with the fourth DSP chip through a PCI-E bus, an HYPERLINK interface of the first DSP chip is electrically connected with an HYPERLINK interface of the second DSP chip, an HYPERLINK interface of the third DSP chip is electrically connected with an HYPERLINK interface of the fourth DSP chip, and a VPX interface is arranged on the FPGA chip.
Description
Technical field
The invention belongs to radar data processing technology field, particularly a kind of radar digital signal processing device, has realized the collaborative work of fpga chip and multiple dsp chips.
Background technology
Digital Signal Processing has been widely used in the fields such as communication, radar, sonar, remote sensing, graph and image processing and speech processes, for the two dimension becoming increasingly complex, three-dimensional even four-dimensional image processing, needs disposal system can move complicated algorithm.For the high-end devices such as communication, radar need to be within the extremely short time Treatment Analysis of settling signal, require more and more higher to processor performance, for example phonetic algorithm needs several several hundred million computings of necessarily arriving that complete per second, video and image algorithm need per secondly complete several hundred million to tens computings, and the Processing Algorithm of radar signal more needs per secondly to complete tens to hundred million computings of hundreds of.These algorithm complexes are high, real-time, and some algorithm must adopt floating-point operation just can complete, and the High speed real-time signal processing platform that therefore needs design to have stronger versatility is realized these algorithms.
Monokaryon DSP relies on the improvement of technique to promote handling property, and the integrated level of monokaryon chip improves the restriction that is subject to following factor: the restriction of physics limit, the cost of manufacture increasing progressively by geometric series, the requirement of chip processing power to power consumption, heat radiation, wire delay etc., produced bottleneck thereby single core processor performance is improved.
Summary of the invention
The object of the invention is to propose a kind of radar digital signal processing device.Can realize the digital signal processing function of high speed big data quantity.
For realizing above-mentioned technical purpose, the present invention adopts following technical scheme to be achieved.
A kind of radar comprises fpga chip, the first dsp chip to the four DSP chips with digital signal processing device, also comprises for the power module of power supply is provided to fpga chip and the first dsp chip to the four dsp chips, for the clock module of clock signal is provided to fpga chip and the first dsp chip to the four dsp chips; Described fpga chip is electrically connected respectively the first dsp chip to the four dsp chips by SRIO bus, and described the first dsp chip is by PCI-E bus electrical connection the 3rd dsp chip, and described the second dsp chip is by PCI-E bus electrical connection the 4th dsp chip; The HYPERLINK interface of described the first dsp chip is electrically connected the HYPERLINK interface of the second dsp chip, the HYPERLINK interface of HYPERLINK interface electrical connection the 4th dsp chip of described the 3rd dsp chip; On described fpga chip, be provided with VPX interface.
Feature of the present invention and further improvement are:
The model of described each dsp chip is TMS320C6678, and the model of described fpga chip is XC6VLX240T-2FFG1156I.
Each dsp chip is provided with DDR3 controller, and each dsp chip is electrically connected with SDRAM chip by DDR3 controller, and the capacity of described SDRAM chip is 1GB or 2GB.
Each dsp chip is electrically connected with NOR FLASH storer, and described fpga chip is electrically connected with FLASH storer.
Described fpga chip, the first dsp chip, the second dsp chip, the 3rd dsp chip or the 4th dsp chip are electrically connected with gigabit Ethernet mouth, and described gigabit Ethernet mouth is electrically connected with computing machine by netting twine.
Described clock module comprises crystal oscillator, the first clock generator and second clock generator, and the frequency of described crystal oscillator is 25MHz, and the model of described the first clock generator and second clock generator is CDCE62005;
Described the first clock generator is provided with input end, the first output terminal, the second output terminal and the 3rd output terminal, and described second clock generator is provided with input end, the first output terminal, the second output terminal, the 3rd output terminal and the 4th output terminal; Described the first clock generator electrical connection crystal oscillator, the input end of the first output terminal electrical connection second clock generator, the SDRAM input end of clock of the second output terminal electrical connection dsp chip, the storage subsystem input end of clock of the 3rd output terminal electrical connection dsp chip; The SRIO interface clock input end of the first output terminal electrical connection dsp chip of described second clock generator, the HYPERLINK interface clock input end of the second output terminal electrical connection dsp chip of described second clock generator, the PCI-E interface clock input end of the 3rd output terminal electrical connection dsp chip of described second clock generator, the nuclear clock input end of the 4th output terminal electrical connection dsp chip of described second clock generator.
Beneficial effect of the present invention is:
1) division of labor of dsp chip and fpga chip is clear and definite efficient, and signal is processed take 4 dsp chips as core, endorses and carries out data processing simultaneously for totally 32, and floating-point operation ability reaches as high as 512GFLOPS.Fpga chip can carry out to data on the one hand the processing in early stage, is used on the other hand configuration that dsp chip and other circuit are correlated with.
2) between fpga chip and each dsp chip, connect by SRIO bus, each dsp chip like this can be synchronously and the processing fpga chip at a high speed data of sending, last processing data later can be sent it back to fpga chip equally, carry out follow-up transmission and processing by VPX interface.
3) between 4 dsp chips, there is high-speed serial bus to carry out interconnected, can realize the data transmission between any two flexible and changeablely.
4) jtag circuit of every dsp chip is all connected to FPGA above, and the debug phase is programmed and can be debugged any one dsp chip flexibly by fpga chip like this.
5) 4 needed unsteady core voltage of dsp chip only just can realize by 1 digital PWM system controller and two digital power control drivers, have not only saved interconnection resource but also can be to the adjusting of floating of the core voltage of dsp chip.
6) clock signal of every dsp chip produces by 5 configurations of 2 clock generators, very flexible, can change by configuring each clock generator the value of any road clock, and guarantees the synchronous of several roads output clock.
7) the present invention adopts 12V single power supply, is convenient to debug.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of radar digital signal processing device of the present invention;
Fig. 2 is the structural representation of clock module of the present invention;
Fig. 3 is the First Principle schematic diagram of dsp chip power supply of the present invention;
Fig. 4 is the second principle schematic of dsp chip power supply of the present invention;
Fig. 5 is the principle schematic of fpga chip power supply of the present invention;
Fig. 6 is electric sequence schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
With reference to Fig. 1, it is the structural representation of digital signal processing device for a kind of radar of the present invention.This radar comprises fpga chip and the first dsp chip to the four dsp chips with digital signal processing device.In the embodiment of the present invention, each dsp chip adopts the 8 core TMS320C6678 of TI company, has SRIO, PCIe, Hyperlink, SGMII, DDR3, SPI interface above this DSP, can realize very abundant peripheral circuit function.Fpga chip adopts the Virtex-6 Series FPGA of Xilinx company, and model is XC6VLX240T-2FFG1156I.
In the embodiment of the present invention, 4 dsp chips adopt fully connected topology, and are connected respectively on fpga chip, are easy to realize the data communication between data communication and dsp chip and the fpga chip between multiple dsp chips.Be described as follows: each dsp chip has 4Lane SRIO interface 2Lane PCIe interface and 4Lane Hyperlink interface.Fpga chip is electrically connected respectively the first dsp chip to the four dsp chips by SRIO bus 2, and above-mentioned the first dsp chip is electrically connected the 3rd dsp chip by PCI-E bus 1, and above-mentioned the second dsp chip is electrically connected the 4th dsp chip by PCI-E bus 1; The HYPERLINK interface of above-mentioned the first dsp chip is electrically connected the HYPERLINK interface of the second dsp chip, the HYPERLINK interface of HYPERLINK interface electrical connection the 4th dsp chip of above-mentioned the 3rd dsp chip.In a word, between 4 dsp chips and fpga chip, connect and compose full interconnect architecture, between two dsp chips by SRIO interface, PCI-E interface, Hyperlink interface inter-link.Above-mentioned SRIO bus and PCI-E bus are all high-speed serial bus, and X1-Lane transfer rate reaches as high as 5Gbs/s, and Hyperlink interface is the distinctive interface of the DSP of TI company, and X1-Lane transfer rate reaches as high as 12.5Gbs/s.Interconnected by SRIO bus between each dsp chip and fpga chip.On above-mentioned fpga chip, be provided with VPX interface, can and other boards carry out between plate interconnected.According to above-mentioned annexation, fpga chip is for from the raw data of VPX interface receiving radar signal processing, and pre-stored in fpga chip and each dsp chip have a program.After fpga chip receives the raw data of Radar Signal Processing, can be according to the program of its storage, to data process or by a part of data transmission wherein to corresponding dsp chip; After dsp chip is received corresponding data, can process accordingly according to the program of storage.By the associated treatment of dsp chip and fpga chip, both can complete data handling procedure like this, draw corresponding result (as SAR imaging results).
In addition, be electrically connected with gigabit Ethernet mouth at above-mentioned fpga chip, the first dsp chip, the second dsp chip, the 3rd dsp chip or the 4th dsp chip.Now, just gigabit Ethernet mouth can be electrically connected to computing machine by netting twine, realize the information interaction of dsp chip (fpga chip) and computing machine.
In the embodiment of the present invention, each dsp chip is provided with DDR3 controller (DDR3Controler), and each dsp chip is electrically connected with SDRAM chip by DDR3 controller, and the capacity of above-mentioned SDRAM chip is 1GB or 2GB.For example, the DDR3SDRAM that SDRAM chip is Samsung, so just can guarantee the operation of dsp chip to big data quantity.
In the embodiment of the present invention, each dsp chip is electrically connected with the NOR FLASH storer of 16MB, is used for realizing the NOR FLASH of DSP is loaded.Above-mentioned fpga chip is electrically connected with the FLASH storer of 16MB.The Bit file that fpga chip can be designed program from FLASH storer loaded with hardware.88E1111 is the physical layer conversion chip that MARVELL company produces, and RJ45 selects general Ethernet interface connector.On the fpga chip using in the present invention, always have the GTX interface of 20 passages, owing to being connected the SRIO of X2-Lane with each dsp chip, exhaust the GTX interface of 8 passages, also remain 12 passages, remaining GTX all guides on VPX interface, uses as the expansion in later stage.
Take the first dsp chip electrical connection gigabit Ethernet mouth as example, the course of work of the present invention is described: fpga chip arrives any one dsp chip processing the original data transmissions that receives the Radar Signal Processing of coming, treated data are transferred to the first dsp chip again, because the first dsp chip has connected network interface, the final data after processing like this can transfer to computing machine by the network interface of the first dsp chip and carry out observations.Describe as an example of SAR imaging processing example below, the SAR imaging processing raw data that collection is come completes apart from pulse pressure and DDC(Digital Down Convert to fpga chip by VPX bus transfer), then by SRIO interface, data are transferred to respectively to 4 dsp chips, in corresponding dsp chip, first complete distance to processing, comprise the estimation of Doppler center, range curvature is proofreaied and correct and doppler frequency rate is estimated, the first dsp chip receives the data from other 3 dsp chips by Hyperlink interface afterwards, at the first dsp chip, whole data are merged, and along distance to piecemeal, then data good piecemeal are transferred to other 3 dsp chips by Hyperlink interface, then 4 dsp chips carry out respectively orientation to processing, comprise orientation motion compensation and orientation pulse pressure, other 3 dsp chips are given the first dsp chip by Hyperlink interface by the data transmission of piecemeal afterwards, in the first dsp chip, finish many Video processing and image quantization, then the first dsp chip is gone out image data transmission by network interface.
What introduce above is the interface of core processing unit of the present invention, in order to allow the present invention normally work together, needs peripheral numerous auxiliary circuit, wherein the most important thing is the design of power module and clock module, and this directly concerns serviceability of the present invention.
In the embodiment of the present invention, be also provided with for providing the power module of power supply to fpga chip and the first dsp chip to the four dsp chips and for the clock module of clock signal is provided to fpga chip and the first dsp chip to the four dsp chips.Wherein, clock module comprises crystal oscillator, the first clock generator and second clock generator, and the frequency of above-mentioned crystal oscillator is 25MHz,
With reference to Fig. 2, it is the structural representation of clock module of the present invention.Above-mentioned the first clock generator is provided with input end, the first output terminal, the second output terminal and the 3rd output terminal, and above-mentioned second clock generator is provided with input end, the first output terminal, the second output terminal, the 3rd output terminal and the 4th output terminal; Above-mentioned the first clock generator electrical connection crystal oscillator, the input end of the first output terminal electrical connection second clock generator, the second output terminal is electrically connected respectively the SDRAM input end of clock of each dsp chip, and corresponding clock output frequency is 66.667MHZ; The 3rd output terminal is electrically connected respectively the storage subsystem input end of clock (PASS) of each dsp chip, and corresponding clock output frequency is 100MHZ; The first output terminal of above-mentioned second clock generator is electrically connected respectively the SRIO interface clock input end of each dsp chip, and corresponding clock output frequency is 312.5MHZ; The second output terminal of above-mentioned second clock generator is electrically connected respectively the HYPERLINK interface clock input end of each dsp chip, and corresponding clock output frequency is 312.5MHZ; The 3rd output terminal of above-mentioned second clock generator is electrically connected respectively the PCI-E interface clock input end of each dsp chip, and corresponding clock output frequency is 100MHZ; The 4th output terminal electrical connection of above-mentioned second clock generator is electrically connected respectively the nuclear clock input end of each dsp chip, and corresponding clock output frequency is 100MHZ.In the embodiment of the present invention, the outside of fpga chip is used the high stability crystal oscillator of the SiT9102 series of another 200MHZ to input as external clock.
In the embodiment of the present invention, the model of above-mentioned the first clock generator and second clock generator is CDCE62005.CDCE62005 chip is supported multiple input clock mode, the output of You Si road, between each road, be all independently, by exporting 40KHZ to 800MHZ(LVDS to the control of its internal register) between the clock of frequency, it also supports the clock under LVPECL and LVCMOS level simultaneously.
Because the present invention uses the dsp chip that four models are TMS320C6678, deliver to two DSP so need to distribute chip through oversampling clock from CDCE62005 chip clock out.Here clock distribution chip adopts this chip of CDCLVD2104 of TI, the maximum clock incoming frequency that it is supported is 800MHZ, binary channels input, and each passage can divide away four tunnels, the feature of CDCLVD2104 chip is as follows: 1) support binary channels input, corresponding 4 tunnel outputs are inputted on every road.2) shake is very low, is less than 300fs.3) clock skew between passage output is very little, and maximum is no more than 35ps.4) incoming level of supporting has LVDS, LVPECL, LVCMOS.5) 8 road LVDS outputs, and support ANSIEIA/TIA-644A agreement.6) the highest incoming frequency of supporting is up to 800MHZ.7) support the supply voltage between 2.375 – 2.625V.
In the embodiment of the present invention, be provided with the dsp chip that 4 models of fpga chip are TMS320C6678, on fpga chip, dispose FLASH storer; Each dsp chip disposes SDRAM chip and NAND FLASH storer.Therefore the core devices that the present invention uses is more, and processor cores frequency and interface rate higher, therefore the normal operation of system to power consumption require high, be far longer than common single processor system.The good Power Management Design of embedded system is the normally key of steady operation of whole system, must meet system power dissipation requirement, and power consumption surplus need to be provided.The power type that the present invention uses has: 12V, 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1.0V.
With reference to Fig. 3, it is the First Principle schematic diagram of dsp chip power supply of the present invention; With reference to Fig. 4, it is the second principle schematic of dsp chip power supply of the present invention.In the embodiment of the present invention, above-mentioned power module comprises multiple terminal voltage stabilizers and DC/DC converter to the four DC/DC converters.Wherein, each terminal voltage stabilizer has output terminal, first input end and the second input end.The input end of the one DC/DC converter to the four DC/DC converters is all inputted 12V direct current, the model of the one DC/DC converter is PTH08T210W, its output terminal is electrically connected respectively each dsp chip, for exporting 1V direct current (electric current is 30A) to each dsp chip.The model of the 2nd DC/DC converter is PTH08T240W, and its output terminal is electrically connected respectively the first input end of each terminal voltage stabilizer, for exporting 3.3V direct current (electric current is 10A) to each terminal voltage stabilizer.The model of the 3rd DC/DC converter is PTH08T240W, and its output terminal is electrically connected respectively the second input end of each dsp chip and each terminal voltage stabilizer, for exporting 1.8V direct current (electric current is 10A) to each dsp chip and each terminal voltage stabilizer.The model of the 4th DC/DC converter is PTH08T240W, and its output terminal is electrically connected respectively each dsp chip, for exporting 1.5V direct current (electric current is 10A) to each dsp chip.The model of each terminal voltage stabilizer is PTH08T240W, and its output terminal connects a corresponding SDRAM chip, provides direct supply for exporting 0.75V direct current (electric current is 0.5A) to corresponding SDRAM chip.
Owing to also needing to supply unsteady core voltage on each dsp chip.Therefore, in embodiments of the present invention, power module also comprises digital PWM system controller, the first digital power control driver and the second digital power control driver.The model of digital PWM system controller is UCD9244, has input end, the first control end and the second control end; The model of each digital power control driver is UCD7242, has input end, the first output terminal and the second output terminal.The input end access 12V direct current of digital PWM system controller, the first control end is electrically connected the input end of the first digital power control driver, the second control end is electrically connected the input end of the second digital power control driver, and digital PWM system controller is for controlling respectively the output voltage of the first digital power control driver and the second digital power control driver.Two output terminals of two output terminals of the first digital power control driver and the first digital power control driver are corresponding connects 4 dsp chips, is used to each dsp chip that floating voltage is provided.
With reference to Fig. 5, it is the principle schematic of fpga chip power supply of the present invention.In the embodiment of the present invention, power module also comprises: the first voltage stabilizer to the five voltage stabilizers and the 5th DC/DC converter to the seven DC/DC converters.Wherein, the second voltage stabilizer has output terminal, first input end and the second input end, and the 4th voltage stabilizer has output terminal, first input end and the second input end, and the 5th voltage stabilizer has output terminal, first input end and the second input end.The model of the first voltage stabilizer is TPS54631, its input end access 12V direct current, output terminal is electrically connected respectively the first input end of the 4th voltage stabilizer and the first input end of the 5th voltage stabilizer, for exporting respectively 5V direct current (electric current is 1A) to the first input end of the 4th voltage stabilizer and the first input end of the 5th voltage stabilizer.The model of the 5th DC/DC converter is PTH08T240W, its input end access 12V direct current, and output terminal electrical connection fpga chip, for exporting 1.8V direct current (electric current is 10A) to fpga chip.The model of the 6th DC/DC converter is PTH08T240W, its input end access 12V direct current, and output terminal electrical connection fpga chip, for exporting 2.5V direct current (electric current is 10A) to fpga chip.The model of the 7th DC/DC converter is PTH08T240W, its input end access 12V direct current, and output terminal electrical connection fpga chip, for exporting 1V direct current (electric current is 10A) to fpga chip.The model of the second voltage stabilizer is TPS54620, its first input end access 12V direct current, the output terminal (access 3.3V direct current) of the second input end electrical connection the 2nd DC/DC converter, output terminal electrical connection fpga chip, for exporting 1.5V direct current (electric current is 6A) to fpga chip.The model of the 3rd voltage stabilizer is TPS73701, the output terminal (access 3.3V direct current) of its input end electrical connection the 2nd DC/DC converter, and the power input of output terminal electrical connection gigabit Ethernet mouth, for providing 1.2V direct current (electric current is 0.38A).The model of the 4th voltage stabilizer is TPS74401, the output terminal (access 3.3V direct current) of its second input end electrical connection the 2nd DC/DC converter, and output terminal electrical connection fpga chip, for providing 1.0V DC voltage (electric current is 6A).The model of the 5th voltage stabilizer is TPS74401, the output terminal (access 3.3V direct current) of its second input end electrical connection the 2nd DC/DC converter, and output terminal electrical connection fpga chip, for providing 1.2V DC voltage (electric current is 6A).
In the embodiment of the present invention, the dsp chip that model is TMS320C6678 has the requirement of strict electric sequence to operating voltage, and it has two kinds of mode of operations.One is that IO voltage is for before core voltage, another kind is that IO voltage is for after core voltage, what the embodiment of the present invention adopted is the second powering mode, specific as follows: what first need to power on is the floating voltage on dsp chip, represent with CVDD, cross 5ms for applying fixing 1.0V core voltage, keep supplying the common 1.8V IO of DSP voltage through 5ms, keep supplying the common 1.5V IO of DSP voltage through 5ms, keep supplying DDR3IO voltage 1.5V and DDR3 voltage 0.75V finally by crossing 5ms, these controls can be by the FPGA realization of programming above, because PTH08T210W chip and PTH08T240W chip have PGOOD pin and an ENA enable pin, we can reach accordingly and control accurately DSP1V, DSP1V5, DSP1V8, the power-on time of DSP0V75, floating voltage on dsp chip is realized by UCD9244 chip and two UCD7242 chips, controlling two UCD7242 chips by UCD9244 chip exports, each UCD7242 chip has two-way output, each road output can be configured to floating mode or fixed power source pattern, the 10A when maximum output current on each road, these two chips are used for supplying core voltage to the C66x series DSP of TI specially, PMBUS interface uses the Fusion Design software of host side to control UCD9244 chip, thereby configuration UCD7242 output.With reference to Fig. 6, it is electric sequence schematic diagram of the present invention.
It should be noted that, all electronic components in the present invention can be integrated on a board that meets 6U standard and realize.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (6)
1. a radar digital signal processing device, it is characterized in that, comprise fpga chip, the first dsp chip to the four dsp chips, also comprise for the power module of power supply is provided to fpga chip and the first dsp chip to the four dsp chips, for the clock module of clock signal is provided to fpga chip and the first dsp chip to the four dsp chips; Described fpga chip is electrically connected respectively the first dsp chip to the four dsp chips by SRIO bus, and described the first dsp chip is by PCI-E bus electrical connection the 3rd dsp chip, and described the second dsp chip is by PCI-E bus electrical connection the 4th dsp chip; The HYPERLINK interface of described the first dsp chip is electrically connected the HYPERLINK interface of the second dsp chip, the HYPERLINK interface of HYPERLINK interface electrical connection the 4th dsp chip of described the 3rd dsp chip; On described fpga chip, be provided with VPX interface.
2. a kind of radar digital signal processing device as claimed in claim 1, is characterized in that, the model of described each dsp chip is TMS320C6678, and the model of described fpga chip is XC6VLX240T-2FFG1156I.
3. a kind of radar digital signal processing device as claimed in claim 1, is characterized in that, each dsp chip is provided with DDR3 controller, and each dsp chip is electrically connected with SDRAM chip by DDR3 controller, and the capacity of described SDRAM chip is 1GB or 2GB.
4. a kind of radar digital signal processing device as claimed in claim 1, is characterized in that, each dsp chip is electrically connected with NOR FLASH storer, and described fpga chip is electrically connected with FLASH storer.
5. a kind of radar digital signal processing device as claimed in claim 1, it is characterized in that, described fpga chip, the first dsp chip, the second dsp chip, the 3rd dsp chip or the 4th dsp chip are electrically connected with gigabit Ethernet mouth, and described gigabit Ethernet mouth is electrically connected with computing machine by netting twine.
6. a kind of radar digital signal processing device as claimed in claim 3, it is characterized in that, described clock module comprises crystal oscillator, the first clock generator and second clock generator, the frequency of described crystal oscillator is 25MHz, and the model of described the first clock generator and second clock generator is CDCE62005;
Described the first clock generator is provided with input end, the first output terminal, the second output terminal and the 3rd output terminal, and described second clock generator is provided with input end, the first output terminal, the second output terminal, the 3rd output terminal and the 4th output terminal; Described the first clock generator electrical connection crystal oscillator, the input end of the first output terminal electrical connection second clock generator, the SDRAM input end of clock of the second output terminal electrical connection dsp chip, the storage subsystem input end of clock of the 3rd output terminal electrical connection dsp chip; The SRIO interface clock input end of the first output terminal electrical connection dsp chip of described second clock generator, the HYPERLINK interface clock input end of the second output terminal electrical connection dsp chip of described second clock generator, the PCI-E interface clock input end of the 3rd output terminal electrical connection dsp chip of described second clock generator, the nuclear clock input end of the 4th output terminal electrical connection dsp chip of described second clock generator.
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| CN106199649A (en) * | 2016-07-22 | 2016-12-07 | 中国人民解放军63908部队 | Satellite navigation receiver test platform |
| CN106226792A (en) * | 2016-07-22 | 2016-12-14 | 中国人民解放军63908部队 | Intermediate-freuqncy signal generation module |
| CN106484640A (en) * | 2015-08-29 | 2017-03-08 | 南京理工大学 | A kind of high speed serialization user interface circuit based on FPGA and DSP |
| CN109144943A (en) * | 2018-06-26 | 2019-01-04 | 深圳市安信智控科技有限公司 | Computing chip and memory chip combined system based on high-speed serial channel interconnection |
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| CN113158612A (en) * | 2020-12-25 | 2021-07-23 | 成都卓源网络科技有限公司 | Circuit structure of prototype verification platform |
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| CN106484640A (en) * | 2015-08-29 | 2017-03-08 | 南京理工大学 | A kind of high speed serialization user interface circuit based on FPGA and DSP |
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| CN109194430A (en) * | 2018-08-03 | 2019-01-11 | 中国航空工业集团公司雷华电子技术研究所 | A kind of C6678 distribution type system time synchronous method and system based on SRIO |
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| CN113158612A (en) * | 2020-12-25 | 2021-07-23 | 成都卓源网络科技有限公司 | Circuit structure of prototype verification platform |
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