CN109408151B - Automatic switching device and switching method for configuration mode of field programmable gate array - Google Patents
Automatic switching device and switching method for configuration mode of field programmable gate array Download PDFInfo
- Publication number
- CN109408151B CN109408151B CN201811295229.7A CN201811295229A CN109408151B CN 109408151 B CN109408151 B CN 109408151B CN 201811295229 A CN201811295229 A CN 201811295229A CN 109408151 B CN109408151 B CN 109408151B
- Authority
- CN
- China
- Prior art keywords
- pin
- channel switch
- mode
- switch chip
- programmable gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 21
- 230000004044 response Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000006870 function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
Abstract
An automatic switching device for configuration modes of a Field Programmable Gate Array (FPGA), comprising: a baseboard management controller; the single-channel switch chip 0 is characterized in that a selection signal end of the single-channel switch chip 0 is connected to GPIO0 of the substrate management controller, an input pin B0 of the single-channel switch chip 0 is connected to a pull-up resistor R1, an output pin B1 is connected to a pull-down resistor R2, and an output pin A is connected to a mode configuration pin M0 of the field programmable gate array; in the single-channel switch chip 1, a selection signal end of the single-channel switch chip 1 is connected to a GPIO1 of a substrate management controller, an input pin B0 of the single-channel switch chip 1 is connected to a pull-up resistor R3, an output pin B1 is connected to a pull-down resistor R4, and an output pin A is connected to a mode configuration pin M1 of a field programmable gate array. The device can realize the function of automatic switching of the FPGA configuration mode.
Description
Technical Field
The field relates to the field of computers, in particular to an automatic switching device and an automatic switching method for configuration modes of a field programmable gate array.
Background
FPGA (field Programmable Gate array), namely a field Programmable Gate array, has the characteristics of high Programmable flexibility, short development period and high parallel computing efficiency. The array of internal logic can be customized by the user at will, and the user can perform instant programming on site to modify the internal hardware logic to realize any logic function. Therefore, FPGAs are becoming more and more widely used in server board design.
The FPGA configuration mode is flexible and various, and is divided into a master mode, a slave mode and a JTAG mode according to whether the chip can actively load configuration data. A typical master mode is to load a configuration bitstream in an off-chip non-volatile memory (power-off non-loss data, such as an SPI flash), the clock signals required for configuration are generated internally by the FPGA, and the FPGA controls the whole configuration process. The slave mode requires an external master intelligent terminal (e.g., processor, microcontroller, etc.) to download data into the FPGA. The JTAG mode is a debugging mode, and can download the bit file stream in the PC into the FPGA, and the bit file stream is lost when the power is cut off. In one type of board card design, the FPGA needs to support a master mode, a slave mode and a JTAG debug mode at the same time, the selection of different modes of the FPGA is determined according to the level of a mode configuration pin M [1:0], wherein the JTAG mode is not controlled by the configuration pin M [1:0] and is supported under any condition.
In the prior art (as shown in FIG. 1), to support master, slave, and JTAG configuration modes simultaneously, this is accomplished by reserving pull-down resistors R1-R4 on the M [1:0] outsides. When the master mode needs to be supported, the resistors R4 and R1 are powered on, and R2 and R3 are not powered on, namely M [1:0] ═ 01; when the slave mode needs to be supported, the resistors R1 and R3 are powered on, and R2 and R4 are not powered on, namely M [1:0] ═ 11. JTAG mode is not controlled by M [1:0] and is supported at all times.
Although the prior art can meet the requirement of simultaneously supporting three configuration modes, the method has certain defects that the switching of different modes needs to be realized through welding resistors, the method needs to power off the machine and take out the board card from the chassis for operation, and the switching difficulty and complexity are increased.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide an automatic switching device and a switching method for a field programmable gate array configuration mode, which can implement an automatic switching function of an FPGA configuration mode, and have the advantages of flexible switching and simple operation.
In view of the above object, an aspect of the embodiments of the present invention provides an automatic switching apparatus for configuration mode of a field programmable gate array, including:
a baseboard management controller;
the single-channel switch chip 0 is characterized in that a selection signal end of the single-channel switch chip 0 is connected to GPIO0 of the substrate management controller, an input pin B0 of the single-channel switch chip 0 is connected to a pull-up resistor R1, an output pin B1 is connected to a pull-down resistor R2, and an output pin A is connected to a mode configuration pin M0 of the field programmable gate array; and
in the single-channel switch chip 1, a selection signal end of the single-channel switch chip 1 is connected to a GPIO1 of a substrate management controller, an input pin B0 of the single-channel switch chip 1 is connected to a pull-up resistor R3, an output pin B1 is connected to a pull-down resistor R4, and an output pin A is connected to a mode configuration pin M1 of a field programmable gate array.
According to one embodiment of the present invention, the GPIO0 and the GPIO1 of the bmc may each output a high level and a low level to the selection signal terminal, respectively.
According to an embodiment of the present invention, the single-channel switch chip 0 and the single-channel switch chip 1 have the same structure, and the input pin B1 is connected to the output pin a when the selection signal terminal inputs a high level, and the input pin B0 is connected to the output pin a when the selection signal terminal inputs a low level.
According to an embodiment of the present invention, when the GPIO0 of the baseboard management controller outputs a low level and the GPIO1 outputs a high level, the mode configuration pin M0 is at a high level, the mode configuration pin M1 is at a low level, and the configuration mode of the field programmable gate array is switched to the main mode.
According to an embodiment of the present invention, when the GPIO0 of the baseboard management controller outputs a low level and the GPIO1 outputs a low level, the mode configuration pin M0 is high level, the mode configuration pin M1 is high level, and the configuration mode of the field programmable gate array is switched to the slave mode.
According to one embodiment of the invention, the mode of the field programmable gate array is switched according to the high and low of the levels of the mode configuration pin M0 and the mode configuration pin M1.
According to one embodiment of the invention, the mode of the field programmable gate array comprises: master mode, slave mode, and JTAG mode.
In another aspect of the embodiments of the present invention, there is also provided a method for automatically switching configuration modes of a field programmable gate array, where the method includes the following steps:
1) receiving an instruction for switching to a main mode;
2) enabling the GPIO0 of the baseboard management controller to output low level and enabling the GPIO1 of the baseboard management controller to output high level according to the instruction;
3) in response to the low level of the GPIO0 and the high level of the GPIO1 respectively received by the selection signal terminals of the single-channel switch chip 0 and the single-channel switch chip 1, the input pin B0 of the single-channel switch chip 0 is communicated with the output pin A, the M0 is pulled to the high level through the pull-up resistor R1, meanwhile, the input pin B1 of the single-channel switch chip 1 is communicated with the output pin A, and the M1 is pulled to the low level through the pull-down resistor R4.
According to one embodiment of the invention, the method further comprises the steps of:
1) receiving an instruction to switch to a slave mode;
2) enabling the GPIO0 of the baseboard management controller to output low level according to the instruction, and enabling the GPIO1 of the baseboard management controller to output low level;
3) in response to the selection signal terminals of the single-channel switch chip 0 and the single-channel switch chip 1 respectively receiving the low level of the GPIO0 and the low level of the GPIO1, the input pin B0 of the single-channel switch chip 0 is communicated with the output pin A, the M0 is pulled to be high level through the pull-up resistor R1, meanwhile, the input pin B0 of the single-channel switch chip 1 is communicated with the output pin A, and the M1 is pulled to be high level through the pull-up resistor R3.
In another aspect of the embodiments of the present invention, there is also provided a field programmable gate array, which includes the above apparatus.
The invention has the following beneficial technical effects: the automatic switching device and the switching method for the configuration mode of the field programmable gate array provided by the embodiment of the invention have the advantages that a substrate management controller is added; the system comprises a single-channel switch chip 0, a GPIO0 of a substrate management controller is connected to a selection signal end of the single-channel switch chip 0, an input pin B0 of the single-channel switch chip 0 is connected to a pull-up resistor R1, an output pin B1 is connected to a pull-down resistor R2, and an output pin A is connected to a mode configuration pin M0 of the field programmable gate array; the technical scheme includes that the single-channel switch chip 1 is connected with a GPIO1 of the substrate management controller to a selection signal end of the single-channel switch chip 1, an input pin B0 of the single-channel switch chip 1 is connected to a pull-up resistor R3, an output pin B1 is connected to a pull-down resistor R4, and an output pin A is connected to a mode configuration pin M1 of the field programmable gate array.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a prior art switching scheme for a configuration mode of a field programmable gate array;
fig. 2 is a schematic diagram of an automatic switching apparatus for configuration mode of a field programmable gate array according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating switching of master modes of a field programmable gate array according to another embodiment of the present invention;
fig. 4 is a schematic diagram of switching from mode of a field programmable gate array according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention proposes an embodiment of an automatic switching apparatus for configuration mode of a field programmable gate array. Fig. 2 shows a schematic view of the device.
As shown in fig. 2, the apparatus includes:
a Baseboard Management Controller (BMC);
a single-channel switch (switch) chip 0, wherein a Selection (SEL) signal end of the single-channel switch chip 0 is connected to a GPIO0 of the substrate management controller, an input pin B0 of the single-channel switch chip 0 is connected to a pull-up resistor R1, an output pin B1 is connected to a pull-down resistor R2, and an output pin A is connected to a mode configuration pin M0 of the field programmable gate array; and
in the single-channel switch chip 1, a selection signal end of the single-channel switch chip 1 is connected to a GPIO1 of a substrate management controller, an input pin B0 of the single-channel switch chip 1 is connected to a pull-up resistor R3, an output pin B1 is connected to a pull-down resistor R4, and an output pin A is connected to a mode configuration pin M1 of a field programmable gate array.
Through the technical scheme, the function of automatic switching of the FPGA configuration mode can be realized, and the method has the advantages of flexible switching and simple operation.
In a preferred embodiment of the present invention, the single-channel switch chip 0 and the single-channel switch chip 1 have the same structure, and the input pin B1 is connected to the output pin a when the selection signal terminal inputs a high level, and the input pin B0 is connected to the output pin a when the selection signal terminal inputs a low level.
In a preferred embodiment of the present invention, when the GPIO0 of the baseboard management controller outputs a low level and the GPIO1 outputs a high level, the mode configuration pin M0 is at a high level, the mode configuration pin M1 is at a low level, and the configuration mode of the field programmable gate array is switched to the master mode. According to an embodiment of the present invention, when the GPIO0 of the baseboard management controller outputs a low level and the GPIO1 outputs a low level, the mode configuration pin M0 is high level, the mode configuration pin M1 is high level, and the configuration mode of the field programmable gate array is switched to the slave mode.
In a preferred embodiment of the present invention, the mode of the field programmable gate array may be switched according to the high and low of the levels of the mode configuration pin M0 and the mode configuration pin M1. The modes of the field programmable gate array include: master mode, slave mode, and JTAG mode.
In the technical scheme, the switch0 chip is used for switching the input level of an M [0] pin, the switch1 chip is used for switching the input level of an M [1] pin, and GPIOs 0-1 of BMC are used for respectively controlling SEL signals of the switches 0-1. The working principle of the switch chip is that when the SEL signal is at high level, A is B1; when the SEL signal is low, a equals B0. When the FPGA needs to support the master mode, GPIO0 is 0, that is, switch0 chip a is B0, and the M [0] pin is pulled up to a high level through a resistor R1; GPIO1 is 1, i.e. switch1 chip a is B1, and M [1] pin is pulled down to low level through resistor R4; and enabling M [1:0] to be 01, so that the FPGA configuration mode is switched to the main mode. When the FPGA needs to support the slave mode, GPIO0 is 0, that is, switch0 chip a is B0, and the M [0] pin is pulled up to a high level through a resistor R1; GPIO1 is 0, that is, switch1 chip A is B0, M [1] pin is pulled up to high level through resistor R3; and M [1:0] is set to be 11, so that the FPGA configuration mode is switched to the slave mode. JTAG mode does not need GPIO 0-1 configuration, and is supported under any condition. Compared with the prior art, the scheme has the characteristics of flexible switching and simple operation, and reduces the switching difficulty among different modes.
In view of the above object, a second aspect of the embodiments of the present invention further provides a method for automatically switching configuration modes of a field programmable gate array, where the method uses the above apparatus to implement the following steps:
1) receiving an instruction for switching to a main mode;
2) enabling the GPIO0 of the baseboard management controller to output low level and enabling the GPIO1 of the baseboard management controller to output high level according to the instruction;
3) in response to the low level of the GPIO0 and the high level of the GPIO1 respectively received by the selection signal terminals of the single-channel switch chip 0 and the single-channel switch chip 1, the input pin B0 of the single-channel switch chip 0 is communicated with the output pin A, the M0 is pulled to the high level through the pull-up resistor R1, meanwhile, the input pin B1 of the single-channel switch chip 1 is communicated with the output pin A, and the M1 is pulled to the low level through the pull-down resistor R4.
In a preferred embodiment of the invention, the method further comprises the steps of:
1) receiving an instruction to switch to a slave mode;
2) enabling the GPIO0 of the baseboard management controller to output low level according to the instruction, and enabling the GPIO1 of the baseboard management controller to output low level;
3) in response to the selection signal terminals of the single-channel switch chip 0 and the single-channel switch chip 1 respectively receiving the low level of the GPIO0 and the low level of the GPIO1, the input pin B0 of the single-channel switch chip 0 is communicated with the output pin A, the M0 is pulled to be high level through the pull-up resistor R1, meanwhile, the input pin B0 of the single-channel switch chip 1 is communicated with the output pin A, and the M1 is pulled to be high level through the pull-up resistor R3.
When the FPGA needs to support the main mode: the BMC controls GPIO0 to be 0, namely, a switch0 chip A is B0, and an M [0] pin is pulled up to a high level through a resistor R1; GPIO1 is 1, i.e. switch1 chip a is B1, and M [1] pin is pulled down to low level through resistor R4; and enabling M [1:0] to be 01, so that the FPGA configuration mode is switched to the main mode. The FPGA master mode switching control is shown in FIG. 3.
When the FPGA needs to support the slave mode: the BMC controls GPIO0 to be 0, namely, a switch0 chip A is B0, and an M [0] pin is pulled up to a high level through a resistor R1; GPIO1 is 0, that is, switch1 chip A is B0, M [1] pin is pulled up to high level through resistor R3; and M [1:0] is set to be 11, so that the FPGA configuration mode is switched to the slave mode. The FPGA mode switching control is shown in FIG. 4.
It should be particularly noted that the embodiment of the system described above employs the embodiment of the method described above to specifically describe the working process of each module, and those skilled in the art can easily think that the modules are applied to other embodiments of the method described above.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
The embodiments described above, particularly any "preferred" embodiments, are possible examples of implementations and are presented merely to clearly understand the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (10)
1. An automatic switching device for configuration modes of a Field Programmable Gate Array (FPGA), comprising:
a baseboard management controller;
the single-channel switch chip 0 is characterized in that a selection signal end of the single-channel switch chip 0 is connected to a GPIO0 of the baseboard management controller, an input pin B0 of the single-channel switch chip 0 is connected to a pull-up resistor R1, an output pin B1 is connected to a pull-down resistor R2, and an output pin A is connected to a mode configuration pin M0 of the field programmable gate array; and
the single-channel switch chip 1 is characterized in that a selection signal end of the single-channel switch chip 1 is connected to a GPIO1 of the baseboard management controller, an input pin B0 of the single-channel switch chip 1 is connected to a pull-up resistor R3, an output pin B1 of the single-channel switch chip 1 is connected to a pull-down resistor R4, and an output pin A of the single-channel switch chip is connected to a mode configuration pin M1 of the field programmable gate array.
2. The device of claim 1, wherein the GPIO0 and GPIO1 of the baseboard management controller each output a high level and a low level, respectively, to the select signal terminal.
3. The apparatus of claim 2, wherein the single-channel switch chip 0 and the single-channel switch chip 1 are identical in structure, and wherein the input pin B1 is connected to the output pin a when the signal terminal is selected to be inputted with a high level, and the input pin B0 is connected to the output pin a when the signal terminal is selected to be inputted with a low level.
4. The apparatus of claim 3, wherein when the GPIO0 of the baseboard management controller outputs a low level and GPIO1 outputs a high level, the mode configuration pin M0 is high, the mode configuration pin M1 is low, and the configuration mode of the field programmable gate array is switched to a master mode.
5. The apparatus of claim 3, wherein when the GPIO0 of the baseboard management controller outputs a low level and GPIO1 outputs a low level, the mode configuration pin M0 is high, the mode configuration pin M1 is high, and the configuration mode of the field programmable gate array is switched to a slave mode.
6. The apparatus of claim 1, wherein the mode of the field programmable gate array is switched according to the high and low of the levels of the mode configuration pin M0 and the mode configuration pin M1.
7. The apparatus of claim 6, wherein the pattern of the field programmable gate array comprises: master mode, slave mode, and JTAG mode.
8. A method for automatic switching of configuration modes of a field programmable gate array, characterized in that the following steps are implemented using the apparatus according to any of claims 1-7:
1) receiving an instruction for switching to a main mode;
2) enabling the GPIO0 of the baseboard management controller to output a low level and enabling the GPIO1 of the baseboard management controller to output a high level according to the instruction;
3) in response to the selection signal terminals of the single-channel switch chip 0 and the single-channel switch chip 1 respectively receiving the low level of the GPIO0 and the high level of the GPIO1, the input pin B0 of the single-channel switch chip 0 is communicated with the output pin A, the M0 is pulled to the high level through the pull-up resistor R1, meanwhile, the input pin B1 of the single-channel switch chip 1 is communicated with the output pin A, and the M1 is pulled to the low level through the pull-down resistor R4.
9. The method of claim 8, further comprising the steps of:
1) receiving an instruction to switch to a slave mode;
2) enabling the GPIO0 of the baseboard management controller to output a low level according to the instruction, and enabling the GPIO1 of the baseboard management controller to output a low level;
3) in response to the selection signal terminals of the single-channel switch chip 0 and the single-channel switch chip 1 respectively receiving the low level of the GPIO0 and the low level of the GPIO1, the input pin B0 of the single-channel switch chip 0 is communicated with the output pin A, the M0 is pulled to be high level through the pull-up resistor R1, meanwhile, the input pin B0 of the single-channel switch chip 1 is communicated with the output pin A, and the M1 is pulled to be high level through the pull-up resistor R3.
10. A field programmable gate array, characterized in that it comprises an apparatus according to any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811295229.7A CN109408151B (en) | 2018-11-01 | 2018-11-01 | Automatic switching device and switching method for configuration mode of field programmable gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811295229.7A CN109408151B (en) | 2018-11-01 | 2018-11-01 | Automatic switching device and switching method for configuration mode of field programmable gate array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109408151A CN109408151A (en) | 2019-03-01 |
| CN109408151B true CN109408151B (en) | 2021-10-29 |
Family
ID=65471226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811295229.7A Active CN109408151B (en) | 2018-11-01 | 2018-11-01 | Automatic switching device and switching method for configuration mode of field programmable gate array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109408151B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111103827B (en) * | 2019-12-06 | 2021-06-29 | 苏州浪潮智能科技有限公司 | Server working mode switching device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582688A (en) * | 2008-05-15 | 2009-11-18 | 中兴通讯股份有限公司 | Dynamic configuration circuit with FPGA loading mode |
| CN104504975A (en) * | 2014-12-29 | 2015-04-08 | 清华大学 | Portable comprehensive electronic experimental platform on basis of field programmable gate arrays |
| CN104836959A (en) * | 2015-05-15 | 2015-08-12 | 华南师范大学 | FPGA-based Multi-mode automatic switchover collection system of array CMOS image sensor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7013232B2 (en) * | 2001-08-15 | 2006-03-14 | National Insurance Corporation | Network-based system for configuring a measurement system using configuration information generated based on a user specification |
| CN104899179A (en) * | 2015-04-03 | 2015-09-09 | 浪潮电子信息产业股份有限公司 | Method for designing multi-path server QPI clamp based on converged infrastructure |
-
2018
- 2018-11-01 CN CN201811295229.7A patent/CN109408151B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582688A (en) * | 2008-05-15 | 2009-11-18 | 中兴通讯股份有限公司 | Dynamic configuration circuit with FPGA loading mode |
| CN104504975A (en) * | 2014-12-29 | 2015-04-08 | 清华大学 | Portable comprehensive electronic experimental platform on basis of field programmable gate arrays |
| CN104836959A (en) * | 2015-05-15 | 2015-08-12 | 华南师范大学 | FPGA-based Multi-mode automatic switchover collection system of array CMOS image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109408151A (en) | 2019-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102508533B (en) | Reset control device and method | |
| US9250690B2 (en) | Low-power modes of microcontroller operation with access to configurable input/output connectors | |
| US20120137159A1 (en) | Monitoring system and method of power sequence signal | |
| CN111103827B (en) | Server working mode switching device | |
| CN210986071U (en) | Digital signal interface circuit, chip and electronic equipment | |
| JP4209771B2 (en) | General purpose computer architecture | |
| CN110399328B (en) | Control method and device for board-mounted graphics processor | |
| CN109408151B (en) | Automatic switching device and switching method for configuration mode of field programmable gate array | |
| CN106066453A (en) | String line debugging bridge | |
| CN211349065U (en) | Integrated circuit and processing system | |
| CN110618744A (en) | Novel GPU Carrier board card | |
| CN210038710U (en) | Power supply switching circuit and server | |
| CN110190841B (en) | IO port multiplexing control circuit and electronic equipment | |
| CN114020669B (en) | CPLD-based I2C link system and server | |
| CN211015473U (en) | Upgrade configuration logic circuit, programmable logic device and upgrade configuration system | |
| CN108009113B (en) | Method for realizing debugging serial port in double-master control system | |
| CN115933846A (en) | Resetting method, terminal equipment and chip | |
| CN111857310A (en) | Power supply system and method for components | |
| JP2004185619A (en) | System and method for switching clock source | |
| CN106936518B (en) | Measuring device with bidirectional IO function | |
| CN218768136U (en) | Device for switching I2C bus by using programmable logic device | |
| CN110096124A (en) | A kind of configuration method and device of multiple nucleus system | |
| US11614931B2 (en) | Online software upgrade device and method for maintaining operation uninterrupted | |
| CN211087224U (en) | Mainboard and computer equipment | |
| JP2002169602A (en) | General-purpose functional circuit and general-purpose unit for programmable controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |