CN103781085B - A kind of multiband TETRA Digital Clusterings detection method and device - Google Patents
A kind of multiband TETRA Digital Clusterings detection method and device Download PDFInfo
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Abstract
The invention discloses the detection method of a kind of multiband TETRA Digital Clusterings detection means and its use device.The multiband receiver radio frequency front end, Digital IF Processing plate, reference source, secondary power supply, it is characterised in that：The multiband receiver radio frequency front end receives the multiple signals in any one frequency range simultaneously；The Digital IF Processing plate is responsible for receiving the processing of data and the control of complete machine, and provides external interface；The reference source provides reference clock；The secondary power supply provides working power for above each several part.The implementation complexity and production cost of TETRA Digital Clustering detection means can be reduced using the present invention, and improve anti-interference.
Description
Technical field
The present invention relates to TETRA（Terrestrial trunked radio）Digital cluster communication, more particularly to a kind of multiband TETRA numbers
Word cluster detection method and device.
Background technology
TETRA digital clustering communication systems are a kind of based on digital tdma（TDMA）The wireless colony movement of technology is logical
Letter system.The system is ETSI（ETS association）Department, manufacturer, detection department or even portion of government is used in combination
Door, in order to meet the specialized departments of European Countries to mobile communication the need for design, work out the open system of unified standard.
TETRA digital clustering communication systems can provide command scheduling, data transfer and telephone service on same technology platform, and it is not only
The scheduling feature of many groups is provided, but also short data information service, packet data service and digitized complete can be provided
Duplexing mobile phone service.
Prime information Estate Division issued China on December 28th, 2000《Digital Clustering GSM system》（SJ/
T11228-2000）Standard, this is the recommendatory ministry standard of an electronics industry, and TETRA systems are determined in the standard
With two kinds of systems of iDEN systems.The Ministry of Public Security in 2003 has formulated 350MHz TETRA professional standards, and in succession in Guangzhou, Shenzhen
Try net has been set up with Zhuhai.
TERTA digital cluster systems at home and abroad railway, subway, light rail, airport, harbour water conservancy, public security, safety, army
The application of Dui Deng specialized departments.At present, urban track traffic（For example：Subway, light rail and suburban railway）It is that China is maximum
Professional TETRA digital trunk networks.Up to now, China's track traffic urban track traffic uses more than 1400 base station and more than 150
Individual interchanger, possesses more than 31000 user terminal.
To meet the World College Students Games in 2011,69 base stations and 2 interchangers have been built by Shenzhen Municipal Public Security Bureau
350MHz TETRA Digital Clustering private networks, the network can accommodate 25000 users.At present, Qingdao public security bureau builds 40
Multiple base stations and the 350MHz TETRA Digital Clustering private networks of 2 interchangers, the network can accommodate 3 general-purpose families.
To meet the 2008 Beijing Olympic Games, the larger rule of more than 300 base station and 6 interchangers have been built by Zheng Tong companies
Mould 800MHz TETRA Digital Clustering common networks, the network can accommodate 9 general-purpose families, and current network has more than 70,000 user.To meet
The Guangzhou Asian Games in 2010, the 800MHz TETRA Digital Clusterings for having built 179 base stations and 2 interchangers by Guangdong Telecom are total to
Net, the network can accommodate 5 general-purpose families.
The mission-critical scheduling feature of TETRA Digital Clusterings and reliable networking capability are the Olympic Games, World Expo, the Asian Games
Meeting, Games for university students etc. provide thousands of phone groups, and flexibly across tissue horizontal coordination communication, vehicle location, individual can be achieved
People positions, and short message and packet data application.The big traffic that Opening and closing ceremonies and accident for occasion are produced
The impact to network is measured, TETRA can provide optimal solution and counter-measure.
Because TETRA is an open international standard, numerous enterprises and institute has been attracted directly to participate in TETRA productions
The research and production of product.Domestic unit has Harbin Institute of Technology, Beijing Jiaotong University, Beijing Institute of Technology, Qingdao Hisense collection
Group, Tianjin Communications broadcast group, Wuhan Central Plains communication group, company of EastCom, institute of group company of ZhongDian Science ＆ Technology 7 and 54 institutes,
Shanghai San Ji companies, wide 1 Haige Co., Shenzhen Hai Nengda companies, Shenzhen Kirisun company, Beijing Shou Ke software companys and Hangzhoupro
Zhou Youneng companies etc. successively put into TETRA was researched and developed and produced to strength system and terminal.And the TETRA systems of overseas enterprise
System and terminal, such as TETRA of the TETRA systems of France CASsIDIAN (NOKIA, EADS) company, DAMM companies of Denmark-
FLEX systems, the DIMETRA systems of MOTOROLA companies of the U.S., TETRA-NODE systems of ROHILL companies of Holland, Germany
The ACCESSNET systems of ROHDESCHWARZ companies, the ACCESSNET systems of SIEMENS companies of Germany, THALEs companies of France
TETRA systems, the ELETTRA systems of Italy SELEX (OTE, MARCONI) company, TEAM SIMOCO companies of Britain
TETRA terminals of TETRA/G systems, the NEBULA systems of TELTRONIC companies of Spain and SEPURA companies of Britain etc. are manufactured
TETRA equipment largely all passed through the detection at the Ministry of Industry and Information Technology of China radio monitoring center, and obtain wireless
The Type Approval of electric management board.
Due to TETRA digital colony networks various countries all over the world, the reality that each country manages according to oneself National Radio
Border situation, is assigned with different TETRA Digital Clustering frequencies, and table 1 gives the distribution of domestic and international TETRA Digital Clusterings frequency.
The distribution of the domestic and international TETRA Digital Clusterings frequency of table 1
No matter the operation of TETRA digital colony networks, or TETRA digital packet terminals and system（Base station and interchanger）
Exploitation, be required for a kind of multiband TETRA Digital Clustering detection means, TETRA digital colony networks and institute to operation
The base station of exploitation and terminal are detected, it is ensured that runed TETRA digital colony networks safety and available, supported TETRA numerals
Signaling protocol during the protocal analysis of group system and terminal development, display TETRA digital packet terminals and intersystem communications
Complicated Flow details.
Prior art one related to the present invention
The technical scheme of prior art one
Prior art source：Patent application, application number 200910258707.1.Publication number：CN102096079A.
The patent belongs to radio frequency communication technical field, is related to satellite navigation receiver RF front-end circuit, especially
It is related to and recognizes method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and its module.
A kind of configurable multimode multi-frequency section satellite navigation receiver method and its RF front-end module are which disclose,
RF front-end module can receive GPS, the Big Dipper, Galileo and GLONASS satellite navigation and location system signal, the module bag
Include the configurable LNA with Buffer and active Balun, the configurable multi-mode wave filter of band, automatic gain control amplifier AGC
With the bigoted circuit of direct current, include the switch control word of the multi mode multi band programmed code from reception system.By receiving
The control word of System Programming, front-end module can meet multiband and multi-mode working, be inputted with one-channel signal, two paths of differential signals
Output, RF front-end circuit composition is simple and reliable, is not required to the time division multiplexing control system and piece outer mold piece of complexity, and cost is low, spirit
Activity is good, improves the noiseproof feature and multi mode multi band signal handling capacity of whole receiver radio frequency front end.
Fig. 1 shows that a kind of multi mode multi band RF front-end circuit constitutes block diagram, mainly preposition by configurable low noise
Amplifier LNA11, buffer Buffer12, active single turn double change end-apparatus Balun13, two frequency mixers 14 and 16, configurable frequencies
Rate synthesizer 15, configurable multimode wave filter 17 and broadband automatic gain control amplifier AGC18 compositions.
Put before receiving the configurable low-noise preamplifier LNA11 of radiofrequency signal RFIN accesses input, low noise
Big device LNA11, buffer Buffer12, active single turn it is double change end-apparatus Balun13 single-ended connections successively, it is active to change end-apparatus
Balun13 two difference output ends connect the input of frequency mixer 14 and 16 respectively, can configure what frequency synthesizer 15 was exported
Difference local oscillation signal " I " and " Q " connect the local oscillation signal input of respective mixers 14 and 16, the difference sheet that frequency mixer 14 is exported
The difference radio-frequency signal " Q " that signal " I " and frequency mixer 16 export that shakes connects the input of corresponding configurable filter 17 respectively,
The difference radio-frequency signal " I " and " Q " output end of configurable filter 17 connect automatic gain control amplifier AGC18 difference respectively
Divide input, automatic gain control amplifier AGC18 difference output " I " and " Q " end, by multi mode multi band radio-frequency front-end mould
The front radio-frequency output signal REOUT of block output delivers to follow-up circuit module.
The shortcoming of prior art one
（1）Prior art is related to more than the working frequency 1GHz of satellite navigation receiver radiofrequency signal, and TETRA is digital
Cluster detection means working frequency is in 300MHz~900MHz, so the method for prior art is not suitable for the inspection of TETRA Digital Clusterings
Survey device.
（2）The modulation system and radio frequency reception index that prior art is related to satellite navigation receiver radiofrequency signal can not
Meet the requirement of TETRA Digital Clusterings detection means.
（3）Prior art is not directed to whole receiver apparatus, relates only to satellite navigation receiver RF front-end circuit.
Prior art two related to the present invention
The technical scheme of prior art two
Prior art source：Electronic device (Chinese Jourml of Electron Device) periodical, 2006
Volume 29, the 3rd phase.
A kind of base station receiver for TETRA digital cluster systems is designed, Wang Jingning, and (Harbin industry is big by Tan Xuezhi
Learn Research on Communication Technology institute, Harbin 150001)
Paper is directed to requirement of the special mobile mobile communication to receiver, analyzes base station receiver skill in TETRA agreements
Art index and selection dual IF superhet scheme.Noise coefficient and gain distribution are carried out to each several part, and from full
The middle and small scale integrated device that foot is required, carries out circuit design and the realization of receiver.
Using the receiver of superhet dual IF structure, the first intermediate frequency selects 70MHz, and the second intermediate frequency selects l0.7MHz.It is selected
Property it is good, dynamic range is big, and noise coefficient is low, and mirror image suppresses, and Fig. 2 shows the structured flowchart of receiver.
Receiver is functionally divided into four parts：Radio-frequency front-end, intermediate frequency amplification, demodulation, automatic power gain control.Respectively
The noise coefficient and gain of level are as shown in Figure 2.
（1）First local frequency is 876~891MHz, and Image interference occurs on 810+2*70=950MHz, in order to
Solve this problem, it is necessary to add wave filter BPF1 before low-noise amplifier, BPF1 function is just filled by duplexer here
When loss is small, and the influence to overall noise figure is small.
（2）The selection of noise coefficient
[NF]=[NF]1+([NF]2-1)/G1+([NF]3-1)/G1G2+......
Above formula is the calculation formula of total noise coefficient of receiver.From formula, overall noise figure mainly depends on
In first order amplifying circuit LNA, it is desirable to which its noise coefficient is low.General way is：[NF]2About 2dB, while G1At least
[NF]2Than big 3dB.
（3）Side channel suppresses
Accomplish 25kHz bandwidth on 800MHz radio frequencies, the Q values of wave filter are impossible to accomplish, can only be in intermediate frequency and low
The filtering of 25kHz bandwidth is realized on frequency.The general side channel that can only accomplish 30dB on 10.7MHz intermediate frequency suppresses.Base band
Processing use CMX980A, it can make 25kHz attenuation outside a channel fall 60dB, and such neighboring trace suppresses that desired 45dB can be exceeded.
But so the problem of be the power detection that is carried out on intermediate frequency to be not to receive actual power on channel, it is necessary in power inspection
Survey branch road and connect a wave filter again, obtain 60dB suppression.
Low-noise amplifier selects AGB330.RF mixer selects AD8344, the AD8344 of Analog Device companies
It is a kind of high performance frequency mixer, it is designed primarily directed to radio infrastructure, using gilbert's structure, radio frequency frequency
Bandwidth, noise is low, and the linearity is high, and Intermodulation Interference is small, low in energy consumption, and Signal segregation degree is high, outside can turn off.
Intermediate frequency puts amplifier and selects MC1496, and this is the product of motorola inc, and it is 35dB in the 60MHz gains for being,
Noise coefficient 6dBmAGC scopes reach 60dB, and power consumption only 204mw, also acts as frequency mixer when l2V powers.Using being put in two
MC1496, can arrive 120dB AGC controls.
First local frequency synthesis selection ADF4360-7, frequency range is 350~1800MHz.Its advantage be collection VCO with
PLL is in a chip, and peripheral cell is few, and oscillation center frequency is determined by internal varactor and two inductance of periphery.
Supply voltage is 3.0~3.6V, and output level may be programmed, 3-line serial interface.Second local frequency synthesis selection ADF4001 is done
PLL, is VCO of the oscillator being carried on ADS344, the ADF4001 bandwidth with 200MHz, and supply voltage is 2.7~
5.5V, current programmable control, 3-line serial interface, power can software or hardware controls, extremely low noise.
Quadrature demodulator selects Marconi company RF2721, and it is widely used in VHF receiver, with a width of
100kHz~500MHz, its supply voltage is the active part that oscillator is carried on 5V, chip, is exported simultaneous with digital analog converter
Hold, extremely low local oscillation power requirement, power can be digital control.
The shortcoming of prior art two
（1）The working frequency that prior art is related to the base station receiver of TETRA digital cluster systems is 800MHz, and
TETRA Digital Clustering detection means working frequency is 300MHz~900MHz, so the method for prior art is not suitable for multiband
TETRA Digital Clustering detection means.
（2）Prior art only relates to the radio frequency operation principle of the base station receiver of TETRA digital cluster systems, not to base band
The scheme of signal transacting is described.
（3）The base station receiver for the TETRA digital cluster systems that prior art is related to only is multiband TETRA set of digits
Group's detection means part, is not involved with the overall plan of multiband TETRA Digital Clustering detection means.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention proposes a kind of multiband TETRA Digital Clustering detection means, its
Multichannel reception is carried out in one frequency range, while above and below carrying out row of channels reception, realize multiple terminals and multiple base stations
Captured while signal, the multiple receiving channel is completely independent, the detection means also supports nonsynchronous multiple signals to connect
Receive, it includes multiband receiver radio frequency front end, Digital IF Processing plate, reference source, secondary power supply, it is characterised in that：
The multiband receiver radio frequency front end has multiple receiving paths, a frequency range is supported per road, so as to realize many
UHF band reception, each frequency range is broadband reception, it is ensured that Digital IF Processing plate can carry out multichannel reception, multifrequency in frequency range
Section receiver radio frequency front end has two sets of paths of up-downgoing independence again, supports up-downgoing to receive simultaneously；
The Digital IF Processing plate receives the signal in a band bandwidth, while carrying out the reception of multifrequency point, is responsible for
The processing of data and the control of complete machine are received, and external interface is provided；
The reference source provides reference clock；
The secondary power supply provides working power for above each several part.
Wherein, the receiver radio frequency front end is adopted by numerical-control attenuator for overall provide inside reception dynamic, receiver
Use multistage numerical-control attenuator.
Wherein, the Digital IF Processing plate includes A/D Acquisition Circuits, phase-locked loop circuit pll clock generation circuit, scene
Programmable gate array FPGA+OMAP processor circuits and power supply,.
Wherein, the on-site programmable gate array FPGA part is used to perform the multiband TETRA Digital Clusterings detection
Whole signal transactings of device, it is received according to band bandwidth, can receive all signals in frequency range, in actual use according to
The multiple frequency ranges of selection are set to be received, the OMAP parts are used to perform the multiband TETRA Digital Clustering detection means
Protocol data analytical capabilities, and realize external interface function.
Wherein, the main work clock of the FPGA portion is provided by the PLL circuit, and before master clock generation, institute
Stating FPGA portion needs to produce clock operation PLL configurators by local crystal oscillator.
The invention also provides a kind of multiband receiver radio frequency front end, including two groups of antenna ports, preselection filter and
Receiving channel, it is characterised in that：
One group of antenna port receives uplink band, and another group of antenna port receives band downlink, and two groups of antenna ports can
Received while realizing up-downgoing；
The preselection filter is one group of wave filter, and correspondence corresponding band is gated according to the working frequency range of selection during work
Wave filter, realizes that the multiband of receiver is received；
The receiving channel is different according to the frequency of reception, and signal reception is carried out using corresponding receiving channel, receives logical
The reception bandwidth in road is bin width, can realize that multichannel is received.
Wherein, the signal exported from the preselection filter inputs the receiving channel.
Wherein, according to the frequency of reception, the receiving channel includes low noise amplifier LNA, frequency mixer, intermediate-frequency filter
And controllable gain amplifier, or including low noise amplifier LNA, frequency range selector, frequency mixer, intermediate-frequency filter and controllable increasing
Beneficial amplifier.
The invention also provides a kind of multiband TETRA numbers using above-mentioned multiband TETRA Digital Clustering detection means
Word cluster detection method, the multiband TETRA Digital Clustering detection means is operated in 350MHz to 800MHz 6 cluster works
Make frequency range, the reference source exports three roadbed clock signals, and two-way is supplied to multiband receiver radio frequency front end, and another road is carried
Supply Digital IF Processing plate.
It comprises the following steps：
The multiband receiver radio frequency front end receives frequency range according to parameter setting selection, will receive during signal downconverts to
Frequency signal output；
The Digital IF Processing plate is sampled to the output signal of receiving front-end, before the multiband receiver radio frequency
End provides intermediate frequency output, and the Digital IF Processing plate is provided with intermediate frequency acquisition channel accordingly；The Digital IF Processing plate exists
Numeric field carries out frequency sweep, down coversion, variable Rate, demodulation, decoding and protocal analysis processing, is externally entered by Ethernet interface and serial ports
Row data exchange, and control the display screen of front panel, keyboard.
Wherein, Instrument working parameter input is carried out by front panel keyboard.
Above-mentioned multiband TETRA Digital Clustering detection means is mainly used in searching for the wireless signal of designated frequency band, and recognizes
Go out the frequency of TETRA Digital Clustering carrier waves（Channel number）, Main control channel and network number；Obtain the uplink and downlink of assigned frequency
TETRA Digital Clustering signals, and on-line analysis is carried out to it；In the acquired TETRA Digital Clustering signalings of automatic parsing
PDU, and information analysis is carried out to it；In the form of MSC figures, the signaling process figure of TETRA digital cluster systems is shown；Preserve
Signaling information acquired in whole, and off-line analysis is carried out to it；The voice messaging acquired in whole is preserved, and it is entered to act
After play back.
The beneficial effect that technical solution of the present invention is brought
（1）The working frequency range of TETRA Digital Clustering detection means is 300MHz~900MHz, if TETRA Digital Clusterings are examined
Surveying device does not use multiband to receive, it is necessary to using the A/D devices of very high sample frequency, and higher to signal processing requirement,
Cost and computation complexity are all very high；
（2）If TETRA Digital Clustering detection means does not use multiband to receive, using broadband reception, it will introduce a lot
Interference signal（Other systems signal in addition to group frequency is collected）, the vulnerability to jamming ability and the linearity of system are proposed more stringent
It is required that；
（3）If TETRA Digital Clustering detection means does not use multiband to receive, using broadband reception, some broadband devices
（Such as radio-frequency filter, VCO）Realize that difficulty is larger.
Brief description of the drawings
Fig. 1 shows that a kind of multi mode multi band RF front-end circuit of prior art constitutes block diagram；
Fig. 2 shows a kind of structured flowchart of base station receiver for TETRA group systems of prior art；
Fig. 3 shows the planning chart of the basic parameters at different levels of receiver shown in Fig. 2；
Fig. 4 shows the multiband TETRA Digital Clustering detection means schematic diagram consistent with the embodiment of the present invention；
Fig. 5 shows the multiband receiver radio frequency front end theory diagram consistent with the embodiment of the present invention；
Fig. 6 shows the basic composition figure of the Digital IF Processing plate consistent with the embodiment of the present invention；
Fig. 7 shows the A/D Acquisition Circuit schematic diagram consistent with the embodiment of the present invention；
Fig. 8 shows the pll clock circuit diagram consistent with the embodiment of the present invention；
Fig. 9 shows the PLL configuration circuit schematic diagram consistent with the embodiment of the present invention；
Figure 10 shows the FPGA clock matches circuit consistent with the embodiment of the present invention；
Figure 11 shows the FPGA+OMAP processor circuit schematic diagram consistent with the embodiment of the present invention；
Specific embodiment
（1）Basic composition and the course of work
Multiband TETRA Digital Clusterings detection means is by multiband receiver radio frequency front end, Digital IF Processing plate, reference
Source, secondary power supply, case front panel and fan composition.Multiband receiver radio frequency front end can be received in any one frequency range simultaneously
Multiple signals, two antenna ports receive uplink band signal and band downlink signal in frequency range respectively.At digital intermediate frequency
Reason plate is responsible for receiving the processing of data and the control of complete machine, and provides external interface.Reference source provides reference clock.Secondary power supply
Working power is provided for modules.The basic composition of multiband TETRA Digital Clustering detection means is as shown in Figure 3.
Multiband TETRA Digital Clusterings detection means can be operated in 6 cluster working frequency range shown in table 1, multiband
Radio-frequency front-end has two antenna ports, is respectively used to receive uplink band signal and band downlink signal.Radio-frequency front-end is according to ginseng
Number sets selection to receive frequency range, will receive signal and downconverts to intermediate-freuqncy signal output.
Digital IF Processing plate is sampled to the output signal of receiving front-end, and it is defeated that multi-frequency band radio-frequency front end provides intermediate frequency
Go out, Digital IF Processing plate is provided with intermediate frequency acquisition channel accordingly.Process plate numeric field carry out frequency sweep, down coversion, variable Rate,
The processing such as demodulation, decoding and protocal analysis.Digital IF Processing plate externally carries out data exchange by Ethernet interface and serial ports, and
Control display screen, keyboard of front panel etc..
Reference source provides reference clock for complete machine.Reference source can use internal crystal oscillator, can also select external reference.Ginseng
The clock source selection for examining source is set by front panel, and acquiescence uses internal crystal oscillator mode.The road reference clock letter of reference source output three
Number, two-way is supplied to multiband receiver radio frequency front end, and another road is supplied to Digital IF Processing plate.
Secondary power supply is converted to the 220V AC powers of outside input the working power of modules needs.Front panel shows
Display screen is used for display data analysis result, Instrument working parameter, the information such as working condition.Instrument can be carried out by front panel keyboard
Device running parameter is inputted, the operation such as reset.
（2）Multiband receiver radio frequency front end
Multiband receiver radio frequency front end is needed to configure the cluster frequency range of its work, and intermediate frequency is output as in a cluster frequency range
Uplink band signal or band downlink signal.Radio-frequency front-end is divided into two parts of preselection filter and receiving channel, multiband
Receiver radio frequency front end theory diagram is as shown in Figure 5.
Preselection filter is one group of wave filter, and one of wave filter is gated according to the working frequency range of selection during work.
Antenna port 1（ANT1）Receive uplink band, antenna port 2（ANT2）Band downlink is received, preselection filter group is according in table 1
Cluster frequency range divide design.Receiving channel according to receives frequency different demarcation.Receiving channel 1 and receiving channel 3 receive frequency
Rate scope 350MHz~470MHz signal, receiving channel 2 and the receives frequency scope 806MHz of receiving channel 4~866MHz letter
Number.The reception bandwidth 10MHz of receiving channel 1 and receiving channel 3.The reception bandwidth 15MHz of receiving channel 2 and receiving channel 4.
Receiver radio frequency front end reduces the noise coefficient of complete machine by the LNA of front end, so as to ensure that receiving sensitivity is excellent
In -115dBm.Receiver front end provides reception dynamic by numerical-control attenuator to be overall, and receiver inside is declined using multistage numerical control
Subtract device, it is ensured that receive the requirement that disclosure satisfy that maximum input signal -20dBm.Numerical-control attenuator, which is suitable for TDMA time-division systems, to be made
With, can be according to the default of time slot progress yield value, raising gain controls regulate the speed.Using high phaselocked loop of mutually making an uproar inside receiver
Circuit, it is ensured that the performance of the anti-monkey chatter of system.
（3）Digital IF Processing plate
1）Operation principle
Digital IF Processing plate is responsible for signal transacting and protocol processing task, supports multidiameter delay to receive, possesses multichannel
Parallel processing capability, is made up of analog portion and numerical portion.Analog portion includes high-speed a/d, and phase-locked loop circuit（PLL）.
Numerical portion uses FPGA+OMAP frameworks.The basic composition of Digital IF Processing plate is as shown in Figure 6.
High-speed a/d is responsible for gathering the analog signal of receiving radio frequency front end output.FPGA is responsible for down coversion, demodulation, channel solution
The digital signal processing tasks such as code, synchronous.OMAP completes protocol stack processing work, and provides and outside serial ports, network interface, USB
Deng interface.PLL produces A/D sampling clocks.As the key control unit of analyzer, Digital IF Processing plate is responsible for before radio frequency
End, front panel, the control of frequency source, are provided by FPGA and OMAP.
High-speed figure collection plate is broadly divided into four partial circuits, be respectively A/D Acquisition Circuits, pll clock generation circuit,
FPGA+OMAP processor circuits and power supply.
2）A/D Acquisition Circuits
The IF output signal of A/D Acquisition Circuit receiving radio frequency front ends, if sampling is carried out to analog if signal.A/D
Acquisition Circuit can carry out wideband sampling to the signal in a frequency band, so can subsequently carry out the processing of many receiving channels.
Because the incoming frequency and sample frequency of A/D Acquisition Circuits are all very high, it is necessary to strictly designed Acquisition Circuit,
To ensure its performance.A/D simulation input and clock input uses difference modes, it is ensured that the stability and vulnerability to jamming of signal.
A/D numeral output also uses the LVDS level of difference, it is ensured that the transmission reliability of high-speed digital signal.A/D Acquisition Circuits are such as
Shown in Fig. 7.
3）Pll clock circuit
Clock circuit is used for the work clock for producing each several part on plate, and the reference clock of clock circuit is an externally input, defeated
Go out multichannel differential clocks, be respectively supplied to high-speed a/d and FPGA.Differential clocks are produced by PLL frequencys multiplication, pll clock circuit design
As shown in Figure 8.PLL configuration is completed by FPGA, and configuration circuit is as shown in Figure 9.PLL is supplied to FPGA differential clocks circuit
As shown in Figure 10.
6）FPGA+OMAP processor circuits
Whole signal processing tasks of tester are completed in a piece of FPGA, and all protocol data analytical capabilities are in OMAP
Realize.OMAP as tester primary processor, also to realize external interface and front panel show, the function such as keyboard.FPGA+
The design of OMAP processor circuits is as shown in figure 11.
1. FPGA peripheral circuit is designed
The major function completed in FPGA has：
The Digital Down Convert of multipath reception signal and down-sampling；
Synchronous search；
Carrier synchronization and bit synchronization；
Demodulation and channel decoding；
The configuration of radio-frequency front-end；
With OMAP data communication.
According to FPGA function, its periphery circuit design includes work clock circuit and reset circuit.
FPGA main work clock is provided by PLL circuit.Because PLL circuit needs FPGA to configure, before master clock generation,
FPGA needs to produce clock operation PLL configurators by local crystal oscillator.After after master clock normally input, FPGA enters normal work
Make state.
FPGA has two kinds of reset modes, and external key resets and OMAP resets.OMAP resets to be realized by a GPIO.
FPGA reset signal is low effectively.
2. OMAP periphery circuit designs
OMAP peripheral circuit includes bus circuit, reset circuit, interface circuit and power supply.
OMAP is divided to for two sets of buses of SDRC and GPMC.SDRC buses are served only for accessing outside DDR memory devices, GPMC buses
For accessing external memory storage, such as NAND, FLASH, FPGA is as an External memory equipment, and the GPMC for hanging over OMAP is total
On line.
NAND and FPGA are directly in OMAP GPMC buses.Network card equipment, two are also hung with GPMC buses
Person's connection has to pass through level conversion.Data wire in bus is transmitted in both directions, must control level translator by read-write
Input and output direction, the output for controlling level translator by chip selection signal CS is enabled.NAND occupies the CS0 spaces of GPMC buses,
Network interface card occupies the CS6 spaces of GPMC buses, and FPGA occupies the CS5 spaces of GPMC buses.Bus circuit annexation such as Figure 11 institutes
Show.
OMAP reset circuits support electrification reset and button to reset, and electrification reset is by power management chip control, and it is upper
It is always that OMAP provides reset signal in electric process, is discharged after the completion of upper electricity.Button resets what is provided with power management chip
Reset signal be line and relation.Reset signal is connected on LCD, FPGA and network interface card simultaneously.Reset circuit is as shown in figure 11.
OAMP provides external interface, internal interface and local interface, and interface circuit is as shown in figure 11.
External interface circuit is as follows：
Communication serial port：Using OMAP UART0 serial ports, provided by RS232 interface chips；
Monitor serial ports：Using OMAP UART3 serial ports, provided by RS232 interface chips；
Ethernet interface：Using network card chip, hang on GPMC bus spaces CS6.
Internal interface circuit includes：
USB OTG interfaces：Using OMAP HSUSB0, by the usb circuit of power management chip, there is provided USB
OTG interfaces；
LCD interfaces：OMAP provides DSS interface signals, i.e. 8bits rgb interface signal, can be joined directly together with LCD；
Keyboard interface：Front panel is 4 × 5 keyboards, and OMAP is connect by reading the corresponding registers in power management chip
Receive push button signalling.OMAP is communicated by I2C interfaces with power management chip internal register.
Local interface circuit includes：
JTAG；
BOOT signals：Different BOOT signals configurations, determines OMAP boot sequence, and circuit selection is first opened from NAND
It is dynamic.
3. FPGA and OMAP interface circuit
OMAP is the primary processor of tester, and FPGA is controlled by OMAP as from processor, and the GPMC for being connected to OMAP is total
On line.FPGA and OMAP reading and writing data uses single-cycle read and write pattern, and the piece that FPGA is in OMAP selects 5 spaces, that is, used
NCS5 chooses.The data bits of FPGA and OMAP buses is 16bits, and address is 10bits.
FPGA and OMAP interface signal is in addition to bus signals, also FPGA to OMAP interrupt signal, and OMAP is extremely
GPIO between FPGA reset signal and FPGA reloading signal, and OMAP and FPGA.7）Power supply
Analog power and digital power on Digital IF Processing plate is independent of one another, respectively by outside input.
Analog circuit on plate is powered using external analog power supply, and each several part demand is produced using linear stabilized power supply chip
Different magnitudes of voltage power supply.Linear stabilized power supply chip can provide low noise power supply, it is ensured that the performance of analog circuit.
Digital circuit on plate is powered using digital power, and the difference electricity of each several part demand is produced using switching power source chip
The power supply of pressure value.Switching power source chip can provide the power damage during higher power supply conversion efficiency, reduction Power convert
Consumption.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
In the case of departing from the principle and objective of the present invention a variety of change, modification, replacement and modification can be carried out to these embodiments, this
The scope of invention is limited by claim and its equivalent.
Claims (7)
1. a kind of multiband TETRA Digital Clustering detection means, it carries out multichannel reception in a frequency range, while entering
The reception of row of channels above and below row, is captured while realizing multiple terminals and multiple base station signals, and the multiple receiving channel is complete
Independent, the detection means also supports nonsynchronous multiple signals to receive, and it is included in multiband receiver radio frequency front end, numeral
Frequency process plate, reference source, secondary power supply, it is characterised in that：
The multiband receiver radio frequency front end has multiple receiving paths, a frequency range is supported per road, so as to realize multiband
Receive, each frequency range is broadband reception, it is ensured that Digital IF Processing plate can carry out multichannel reception in frequency range, and multiband connects
Receipts machine radio-frequency front-end has two sets of paths of up-downgoing independence again, supports up-downgoing to receive simultaneously；
The Digital IF Processing plate receives the signal in a band bandwidth, while carrying out the reception of multifrequency point, is responsible for reception
The processing of data and the control of complete machine, and external interface is provided；
The reference source provides reference clock；
The secondary power supply provides working power for above each several part.
2. multiband TETRA Digital Clustering detection means as claimed in claim 1, wherein the receiver radio frequency front end relies on number
Control attenuator is provided inside reception dynamic, receiver using multistage numerical-control attenuator to be overall.
3. multiband TETRA Digital Clustering detection means as claimed in claim 1, wherein the Digital IF Processing plate includes A/
D Acquisition Circuits, phase-locked loop circuit pll clock generation circuit, on-site programmable gate array FPGA+OMAP processor circuits and electricity
Source.
4. multiband TETRA Digital Clustering detection means as claimed in claim 3, wherein the on-site programmable gate array FPGA
Part is used for the whole signal transactings for performing the multiband TETRA Digital Clustering detection means, and it is received according to band bandwidth,
All signals in frequency range can be received, select multiple frequency ranges to be received according to setting in actual use, the OMAP parts
For performing the protocol data analytical capabilities of the multiband TETRA Digital Clustering detection means, and realize external interface work(
Energy.
5. multiband TETRA Digital Clustering detection means as claimed in claim 3, wherein the main work clock of the FPGA portion
There is provided by the PLL circuit, and before master clock generation, the FPGA portion needs to produce clock operation by local crystal oscillator
PLL configurators.
6. a kind of multiband of multiband TETRA Digital Clustering detection means using as described in claim 1-5 any one
TETRA Digital Clustering detection methods, the multiband TETRA Digital Clustering detection means is operated in the 6 of 350MHz to 800MHz
Individual cluster working frequency range, the reference source exports three roadbed clock signals, and two-way is supplied to multiband receiver radio frequency front end,
Another road is supplied to Digital IF Processing plate；
It comprises the following steps：
The multiband receiver radio frequency front end receives frequency range according to parameter setting selection, will receive signal and downconverts to intermediate frequency letter
Number output；
The Digital IF Processing plate is sampled to the output signal of receiving front-end, and the multiband receiver radio frequency front end is carried
For intermediate frequency output, the Digital IF Processing plate is provided with intermediate frequency acquisition channel accordingly；The Digital IF Processing plate is in numeral
Domain carries out frequency sweep, down coversion, variable Rate, demodulation, decoding and protocal analysis processing, and line number is externally entered by Ethernet interface and serial ports
According to exchange, and control the display screen of front panel, keyboard.
7. multiband TETRA Digital Clustering detection methods as claimed in claim 6, wherein carrying out instrument work by front panel keyboard
Make parameter input.
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| CN109995387B (en) * | 2019-03-01 | 2021-03-30 | 电子科技大学 | Method for inhibiting image interference of broadband receiver |
| CN109714066B (en) * | 2019-03-05 | 2020-10-16 | 成都中亚通茂科技股份有限公司 | Full-band radio frequency direct-acquisition receiving and processing equipment |
| CN110221650B (en) * | 2019-06-18 | 2021-04-09 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
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