CN103781085A - Multi-frequency range TETRA digital cluster detection method and apparatus - Google Patents
Multi-frequency range TETRA digital cluster detection method and apparatus Download PDFInfo
- Publication number
- CN103781085A CN103781085A CN201310676115.8A CN201310676115A CN103781085A CN 103781085 A CN103781085 A CN 103781085A CN 201310676115 A CN201310676115 A CN 201310676115A CN 103781085 A CN103781085 A CN 103781085A
- Authority
- CN
- China
- Prior art keywords
- multiband
- frequency
- digital
- tetra
- frequency range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Circuits Of Receivers In General (AREA)
Abstract
The invention discloses a multi-frequency range TETRA digital cluster detection apparatus and a detection method applying the apparatus. The apparatus comprises a multi-frequency range receiver radio frequency front end, a digital intermediate frequency processing plate, a reference source and a secondary power supply, and is characterized in that the multi-frequency range receiver radio frequency front end simultaneously receiving a multipath signal within any one frequency range; the digital intermediate frequency processing plate is in charge of processing of receiving data and control of a whole machine, and provides an external interface; the reference source provides a reference clock; and the secondary power supply supplies working power to the other aforementioned parts. By using the method and apparatus provided by the invention, the realization complexity and production cost of a TETRA digital cluster detection apparatus can be reduced, and the interference resistance is improved.
Description
Technical field
The present invention relates to TETRA(terrestrial trunked radio) digital cluster communication, relate in particular to a kind of multiband TETRA Digital Clustering detection method and device.
Background technology
TETRA digital clustering communication system is a kind of wireless clustering mobile communication system based on digital tdma (TDMA) technology.This system is ETSI(ETS association) combine use department, manufacturer, detection department and even government department, in order to meet the open system of the specialized department of European Countries to the needs design of mobile communication, formulation unified standard.TETRA digital clustering communication system can provide command scheduling, transfer of data and telephone service on same technology platform, it not only provides the scheduling feature of multigroup group, but also short data information service, packet data service and the service of digitized full duplex mobile phone can be provided.
Prime information Estate Division has been issued (SJ/T11228-2000) standard of China's " Digital Clustering mobile communication system system " on December 28th, 2000, this is a ministry standard that electron trade is recommendatory, has determined two kinds of systems of TETRA system and iDEN system in this standard.Within 2003, the Ministry of Public Security has formulated 350MHz TETRA industry standard, and in succession in Guangzhou, Shenzhen and Zhuhai set up try net.
TERTA digital cluster system is the application of the specialized department such as railway, subway, light rail, airport, harbour water conservancy, public security, safety, army at home and abroad.At present, urban track traffic (for example: subway, light rail and suburban railway) is the professional TETRA digital trunk network of China's maximum.Up to now, China's track traffic urban track traffic is used more than 1400 base station and more than 150 switch, has more than 31000 user terminal.
For meeting the World College Students Games in 2011, built the 350MHz TETRA Digital Clustering private network of 69 base stations and 2 switches by Shenzhen Municipal Public Security Bureau, this network can hold 25000 users.At present, Qingdao public security bureau is building the 350MHz TETRA Digital Clustering private network of more than 40 base station and 2 switches, and this network can hold 3 general-purpose families.
For meeting the 2008 Beijing Olympic Games, built the fairly large 800MHz TETRA Digital Clustering common network of more than 300 base station and 6 switches by Zheng Tong company, this network can hold 9 general-purpose families, and network has more than 70,000 user at present.For meeting the Guangzhou Asian Games in 2010, built the 800MHz TETRA Digital Clustering common network of 179 base stations and 2 switches by Guangdong Telecom, this network can hold 5 general-purpose families.
The mission-critical scheduling feature of TETRA Digital Clustering and reliably networking capability provide thousands of phone groups for the Olympic Games, World Expo, the Asian Games, Games for university students etc., flexibly across organizing horizontal coordination communication, can realize vehicle location, individual location, and short message and packet data application.The impact of the Bulk Call producing for Opening and closing ceremonies and the accident of occasion to network, TETRA can provide optimum solution and counter-measure.
Because TETRA is the international standard of an opening, attract numerous enterprises and institute to participate in research and the production of TETRA product directly.System and terminal that domestic unit has the priorities such as 7 of Harbin Institute of Technology, Beijing Jiaotong University, Beijing Institute of Technology, Qingdao Hisense Group, Tianjin Communications broadcast group, Central Plains, Wuhan communication group, company of EastCom, group companies of ZhongDian Science & Technology and 54, Shanghai San Ji company, wide 1 Haige Co.s, Shenzhen Hai Nengda company, Shenzhen Kirisun company, Beijing Shou Ke software company and Hangzhou You Neng company to drop into strength to research and develop and produce TETRA.And TETRA system and the terminal of overseas enterprise, such as French CASsIDIAN (NOKIA, EADS) the TETRA system of company, TETRA-FLEX system of DAMM company of Denmark, the DIMETRA system of MOTOROLA company of the U.S., TETRA-NODE system of ROHILL company of Holland, the ACCESSNET system of ROHDESCHWARZ company of Germany, the ACCESSNET system of SIEMENS company of Germany, the TETRA system of THALEs company of France, Italy SELEX (OTE, MARCONI) the ELETTRA system of company, the TETRA/G system of TEAM SIMOCO company of Britain, the TETRA equipment major part of the manufactures such as the TETRA terminal of the NEBULA system of TELTRONIC company of Spain and SEPURA company of Britain has all been passed through the detection at the Ministry of Industry and Information Technology of China radio monitoring center, and the model that has obtained radio administration is checked and approved.
Due to TETRA digital colony network various countries all over the world, each country, according to the actual conditions of own national radio control, has distributed different TETRA Digital Clustering frequencies, and table 1 has provided the distribution of domestic and international TETRA Digital Clustering frequency.
Table 1 is the distribution of TETRA Digital Clustering frequency both at home and abroad
The no matter operation of TETRA digital colony network, or the exploitation of TETRA digital packet terminal and system (base station and switch), all need a kind of multiband TETRA Digital Clustering checkout gear, TETRA digital colony network to operation and the base station of developing and terminal detect, guarantee to have runed TETRA digital colony network safety and available, support the protocal analysis of TETRA digital cluster system and terminal development, show the Complicated Flow details of signaling protocol in TETRA digital packet terminal and intersystem communications process.
Prior art one related to the present invention
The technical scheme of prior art one
Prior art source: patent application, application number 200910258707.1.Publication number: CN102096079A.
This patent belongs to radio frequency communication technical field, relates to satellite navigation receiver radio-frequency (RF) front-end circuit, particularly recognizes method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and module thereof.
This patent discloses a kind of configurable multimode multi-frequency section satellite navigation receiver method and RF front-end module thereof, RF front-end module can receive the satellite navigation and location system signal of GPS, the Big Dipper, Galileo and GLONASS, this module comprises the configurable LNA with Buffer and active Balun, be with configurable multi-mode filter, the bigoted circuit of automatic gain control amplifier AGC and direct current, also comprises the switch control word from the program control coding of multi mode multi band of receiving system.The control word of programming by receiving system, front-end module can meet multiband and multi-mode working, input with one-channel signal, two paths of differential signals output, radio-frequency (RF) front-end circuit forms simple and reliable, does not need the outer module of complicated time division multiplexing control system and sheet, and cost is low, flexibility is good, improves noiseproof feature and the multi mode multi band signal handling capacity of whole receiver radio frequency front end.
Fig. 1 shows a kind of multi mode multi band radio-frequency (RF) front-end circuit and forms block diagram, mainly by configurable low-noise preamplifier LNA11, buffer Buffer12, actively singly turn two end-apparatus Balun13, two frequency mixers 14 and 16, configurable frequency synthesizer 15, configurable multimode filter 17 and broadband automatic gain control amplifier AGC18 of changing and form.
Received RF signal RFIN accesses the input of configurable low-noise preamplifier LNA11, low-noise preamplifier LNA11, buffer Buffer12, actively singly turn two end-apparatus Balun13 single-ended connections successively of changing, active two difference output ends that change end-apparatus Balun13 connect respectively the input of frequency mixer 14 and 16, the difference local oscillation signal " I " that configurable frequency synthesizer 15 is exported is connected the local oscillation signal input of respective mixers 14 and 16 with " Q ", the difference radio-frequency signal " Q " that the difference local oscillation signal " I " that frequency mixer 14 is exported is exported with frequency mixer 16 is connected respectively the input of corresponding configurable filter 17, the difference radio-frequency signal " I " of configurable filter 17 and " Q " output are connected respectively the differential input end of automatic gain control amplifier AGC18, difference output " I " and " Q " end of automatic gain control amplifier AGC18, the front radio-frequency output signal REOUT of multi mode multi band RF front-end module output is delivered to follow-up circuit module.
The shortcoming of prior art one
(1) more than prior art relates to the operating frequency 1GHz of satellite navigation receiver radiofrequency signal, and TETRA Digital Clustering checkout gear operating frequency is at 300MHz～900MHz, so the method for prior art is not suitable for TETRA Digital Clustering checkout gear.
(2) prior art relates to satellite navigation receiver radiofrequency signal modulation system and radio frequency reception index all can not meet the requirement of TETRA Digital Clustering checkout gear.
(3) prior art does not relate to whole receiver apparatus, only relates to satellite navigation receiver radio-frequency (RF) front-end circuit.
Prior art two related to the present invention
The technical scheme of prior art two
Prior art source: electronic device (Chinese Jourml of Electron Device) periodical, the 29th volume in 2006, the 3rd phase.
A kind of design of the base station receiver for TETRA digital cluster system, Wang Jingning, Tan Xuezhi (Research on Communication Technology institute of Harbin Institute of Technology, Harbin 150001)
Paper is the requirement to receiver for special mobile mobile communication, has analyzed base station receiver technical indicator and selection dual IF superheterodyne receiver scheme in TETRA agreement.Each several part is carried out to noise factor and gain distribution, and select the middle and small scale integrated device meeting the demands, carry out circuit design and the realization of receiver.
The receiver that adopts superhet dual IF structure, the first intermediate frequency selects 70MHz, and the second intermediate frequency selects l0.7MHz.Its selectivity is good, and dynamic range is large, and noise factor is low, and mirror image suppresses, and Fig. 2 shows the structured flowchart of receiver.
Receiver is divided into four parts from function: radio-frequency front-end, intermediate frequency amplifies, demodulation, automatic power gain control.Noise factor at different levels and gain are as shown in Figure 2.
(1) first vibration frequency is 876～891MHz, on 810+2*70=950MHz, there will be mirror image to disturb, in order to address this problem, just need to before low noise amplifier, add filter BPF1, here the function of BPF1 is just served as by duplexer, loss is little, little on the impact of global noise coefficient.
(2) selection of noise factor
[NF]＝[NF]
1+([NF]
2-1)/G
1+([NF]
3-1)/G
1G
2+......
Above formula is the computing formula of total noise factor of receiver.From formula, global noise coefficient depends primarily on first order amplifying circuit LNA, requires its noise factor low.General way is: [NF]
2about 2dB, simultaneously G
1at least want [NF]
2than large 3dB.
(3) side channel suppresses
On 800MHz radio frequency, accomplish the bandwidth of 25kHz, the Q value of filter is impossible accomplish, can only on intermediate frequency and low frequency, realize the filtering of the bandwidth of 25kHz.The general side channel that can only accomplish 30dB on the intermediate frequency of 10.7MHz suppresses.The processing of base band is used CMX980A, and it can make the attenuation outside a channel of 25kHz fall 60dB, and neighboring trace inhibition can exceed the 45dB of requirement like this.But such problem be the power detection of carrying out on intermediate frequency to be not the actual power on receive channel, need to connect again a filter at power detection branch road, obtain the inhibition of 60dB.
Low noise amplifier is selected AGB330.Radio-frequency (RF) mixer is selected AD8344, the AD8344 of Analog Device company is a kind of high performance frequency mixer, it mainly designs for radio infrastructure, adopts gilbert's structure, and radio frequency band is wide, noise is low, the linearity is high, and Intermodulation Interference is little, low in energy consumption, Signal segregation degree is high, can outsidely turn-off.
Intermediate frequency is put amplifier and is selected MC1496, the product of Zhe Shi motorola inc, and the gain that it at 60MHz is is 35dB, and noise factor 6dBmAGC scope reaches 60dB, and when l2V power supply, only 204mw of power consumption, also can be used as frequency mixer.In adopting two, put MC1496, the AGC that can arrive 120dB controls.
Synthetic ADF4360-7 of selecting of first vibration frequency, frequency range is 350～1800MHz.Its advantage is to collect VCO and PLL in a chip, and peripheral cell is few, and oscillation center frequency is determined by inner variable capacitance diode and two peripheral inductance.Supply voltage is 3.0～3.6V, and output level is able to programme, 3-line serial interface.The synthetic ADF4001 that selects of the second local frequency is PLL, with ADS344 upper with oscillator be VCO, the bandwidth with 200MHz of ADF4001, supply voltage is 2.7～5.5V, current programmable control, 3-line serial interface, power can software or hardware controls, extremely low noise.
Quadrature demodulator is selected the RF2721 of Marconi company, and it is widely used in VHF receiver, and bandwidth is 100kHz～500MHz, its supply voltage is 5V, on chip, with the active part of oscillator, exports and digital to analog converter compatibility, extremely low local oscillation power requirement, power can be digital control.
The shortcoming of prior art two
(1) to relate to the operating frequency of the base station receiver of TETRA digital cluster system be 800MHz to prior art, and TETRA Digital Clustering checkout gear operating frequency is 300MHz～900MHz, so the method for prior art is not suitable for multiband TETRA Digital Clustering checkout gear.
(2) prior art only relates to the radio frequency operation principle of the base station receiver of TETRA digital cluster system, the scheme of base band signal process is not described.
(3) base station receiver of the TETRA digital cluster system that prior art relates to is only a multiband TETRA Digital Clustering checkout gear part, does not relate to the overall plan of multiband TETRA Digital Clustering checkout gear.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of multiband TETRA Digital Clustering checkout gear, it carries out multichannel reception in a frequency range, and carry out the reception of up-downgoing passage simultaneously, when realizing multiple terminals and multiple base station signal, capture, described multiple receive paths are completely independent, and described checkout gear also supports nonsynchronous multiple signals to receive, it comprises multiband receiver radio frequency front end, Digital IF Processing plate, reference source, secondary power supply, it is characterized in that:
Described multiband receiver radio frequency front end has multiple receiving paths, a frequency range is supported on every road, thereby realizing multiband receives, each frequency range is broadband reception, guarantee that Digital IF Processing plate can carry out multichannel reception in frequency range, multiband receiver radio frequency front end has again independently two cover paths of up-downgoing, supports that up-downgoing receives simultaneously;
Described Digital IF Processing plate receives the signal in a band bandwidth, carries out the reception of multifrequency point simultaneously, is responsible for receiving the processing of data and the control of complete machine, and external interface is provided;
Described reference source provides reference clock;
Described secondary power supply provides working power for above each several part.
Wherein, described receiver radio frequency front end relies on numerical-control attenuator to receive dynamically for entirety provides, the multistage numerical-control attenuator of the inner employing of receiver.
Wherein, described Digital IF Processing plate comprises that A/D Acquisition Circuit, phase-locked loop circuit pll clock produce circuit, on-site programmable gate array FPGA+OMAP processor circuit and power supply.
Wherein, described on-site programmable gate array FPGA part is for carrying out whole signal processing of described multiband TETRA Digital Clustering checkout gear, it receives according to band bandwidth, can receive all signals in frequency range, in actual use, select multiple frequency ranges to receive according to arranging, described OMAP part is used for carrying out the protocol data analytical capabilities of described multiband TETRA Digital Clustering checkout gear, and realizes external interface function.
Wherein, the main work clock of described FPGA part is provided by described PLL circuit, and before master clock produces, described FPGA part need to rely on local crystal oscillator to produce clock operation PLL configurator.
The invention allows for a kind of multiband receiver radio frequency front end, comprise two groups of antenna ports, preselection filter and receive paths, it is characterized in that:
One group of antenna port receives uplink band, and another group antenna port receives band downlink, when two groups of antenna ports can be realized up-downgoing, receives;
Described preselection filter is one group of filter, and when work, according to the filter of the corresponding corresponding band of the working frequency range gating of selecting, the multiband of realizing receiver receives;
Described receive path, according to the frequency difference receiving, adopts corresponding receive path to carry out signal reception, and the reception bandwidth of receive path is bin width, can realize multichannel and receive.
Wherein, input described receive path from the signal of described preselection filter output.
Wherein, according to the frequency receiving, described receive path comprises low noise amplifier LNA, frequency mixer, intermediate-frequency filter and controllable gain amplifier, or comprises low noise amplifier LNA, frequency range selector, frequency mixer, intermediate-frequency filter and controllable gain amplifier.
The invention allows for a kind of multiband TETRA Digital Clustering detection method that uses above-mentioned multiband TETRA Digital Clustering checkout gear, described multiband TETRA Digital Clustering checkout gear is operated in 6 cluster working frequency range of 350MHz to 800MHz, described reference source is exported three road reference clock signals, two-way offers multiband receiver radio frequency front end, and another road offers Digital IF Processing plate.
It comprises the following steps:
Described multiband receiver radio frequency front end arranges selective reception frequency range according to parameter, and reception signal is downconverted to intermediate-freuqncy signal output;
Described Digital IF Processing plate is sampled to the output signal of receiving front-end, and described multiband receiver radio frequency front end provides intermediate frequency output, and described Digital IF Processing plate is provided with intermediate frequency acquisition channel accordingly; Described Digital IF Processing plate carries out frequency sweep, down-conversion, variable Rate, demodulation, decoding and protocal analysis processing at numeric field, externally carries out exchanges data by Ethernet interface and serial ports, and controls display screen, the keyboard of front panel.
Wherein, carry out Instrument working parameter input by front panel keyboard.
Above-mentioned multiband TETRA Digital Clustering checkout gear is mainly used in searching for the wireless signal of designated frequency band, and identifies TETRA Digital Clustering and carry wave frequency (channel number), Main control channel and network number; Obtain the uplink and downlink TETRA Digital Clustering signal of assigned frequency, and it is carried out to on-line analysis; Automatically resolve the PDU in the TETRA Digital Clustering signaling of obtaining, and it is carried out to information analysis; With the form of MSC figure, show the signaling process figure of TETRA digital cluster system; Preserve whole obtained signaling informations, and it is carried out to off-line analysis; Preserve whole obtained voice messagings, and it is carried out to playback afterwards.
The beneficial effect that technical solution of the present invention is brought
(1) working frequency range of TETRA Digital Clustering checkout gear is 300MHz～900MHz, if TETRA Digital Clustering checkout gear does not adopt multiband to receive, need to adopt the A/D device of very high sample frequency, and higher to signal processing requirement, and cost and computation complexity are all very high;
(2) if TETRA Digital Clustering checkout gear does not adopt multiband to receive, adopt broadband reception, will introduce a lot of interference signals (the other system signal except cluster frequency), the vulnerability to jamming ability to system and the linearity propose more harsh requirement;
(3) if TETRA Digital Clustering checkout gear does not adopt multiband to receive, adopt broadband reception, some broadband devices (such as radio-frequency filter, VCO etc.) to realize difficulty larger.
Accompanying drawing explanation
Fig. 1 has shown that a kind of multi mode multi band radio-frequency (RF) front-end circuit of prior art forms block diagram;
Fig. 2 has shown the structured flowchart of a kind of base station receiver for TETRA group system of prior art;
Fig. 3 has shown the planning chart of the basic parameters at different levels of receiver shown in Fig. 2;
Fig. 4 has shown the multiband TETRA Digital Clustering checkout gear schematic diagram consistent with the embodiment of the present invention;
Fig. 5 has shown the multiband receiver radio frequency front end theory diagram consistent with the embodiment of the present invention;
Fig. 6 has shown the basic composition figure of the Digital IF Processing plate consistent with the embodiment of the present invention;
Fig. 7 has shown the A/D Acquisition Circuit schematic diagram consistent with the embodiment of the present invention;
Fig. 8 has shown the pll clock circuit diagram consistent with the embodiment of the present invention;
Fig. 9 has shown the PLL configuration circuit schematic diagram consistent with the embodiment of the present invention;
Figure 10 has shown the FPGA clock match circuit consistent with the embodiment of the present invention;
Figure 11 has shown the FPGA+OMAP processor circuit schematic diagram consistent with the embodiment of the present invention;
Specific embodiment
(1) basic composition and the course of work
Multiband TETRA Digital Clustering checkout gear is made up of multiband receiver radio frequency front end, Digital IF Processing plate, reference source, secondary power supply, case front panel and fan.Multiband receiver radio frequency front end can receive the multiple signals in any one frequency range simultaneously, and two antenna ports receive respectively uplink band signal and the band downlink signal in frequency range.Digital IF Processing plate is responsible for receiving the processing of data and the control of complete machine, and external interface is provided.Reference source provides reference clock.Secondary power supply provides working power for modules.The basic composition of multiband TETRA Digital Clustering checkout gear as shown in Figure 3.
Multiband TETRA Digital Clustering checkout gear can be operated in 6 cluster working frequency range shown in table 1, and multi-frequency band radio-frequency front end has two antenna ports, is respectively used to receive uplink band signal and band downlink signal.Radio-frequency front-end arranges selective reception frequency range according to parameter, and reception signal is downconverted to intermediate-freuqncy signal output.
Digital IF Processing plate is sampled to the output signal of receiving front-end, and multi-frequency band radio-frequency front end provides intermediate frequency output, and Digital IF Processing plate is provided with intermediate frequency acquisition channel accordingly.Disposable plates is carried out the processing such as frequency sweep, down-conversion, variable Rate, demodulation, decoding and protocal analysis at numeric field.Digital IF Processing plate externally carries out exchanges data by Ethernet interface and serial ports, and controls display screen, the keyboard etc. of front panel.
Reference source provides reference clock for complete machine.Reference source can use inner crystal oscillator, also can select external reference.The clock source selection of reference source arranges by front panel, and acquiescence is used inner crystal oscillator mode.Reference source is exported three road reference clock signals, and two-way offers multiband receiver radio frequency front end, and another road offers Digital IF Processing plate.
The 220V AC power of outside input is converted to the working power that modules needs by secondary power supply.Front panel display screen is for display data analysis result, Instrument working parameter, the information such as operating state.Can carry out the operations such as Instrument working parameter input, reset by front panel keyboard.
(2) multiband receiver radio frequency front end
Multiband receiver radio frequency front end need to configure the cluster frequency range of its work, and intermediate frequency is output as uplink band signal or a band downlink signal in cluster frequency range.Radio-frequency front-end is divided into preselection filter and two parts of receive path, and multiband receiver radio frequency front end theory diagram as shown in Figure 5.
Preselection filter is one group of filter, when work according to select one of them filter of working frequency range gating.Antenna port 1(ANT1) reception uplink band, antenna port 2(ANT2) receive band downlink, preselection filter group is divided design according to the cluster frequency range in table 1.Receive path is according to the different demarcation of receive frequency.The signal of receive path 1 and receive path 3 receive frequency range 350MHz～470MHz, the signal of receive path 2 and receive path 4 receive frequency range 806MHz～866MHz.The reception bandwidth 10MHz of receive path 1 and receive path 3.The reception bandwidth 15MHz of receive path 2 and receive path 4.
Receiver radio frequency front end relies on the LNA of front end to reduce the noise factor of complete machine, thereby guarantees be better than-115dBm of receiving sensitivity.Receiver front end relies on numerical-control attenuator to receive dynamically for entirety provides, and the multistage numerical-control attenuator of the inner employing of receiver, guarantees to receive the requirement that can meet maximum input signal-20dBm.Numerical-control attenuator is suitable for TDMA time-division system and uses, and can carry out the default of yield value according to time slot, improves gain control and regulates the speed.Receiver is inner adopts the height phase-locked loop circuit of making an uproar mutually, guarantees the performance of the anti-monkey chatter of system.
(3) Digital IF Processing plate
1) operation principle
Digital IF Processing plate is responsible for signal and is processed and protocol processes task, supports multidiameter delay to receive, and possesses multi-channel parallel disposal ability, is made up of simulation part and numerical portion.Simulation part divides and comprises high-speed a/d, and phase-locked loop circuit (PLL).Numerical portion adopts FPGA+OMAP framework.The basic composition of Digital IF Processing plate as shown in Figure 6.
High-speed a/d is responsible for gathering the analog signal of receiving radio frequency front end output.FPGA is responsible for down-conversion, demodulation, channel-decoding, the Digital Signal Processing task such as synchronous.OMAP completes protocol stack work for the treatment of, and the interface with outside serial ports, network interface, USB etc. is provided.PLL produces A/D sampling clock.As the key control unit of analyzer, Digital IF Processing plate is responsible for the control of radio-frequency front-end, front panel, frequency source, is provided by FPGA and OMAP.
High-speed figure collection plate is mainly divided into four partial circuits, is respectively that A/D Acquisition Circuit, pll clock produce circuit, FPGA+OMAP processor circuit and power supply.
2) A/D Acquisition Circuit
The intermediate frequency output signal of A/D Acquisition Circuit receiving radio frequency front end, carries out if sampling to analog if signal.A/D Acquisition Circuit can be carried out wideband sampling to the signal in a frequency band, follow-uply like this can carry out the processing of many receive paths.
Because incoming frequency and the sample frequency of A/D Acquisition Circuit are all very high, need to strictly design Acquisition Circuit, to guarantee its performance.The analog input of A/D and clock input all adopt difference modes, guarantee stability and the vulnerability to jamming of signal.The numeral output of A/D also adopts the LVDS level of difference, guarantees the transmission reliability of high-speed digital signal.A/D Acquisition Circuit as shown in Figure 7.
3) pll clock circuit
Clock circuit is for generation of the work clock of each several part on plate, and the reference clock of clock circuit is outside input, and output multi-channel differential clocks, offers respectively high-speed a/d and FPGA.Differential clocks is produced by PLL frequency multiplication, and pll clock circuit design as shown in Figure 8.The configuration of PLL is completed by FPGA, and configuration circuit as shown in Figure 9.The differential clocks circuit that PLL offers FPGA as shown in figure 10.
6) FPGA+OMAP processor circuit
Whole signal processing tasks of tester complete in a slice FPGA, and all protocol data analytical capabilities are realized in OMAP.OMAP, as the primary processor of tester, also will realize the function such as external interface and front panel demonstration, keyboard.FPGA+OMAP processor circuit designs as shown in figure 11.
1. FPGA periphery circuit design
The major function completing in FPGA has:
According to the function of FPGA, its periphery circuit design comprises work clock circuit and reset circuit.
The main work clock of FPGA is provided by PLL circuit.Because PLL circuit needs FPGA configuration, before master clock produces, FPGA need to rely on local crystal oscillator to produce clock operation PLL configurator.After the normal input of master clock, FPGA enters normal operating conditions.
FPGA has two kinds of reset modes, and external key resets and OMAP resets.OMAP resets and relies on a GPIO to realize.The reset signal of FPGA is low effectively.
2. OMAP periphery circuit design
The peripheral circuit of OMAP comprises bus circuit, reset circuit, interface circuit and power supply.
OMAP is divided into SDRC and GPMC two overlaps bus.SDRC bus is only for accessing outside DDR memory device, and GPMC bus is used for access external memory, such as NAND, FLASH etc., and FPGA, as an External memory equipment, hangs in the GPMC bus of OMAP.
NAND and FPGA are directly connected in the GPMC bus of OMAP.In GPMC bus, also hang with network card equipment, both connect must be through level conversion.Data wire in bus is transmitted in both directions, must be by the input and output direction of read-write control level transducer, by the output enable of chip selection signal CS control level transducer.NAND occupies the CS0 space of GPMC bus, and network interface card occupies the CS6 space of GPMC bus, and FPGA occupies the CS5 space of GPMC bus.Bus circuit annexation as shown in figure 11.
OMAP reset circuit supports electrification reset and button to reset, and electrification reset is by power management chip control, and it is always OMAP reset signal is provided in power up, after having powered on, discharges.Button reset and the reset signal that provides of power management chip be line and relation.Reset signal is connected on LCD, FPGA and network interface card simultaneously.Reset circuit as shown in figure 11.
OAMP provides external interface, internal interface and local interface, and interface circuit as shown in figure 11.
External interface circuit is as follows:
Internal interface circuit comprises:
uSB OTG interface: use the HSUSB0 of OMAP, by the usb circuit of power management chip, provide USB OTG interface;
Local interface circuit comprises:
3. the interface circuit of FPGA and OMAP
OMAP is the primary processor of tester, and FPGA, as being controlled by OMAP from processor, is connected in the GPMC bus of OMAP.The reading and writing data of FPGA and OMAP adopts single-cycle read and write pattern, and FPGA selects 5 spaces in the sheet of OMAP, uses NCS5 to choose.The data bits of FPGA and OMAP bus is 16bits, and address is 10bits.
The interface signal of FPGA and OMAP, except bus signals, also has the interrupt signal of FPGA to OMAP, the reset signal of OMAP to FPGA and FPGA reloading signal, and GPIO between OMAP and FPGA.7) power supply
Analog power and digital power on Digital IF Processing plate are independent of one another, are inputted respectively by outside.
Analog circuit on plate uses external analog Power supply, adopts linear stabilized power supply chip to produce the power supply of the different magnitudes of voltage of each several part demand.Linear stabilized power supply chip can provide low noise power supply, guarantees the performance of analog circuit.
Digital circuit on plate is used digital power power supply, adopts switching power source chip to produce the power supply of the different magnitudes of voltage of each several part demand.Switching power source chip can provide higher power supply conversion efficiency, reduces the power loss in power supply transfer process.
Although illustrated and described embodiments of the invention, those having ordinary skill in the art will appreciate that: in the situation that not departing from principle of the present invention and aim, can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is limited by claim and equivalent thereof.
Claims (10)
1. a multiband TETRA Digital Clustering checkout gear, it carries out multichannel reception in a frequency range, and carry out the reception of up-downgoing passage simultaneously, when realizing multiple terminals and multiple base station signal, capture, described multiple receive path is completely independent, described checkout gear also supports nonsynchronous multiple signals to receive, and it comprises multiband receiver radio frequency front end, Digital IF Processing plate, reference source, secondary power supply, it is characterized in that:
Described multiband receiver radio frequency front end has multiple receiving paths, a frequency range is supported on every road, thereby realizing multiband receives, each frequency range is broadband reception, guarantee that Digital IF Processing plate can carry out multichannel reception in frequency range, multiband receiver radio frequency front end has again independently two cover paths of up-downgoing, supports that up-downgoing receives simultaneously;
Described Digital IF Processing plate receives the signal in a band bandwidth, carries out the reception of multifrequency point simultaneously, is responsible for receiving the processing of data and the control of complete machine, and external interface is provided;
Described reference source provides reference clock;
Described secondary power supply provides working power for above each several part.
2. multiband TETRA Digital Clustering checkout gear as claimed in claim 1, wherein said receiver radio frequency front end relies on numerical-control attenuator to receive dynamically for entirety provides, and receiver is inner adopts multistage numerical-control attenuator.
3. multiband TETRA Digital Clustering checkout gear as claimed in claim 1, wherein said Digital IF Processing plate comprises that A/D Acquisition Circuit, phase-locked loop circuit pll clock produce circuit, on-site programmable gate array FPGA+OMAP processor circuit and power supply.
4. multiband TETRA Digital Clustering checkout gear as claimed in claim 3, wherein said on-site programmable gate array FPGA part is for carrying out whole signal processing of described multiband TETRA Digital Clustering checkout gear, it receives according to band bandwidth, can receive all signals in frequency range, in actual use, select multiple frequency ranges to receive according to arranging, described OMAP part is used for carrying out the protocol data analytical capabilities of described multiband TETRA Digital Clustering checkout gear, and realizes external interface function.
5. multiband TETRA Digital Clustering checkout gear as claimed in claim 3, the main work clock of wherein said FPGA part is provided by described PLL circuit, and before master clock produces, described FPGA part need to rely on local crystal oscillator to produce clock operation PLL configurator.
6. a multiband receiver radio frequency front end, comprises two groups of antenna ports, preselection filter and receive paths, it is characterized in that:
One group of antenna port receives uplink band, and another group antenna port receives band downlink, when two groups of antenna ports can be realized up-downgoing, receives;
Described preselection filter is one group of filter, and when work, according to the filter of the corresponding corresponding band of the working frequency range gating of selecting, the multiband of realizing receiver receives;
Described receive path, according to the frequency difference receiving, adopts corresponding receive path to carry out signal reception, and the reception bandwidth of receive path is bin width, can realize multichannel and receive.
7. multiband receiver radio frequency front end as claimed in claim 6, wherein inputs described receive path from the signal of described preselection filter output.
8. multiband receiver radio frequency front end as claimed in claim 6, wherein according to the frequency receiving, described receive path comprises low noise amplifier LNA, frequency mixer, intermediate-frequency filter and controllable gain amplifier, or comprises low noise amplifier LNA, frequency range selector, frequency mixer, intermediate-frequency filter and controllable gain amplifier.
9. the multiband TETRA Digital Clustering detection method of use multiband TETRA Digital Clustering checkout gear as described in claim 1-5, described multiband TETRA Digital Clustering checkout gear is operated in 6 cluster working frequency range of 350MHz to 800MHz, described reference source is exported three road reference clock signals, two-way offers multiband receiver radio frequency front end, and another road offers Digital IF Processing plate.
It comprises the following steps:
Described multiband receiver radio frequency front end arranges selective reception frequency range according to parameter, and reception signal is downconverted to intermediate-freuqncy signal output;
Described Digital IF Processing plate is sampled to the output signal of receiving front-end, and described multiband receiver radio frequency front end provides intermediate frequency output, and described Digital IF Processing plate is provided with intermediate frequency acquisition channel accordingly; Described Digital IF Processing plate carries out frequency sweep, down-conversion, variable Rate, demodulation, decoding and protocal analysis processing at numeric field, externally carries out exchanges data by Ethernet interface and serial ports, and controls display screen, the keyboard of front panel.
10. multiband TETRA Digital Clustering detection method as claimed in claim 9, wherein carries out Instrument working parameter input by front panel keyboard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310676115.8A CN103781085B (en) | 2013-12-11 | 2013-12-11 | A kind of multiband TETRA Digital Clusterings detection method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310676115.8A CN103781085B (en) | 2013-12-11 | 2013-12-11 | A kind of multiband TETRA Digital Clusterings detection method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103781085A true CN103781085A (en) | 2014-05-07 |
| CN103781085B CN103781085B (en) | 2017-07-25 |
Family
ID=50572801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310676115.8A Active CN103781085B (en) | 2013-12-11 | 2013-12-11 | A kind of multiband TETRA Digital Clusterings detection method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103781085B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104661287A (en) * | 2015-03-23 | 2015-05-27 | 重庆邮电大学 | Multimode support parallel multichannel fast frequency sweeping method and multimode support parallel multichannel fast frequency sweeping system |
| CN105099478A (en) * | 2015-08-21 | 2015-11-25 | 小米科技有限责任公司 | Apparatus and method for improving receiving sensitivity of RF link |
| CN105553586A (en) * | 2015-12-21 | 2016-05-04 | 中国电子科技集团公司第四十一研究所 | Multipath fading channel test device |
| CN106301601A (en) * | 2016-08-31 | 2017-01-04 | 成都九华圆通科技发展有限公司 | A kind of drive test data acquisition method |
| CN106385292A (en) * | 2016-08-31 | 2017-02-08 | 成都九华圆通科技发展有限公司 | Drive test data collecting system and method |
| CN106385708A (en) * | 2016-09-13 | 2017-02-08 | 哈尔滨海能达科技有限公司 | Data transmission method and wireless link machine |
| CN106487401A (en) * | 2016-10-12 | 2017-03-08 | 武汉大学 | A kind of AIS receiver based on Super heterodyne principle |
| CN107465464A (en) * | 2017-09-05 | 2017-12-12 | 广东阿尔创通信技术股份有限公司 | Mobile communication multiband sourceless seism tester and method of testing |
| CN109348489A (en) * | 2018-12-05 | 2019-02-15 | 北京锐安科技有限公司 | A kind of TD-LTE endpoint detection system |
| CN109714066A (en) * | 2019-03-05 | 2019-05-03 | 成都中亚通茂科技股份有限公司 | A kind of full frequency band radio frequency directly adopts receiving and processing equipment |
| CN109995387A (en) * | 2019-03-01 | 2019-07-09 | 电子科技大学 | A kind of method that broadband receiver inhibits Image interference |
| CN110221650A (en) * | 2019-06-18 | 2019-09-10 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
| CN111182476A (en) * | 2020-01-06 | 2020-05-19 | 广州维德科技有限公司 | DMR/PDT multi-carrier frequency base station communication system and carrier frequency base station communication method thereof |
| CN113055965A (en) * | 2019-12-10 | 2021-06-29 | 成都鼎桥通信技术有限公司 | Wide-narrow dual-mode cluster terminal and mode switching method and device thereof |
| CN114077297A (en) * | 2020-08-21 | 2022-02-22 | 爱思开海力士有限公司 | Electronic device and operation method thereof |
| CN115792376A (en) * | 2023-02-09 | 2023-03-14 | 成都九洲迪飞科技有限责任公司 | Broadband spectrum monitoring system and method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102096079B (en) * | 2009-12-12 | 2013-12-11 | 杭州中科微电子有限公司 | Method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and module thereof |
| CN102130697B (en) * | 2010-01-20 | 2015-05-27 | 华为技术有限公司 | Receiver, transmitter and feedback device, transceiver and signal processing method |
| CN102243313A (en) * | 2011-04-25 | 2011-11-16 | 上海迦美信芯通讯技术有限公司 | Dual-channel radio frequency receiver and frequency planning method thereof |
| CN202160172U (en) * | 2011-08-17 | 2012-03-07 | 赵熠明 | X wave band broadband high resolution digital channelizing receiver |
-
2013
- 2013-12-11 CN CN201310676115.8A patent/CN103781085B/en active Active
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104661287B (en) * | 2015-03-23 | 2019-02-22 | 重庆邮电大学 | A kind of parallel multi-channel rapid frequency-sweeping method and system for supporting multimode |
| CN104661287A (en) * | 2015-03-23 | 2015-05-27 | 重庆邮电大学 | Multimode support parallel multichannel fast frequency sweeping method and multimode support parallel multichannel fast frequency sweeping system |
| CN105099478A (en) * | 2015-08-21 | 2015-11-25 | 小米科技有限责任公司 | Apparatus and method for improving receiving sensitivity of RF link |
| CN105099478B (en) * | 2015-08-21 | 2018-09-04 | 小米科技有限责任公司 | Improve the device and method of radio frequency link receiving sensitivity |
| CN105553586A (en) * | 2015-12-21 | 2016-05-04 | 中国电子科技集团公司第四十一研究所 | Multipath fading channel test device |
| CN106301601A (en) * | 2016-08-31 | 2017-01-04 | 成都九华圆通科技发展有限公司 | A kind of drive test data acquisition method |
| CN106385292A (en) * | 2016-08-31 | 2017-02-08 | 成都九华圆通科技发展有限公司 | Drive test data collecting system and method |
| CN106385292B (en) * | 2016-08-31 | 2019-10-11 | 成都九华圆通科技发展有限公司 | A kind of drive test data acquisition system and method |
| CN106385708A (en) * | 2016-09-13 | 2017-02-08 | 哈尔滨海能达科技有限公司 | Data transmission method and wireless link machine |
| CN106385708B (en) * | 2016-09-13 | 2020-05-12 | 哈尔滨海能达科技有限公司 | Data transmission method and wireless link machine |
| CN106487401A (en) * | 2016-10-12 | 2017-03-08 | 武汉大学 | A kind of AIS receiver based on Super heterodyne principle |
| CN106487401B (en) * | 2016-10-12 | 2019-02-26 | 武汉大学 | A kind of AIS receiver based on Super heterodyne principle |
| CN107465464A (en) * | 2017-09-05 | 2017-12-12 | 广东阿尔创通信技术股份有限公司 | Mobile communication multiband sourceless seism tester and method of testing |
| CN109348489B (en) * | 2018-12-05 | 2021-11-02 | 北京锐安科技有限公司 | TD-LTE terminal detection system |
| CN109348489A (en) * | 2018-12-05 | 2019-02-15 | 北京锐安科技有限公司 | A kind of TD-LTE endpoint detection system |
| CN109995387B (en) * | 2019-03-01 | 2021-03-30 | 电子科技大学 | Method for inhibiting image interference of broadband receiver |
| CN109995387A (en) * | 2019-03-01 | 2019-07-09 | 电子科技大学 | A kind of method that broadband receiver inhibits Image interference |
| CN109714066A (en) * | 2019-03-05 | 2019-05-03 | 成都中亚通茂科技股份有限公司 | A kind of full frequency band radio frequency directly adopts receiving and processing equipment |
| CN110221650A (en) * | 2019-06-18 | 2019-09-10 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
| CN113055965A (en) * | 2019-12-10 | 2021-06-29 | 成都鼎桥通信技术有限公司 | Wide-narrow dual-mode cluster terminal and mode switching method and device thereof |
| CN113055965B (en) * | 2019-12-10 | 2023-03-31 | 成都鼎桥通信技术有限公司 | Wide-narrow dual-mode cluster terminal and mode switching method and device thereof |
| CN111182476A (en) * | 2020-01-06 | 2020-05-19 | 广州维德科技有限公司 | DMR/PDT multi-carrier frequency base station communication system and carrier frequency base station communication method thereof |
| CN114077297A (en) * | 2020-08-21 | 2022-02-22 | 爱思开海力士有限公司 | Electronic device and operation method thereof |
| CN114077297B (en) * | 2020-08-21 | 2024-03-15 | 爱思开海力士有限公司 | Electronic device and operation method thereof |
| CN115792376A (en) * | 2023-02-09 | 2023-03-14 | 成都九洲迪飞科技有限责任公司 | Broadband spectrum monitoring system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103781085B (en) | 2017-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103781085A (en) | Multi-frequency range TETRA digital cluster detection method and apparatus | |
| CN102523596B (en) | High speed frequency sweep apparatus and realization method thereof | |
| CN101095324B (en) | System and method for blind source separation of wireless communication signals | |
| CN101257465B (en) | Method for converting signal, quadrature demodulator as well as zero intermediate frequency receiver | |
| CN100542068C (en) | Realize the two-way conversion integrated circuit between RF signal and the intermediate frequency wire signal | |
| CN107888276B (en) | Multi-frequency band multi-mode modulation and demodulation device | |
| CN106849984A (en) | A kind of shared method and system of multi-mode radio frequency | |
| US8498602B2 (en) | Architecture of future open wireless architecture (OWA) radio system | |
| CN108196230B (en) | Two-stage digital channelized receiving device of passive radar | |
| CN101116272A (en) | Communication apparatus | |
| CN108377155A (en) | A kind of multi-standard, multiband, miniaturization communication receiver apparatus | |
| CN104283574B (en) | software radio receiver circuit | |
| CN201699698U (en) | Multiplex receiving device, receiver and base station | |
| CN103762979B (en) | Broadband frequency source for LTE channel simulator | |
| CN204334556U (en) | A kind of vehicle mounted communication module | |
| CN101908896A (en) | Multi-frequency band radio-frequency receiver | |
| CN101867390A (en) | Anti-interference method and system for mobile communication terminal | |
| WO2012152034A1 (en) | Dual-mode radio frequency module, dual-mode radio frequency transmitting and receiving method and user terminal | |
| CN201878199U (en) | Interphone with functions of mobile phone | |
| US7158583B2 (en) | Multiple communication protocols with common sampling rate | |
| CN102137513A (en) | Global system for mobile communication (GSM)/enhanced data rate for GSM evolution (EDGE)/time division synchronous code division multiple access (TD-SCDMA) transceiver and receiver | |
| CN101902287A (en) | Calibration test system, device and method of receivers | |
| CN100426684C (en) | 2-carrier receiving module and multiple-carrier base station receiver | |
| CN204089809U (en) | General digital integrated communication hardware platform | |
| CN200983589Y (en) | Bidirectional conversion integrated circuit between RF signals and middle-frequency wired signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100081 No. 5, Zhongguancun South Street, Haidian District, Beijing Co-patentee after: THE STATE RADIO MONITORING CENTER TESTING CENTER Patentee after: BEIJING INSTITUTE OF TECHNOLOGY Co-patentee after: RADIOSKY (BEIJING) TECHNOLOGY Co.,Ltd. Address before: 100081 No. 5, Zhongguancun South Street, Haidian District, Beijing Co-patentee before: THE STATE RADIO MONITORING CENTER TESTING CENTER Patentee before: BEIJING INSTITUTE OF TECHNOLOGY Co-patentee before: RADIOSKY TESTING SERVICES (BEIJING) Ltd. |