CN103745681B - A kind of graphicalphanumeric generator based on complex programmable device - Google Patents
A kind of graphicalphanumeric generator based on complex programmable device Download PDFInfo
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Abstract
The invention belongs to figure and produce technical field, it relates to a kind of graphicalphanumeric generator based on complex programmable device. Described graphicalphanumeric generator comprises connected complex programmable device and DDR3SDRAM frame memory device. Wherein, complex programmable device comprises arm processor, multiterminal mouth DDR3SDRAM controller, DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the 2nd data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffering module, the 2nd buffering module and the 3rd buffering module. Wherein, multiterminal mouth DDR3SDRAM controller deposits module for reading and writing with arm processor, DDR3SDRAM frame, DDR3SDRAM frame memory device is connected; DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the 2nd data conversion module; Sequence generation module deposits module for reading and writing with arm processor, DDR3SDRAM frame, the first data conversion module, the 2nd data conversion module are connected. Graphicalphanumeric generator of the present invention can significantly improve circuit level and reliability, reduces circuit power consumption.
Description
Technical field:
The invention belongs to figure and produce technical field, it relates to a kind of graphicalphanumeric generator based on complex programmable device.
Background technology:
Graphicalphanumeric generator is the supporting important parts of liquid-crystal display, become by multiple digital circuit combination of devices, main function be according to mapping instruction, make graph parameter, data, use various digital processing technology, generate graphic picture data in real time, show with liquid crystal display. Existing graphicalphanumeric generator generally adopts Digital processing device DSP, programmable logic device part FPGA and random access frame memory device SRAM as main processing element, digital processing device runs mapping algorithm program, it is responsible for generating graph data, programmable logic device part has assisted the generation of complex figure data as coprocessor, and random access frame memory device is used for register map graphic data.
Along with the development of technology, the resolving power of liquid-crystal display is more and more higher, it is necessary to the image content of display is also more and more complicated, but the power consumption requiring product is lower, integrated level is higher, and graphics generation circuit is had higher requirement by this. There is following defect in current existing graphicalphanumeric generator: circuit scale is huge, integrated level and reliability is not high, figure generation efficiency is low, power consumption can be in any more, be difficult to meet high resolving power and real-time application demand.
Summary of the invention:
The object of the present invention: the graphicalphanumeric generator that a kind of integrated level height, strong adaptability, reliability height, low in energy consumption, excellent performance are provided.
In order to adapt to the trend of machine load passenger cabin liquid-crystal display to low-power consumption, high integration, light scale of construction development, a kind of high integration, high-performance, low-power consumption graphicalphanumeric generator implementation are proposed, adopt complex programmable device as main process chip, its integrated arm processor is as the main processing apparatus of graphic operation, adopt DDR3SDRAM frame memory device, significantly improve circuit level. Utilize complex programmable device DDR3SDRAM frame memory device to be write, read, null clear operation, it is achieved motion graphics generate with display function.
The technical scheme of the present invention: a kind of graphicalphanumeric generator based on complex programmable device, comprise connected complex programmable device and DDR3SDRAM frame memory device, wherein, described complex programmable device comprises arm processor, multiterminal mouth DDR3SDRAM controller, DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the 2nd data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffering module, the 2nd buffering module, the 3rd buffering module. Wherein multiterminal mouth DDR3SDRAM controller deposits module for reading and writing with arm processor, DDR3SDRAM frame, DDR3SDRAM frame memory device is connected; DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the 2nd data conversion module; Sequence generation module deposits module for reading and writing with arm processor, DDR3SDRAM frame, the first data conversion module, the 2nd data conversion module are connected.
Described arm processor, for carrying out drawing algorithm computing, obtain drawing computing data, send write operation request to multiterminal mouth DDR3SDRAM controller, by multiterminal mouth DDR3SDRAM controller, drawing computing data are write the buffering module in DDR3SDRAM frame memory device.
Described multiterminal mouth DDR3SDRAM controller, for carrying out arbitration and prioritization process to the write received, reading, clear empty three kinds of operator schemes.
Described DDR3SDRAM frame deposits module for reading and writing, for being sent reading and null clear operation request to the buffering module in DDR3SDRAM frame memory device by multiterminal mouth DDR3SDRAM controller.
The first described data conversion module, for converting the data stream form that DDR3SDRAM module for reading and writing can receive to by complete zero signal.
The 2nd described data conversion module, for changing the digital RGB video signal meeting liquid crystal display driver' s timing standard into by the stream compression that DDR3SDRAM module for reading and writing is sent.
Described sequence generation module, for generation of arm processor, multiterminal mouth DDR3SDRAM controller, the first data conversion module, the 2nd data conversion module work needed for all kinds of time sequential signal.
Described DDR3SDRAM frame memory device, for carrying out the buffered of draw data, comprising the first buffering module, the 2nd and cushion module, the 3rd buffering module, the field synchronization signal that described the first buffering module, the 2nd cushions module, the operator scheme of the 3rd buffering module sends taking sequence generation module carried out replacing switching as the cycle.
Further, said write operator scheme is that arm processor is by DDR3SDRAM controller certain buffering module write drawing computing data in DDR3SDRAM frame memory device. Read mode is that DDR3SDRAM frame deposits module for reading and writing by multiterminal mouth DDR3SDRAM controller certain buffering module reading draw data from DDR3SDRAM frame memory device. Null clear operation pattern be DDR3SDRAM frame deposit module for reading and writing by multiterminal mouth DDR3SDRAM controller in DDR3SDRAM frame memory device certain buffering module write full zero data.
The useful effect of the present invention:
Graphicalphanumeric generator of the present invention is using complex programmable device as main process chip, and it is integrated with arm processor and programmable logic resource, adopts DDR3SDRAM frame memory device, drastically increases integrated level and the reliability of circuit, reduce hardware power consumption. In addition, DDR3SDRAM frame memory device is provided with three buffering modules, reaches the effect to three buffer memory parallel processing with the high bandwidth characteristic of the high speed of DDR3SDRAM, it is to increase the efficiency that figure produces and shows. The advantages such as this graphicalphanumeric generator has circuit level height, low in energy consumption, volume is little, data bandwidth height, processing speed are fast, the display of figure generation efficiency height, dynamic menu is smooth, can compatible multiple resolution graphics picture.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of graphicalphanumeric generator of the present invention;
Wherein, 1-complex programmable device, 2-ARM treater, 3-multiterminal mouth DDR3SDRAM controller, 4-DDR3SDRAM frame deposit module for reading and writing, 5-first data conversion module, 6-the 2nd data conversion module, 7-sequence generation module, 8-DDR3SDRAM frame memory device, 9-first cushions module, 10-the 2nd cushions module, 11-the 3rd cushions module.
Embodiment
Below by specific embodiment, the present invention is described in detail:
Referring to Fig. 1, it is the functional block diagram of graphicalphanumeric generator of the present invention.
A kind of graphicalphanumeric generator based on complex programmable device, comprise connected complex programmable device and DDR3SDRAM frame memory device, it is characterized in that: described complex programmable device comprises arm processor, multiterminal mouth DDR3SDRAM controller, DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the 2nd data conversion module, sequence generation module, DDR3SDRAM frame memory device comprises the first buffering module, the 2nd buffering module, the 3rd buffering module. Wherein multiterminal mouth DDR3SDRAM controller deposits module for reading and writing with arm processor, DDR3SDRAM frame, DDR3SDRAM frame memory device is connected; DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the 2nd data conversion module; Sequence generation module deposits module for reading and writing with arm processor, DDR3SDRAM frame, the first data conversion module, the 2nd data conversion module are connected.
Described arm processor, for carrying out drawing algorithm computing, obtain drawing computing data, send write operation request to multiterminal mouth DDR3SDRAM controller, by multiterminal mouth DDR3SDRAM controller, drawing computing data are write the buffering module in DDR3SDRAM frame memory device.
Described sequence generation module, for generation of arm processor, multiterminal mouth DDR3SDRAM controller, the first data conversion module, the 2nd data conversion module work needed for all kinds of time sequential signal, comprising meeting the line synchronising signal Hsync of VSEA standard, field synchronization signal Vsync, horizontal blanking signal Hblank, field blanking signal Vblank, enable signal Enable, also comprise DDR3SDRAM module for reading and writing frame starting signal Fsync, arm processor interruption controls signal irq. Fsync signal and irq signal are cycle signal, and identical with the Vsync signal period. for controlling, arm processor carries out drawing computing to described irq interruption controls signal, arm processor often receives an irq signal, then enter interrupt service routine, in interrupt service routine first according on the operator schemes of three buffering modules in DDR3SDRAM in a Vsync signal period, the first address of buffering module corresponding to three kinds of operator schemes is switched, also within the current Vsync signal period, namely change the operator scheme of three buffering modules, determine that ARM writes in DDR3SDRAM the first address of buffering module cushioned corresponding to the first address of module and the reading of DDR3SDRAM module for reading and writing and clear operation, corresponding register in DDR3SDRAM module for reading and writing is write by ARM software by reading the first address with the buffering module corresponding to clear operation, then arm processor carries out drawing calculation process. DDR3SDRAM frame deposits module for reading and writing after receiving Fsync initiating signal, corresponding buffering module is read and null clear operation respectively according to first address.
Described multiterminal mouth DDR3SDRAM controller, for carrying out arbitration and prioritization process to the write received, reading, clear empty three kinds of operator schemes. Write, reading, clear empty three kinds of operator schemes are corresponding to three buffering modules in DDR3SDRAM frame memory device. Said write operator scheme is arm processor certain buffering module write drawing computing data in DDR3SDRAM frame memory device; Read mode is that DDR3SDRAM frame deposits module for reading and writing certain buffering module reading draw data from DDR3SDRAM frame memory device; Null clear operation pattern be DDR3SDRAM frame deposit module for reading and writing in DDR3SDRAM frame memory device certain buffering module write full zero data. In a certain moment, only a kind of access request is responded, and also namely only a buffering is in accessed state, but three kinds of access request are all responded within a frame period, and also namely three bufferings are all accessed, and access type is different.
Described DDR3SDRAM frame deposits module for reading and writing, for writing full zero data by multiterminal mouth DDR3SDRAM controller to DDR3SDRAM frame memory device a certain buffering module, or from a certain buffering module, read frame picture data, the Fsync signal that two kinds of operator schemes are sent by sequence generation module starts, a Fsync pulse signal often occurs, then start and once access, the frame data that once access is corresponding complete. The Fsync signal period is identical with the Vsync signal period.
Described DDR3SDRAM frame memory device, for carrying out the buffered of draw data, comprises the first buffering module, the 2nd buffering module, the 3rd buffering module. Described the first buffering module, the 2nd cushions module, the operator scheme of the 3rd buffering module switches by the cycle of Vsync signal, and first address of each buffering module is set by arm processor, and first interval, address exceedes screen pixels sum. Three buffering module correspondence writes, reading, clear empty three kinds of operator schemes. Referring to table 1, in the current Vsync signal period, the operating method of three buffering modules is different, and when a certain buffering module is write operation, then in next Vsync cycle, same buffering module switches to read operation; When a certain buffering module is read operation, then in next Vsync cycle, same buffering module switches to null clear operation; When a certain buffering module is null clear operation, then in next Vsync signal period, same buffering module switches to write operation. By this kind of buffering module handover mechanism, within the previous frame cycle, complete write operation to ensure to carry out in current frame period the buffering module of read operation, read up-to-date data from this buffering module; The buffering module carrying out null clear operation in current frame period has completed read operation within the previous frame cycle, and this buffering module carries out vacancy reason clearly; The buffering module carrying out write operation in current frame period has completed null clear operation within the previous frame cycle, and this buffering module is write current draw data.
Table 1
The first described data conversion module, for complete zero signal being converted to the data stream form that DDR3SDRAM module for reading and writing can receive, after multiterminal mouth DDR3SDRAM controller is arbitrated, write the buffering module of corresponding clear operation in DDR3SDRAM frame memory device by DDR3SDRAM module for reading and writing.
The 2nd described data conversion module is used for changing DDR3SDRAM module for reading and writing into meet liquid crystal display driver' s timing standard digital RGB video signal through the multiterminal mouth DDR3SDRAM controller arbitration stream compression that corresponding read operation buffering module reads from DDR3SDRAM frame memory device.
The graphic operation result of arm processor in complex programmable logic device is write DDR3SDRAM frame memory device based on the graphicalphanumeric generator of complex programmable device by the present invention in sum, DDR3SDRAM Read-write Catrol module reads the draw data of arm processor write from DDR3SDRAM frame memory device, and the data of write are carried out vacancy reason clearly. To the write of in DDR3SDRAM frame memory device three bufferings, reading, null clear operation by the cycle of Vsync signal by arm processor control switching, and three kinds of operations are arbitrated through multiterminal mouth DDR3SDRAM controller within a Vsync signal period. The present invention can significantly reduce hardware circuit scale, it is to increase circuit reliability, reduces power consumption, and supports multiple resolution graphics.
Described complex programmable device, during enforcement, can select the complex programmable device CycloneV series of the integrated ARM kernel of Altera company, it is also possible to select the complex programmable device Zynq-7000 series of the integrated ARM kernel of Xilinx company. After selected complex programmable device, sequence generation module, the first data conversion module, the 2nd data conversion module adopt VHDL or Verilog hardware description language programming realization by the programmable logic resource that complex programmable device inside is integrated, it is possible to adopt pattern input mode to realize. DDR3SDRAM frame deposits module for reading and writing can adopt VHDL or Verilog hardware description language programming realization, it is possible to the IP kernel adopting complex programmable device inside integrated realizes.
Described DDR3SDRAM frame memory device, during enforcement, the DDR3SDRAM storer that Micron company can be selected to produce realizes, it is possible to the similar DDR3SDRAM storer selecting other companies to produce realizes.
Claims (4)
1. the graphicalphanumeric generator based on complex programmable device, it is characterized in that, comprise connected complex programmable device and DDR3SDRAM frame memory device, wherein, described complex programmable device comprises arm processor, multiterminal mouth DDR3SDRAM controller, DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the 2nd data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffering module, the 2nd buffering module, the 3rd buffering module; Wherein multiterminal mouth DDR3SDRAM controller deposits module for reading and writing with arm processor, DDR3SDRAM frame, DDR3SDRAM frame memory device is connected; DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the 2nd data conversion module; Sequence generation module deposits module for reading and writing with arm processor, DDR3SDRAM frame, the first data conversion module, the 2nd data conversion module are connected;
Described arm processor, for carrying out drawing algorithm computing, obtain drawing computing data, send write operation request to multiterminal mouth DDR3SDRAM controller, by multiterminal mouth DDR3SDRAM controller, drawing computing data are write the buffering module in DDR3SDRAM frame memory device;
Described multiterminal mouth DDR3SDRAM controller, for carrying out arbitration and prioritization process to the write received, reading, clear empty three kinds of operator schemes;
Described DDR3SDRAM frame deposits module for reading and writing, for being sent reading and null clear operation request to the buffering module in DDR3SDRAM frame memory device by multiterminal mouth DDR3SDRAM controller;
The first described data conversion module, for converting the data stream form that DDR3SDRAM module for reading and writing can receive to by complete zero signal;
The 2nd described data conversion module, for changing the digital RGB video signal meeting liquid crystal display driver' s timing standard into by the stream compression that DDR3SDRAM module for reading and writing is sent;
Described sequence generation module, for generation of arm processor, multiterminal mouth DDR3SDRAM controller, the first data conversion module, the 2nd data conversion module work needed for all kinds of time sequential signal;
Described DDR3SDRAM frame memory device, for carrying out the buffered of draw data, comprising the first buffering module, the 2nd and cushion module, the 3rd buffering module, the field synchronization signal that described the first buffering module, the 2nd cushions module, the operator scheme of the 3rd buffering module sends taking sequence generation module carried out replacing switching as the cycle.
2. a kind of graphicalphanumeric generator based on complex programmable device as claimed in claim 1, it is characterized in that, further, said write operator scheme is that arm processor is by DDR3SDRAM controller one of three buffering modules write drawing computing data in DDR3SDRAM frame memory device.
3. a kind of graphicalphanumeric generator based on complex programmable device as claimed in claim 1, it is characterized in that, further, described read mode is that DDR3SDRAM frame deposits module for reading and writing by multiterminal mouth DDR3SDRAM controller one of three buffering modules reading draw data from DDR3SDRAM frame memory device.
4. a kind of graphicalphanumeric generator based on complex programmable device as claimed in claim 1, it is characterized in that, further, described null clear operation pattern is that DDR3SDRAM frame deposits module for reading and writing by multiterminal mouth DDR3SDRAM controller one of three buffering modules full zero data of write in DDR3SDRAM frame memory device.
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