CN103745681A - Pattern generator based on integrated programmable device - Google Patents
Pattern generator based on integrated programmable device Download PDFInfo
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- CN103745681A CN103745681A CN201310626809.0A CN201310626809A CN103745681A CN 103745681 A CN103745681 A CN 103745681A CN 201310626809 A CN201310626809 A CN 201310626809A CN 103745681 A CN103745681 A CN 103745681A
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Abstract
The invention pertains to the technical field of pattern generation, and relates to a pattern generator based on an integrated programmable device. The pattern generator comprises an integrated programmable device and a DDR3SDRAM frame storage device which are connected. The integrated programmable device comprises an ARM processor, a multiport DDR3SDRAM controller, a DDR3SDRAM frame storage read-write module, a first data conversion module, a second data conversion module, and a timing sequence generation module. The DDR3SDRAM frame storage device comprises a first buffer module, a second buffer module and a third buffer module. The multiport DDR3SDRAM controller is connected with the ARM processor, the DDR3SDRAM frame storage read-write module and the DDR3SDRAM frame storage device. The DDR3SDRAM frame storage read-write module is connected with the first data conversion module and the second data conversion module. The timing sequence generation module is connected with the ARM processor, the DDR3SDRAM frame storage read-write module, the first data conversion module and the second data conversion module. The pattern generator of the invention can be used to significantly improve the circuit integration level and the reliability, and reduce the circuit power consumption.
Description
Technical field:
The invention belongs to figure and produce technical field, relate to a kind of pattern generator based on comprehensive programming device.
Background technology:
Pattern generator is a supporting vitals of liquid crystal display, by multiple digital circuit combination of devices, formed, major function is according to mapping instruction, makes graph parameter, data, uses various digital processing technologies, generate in real time graphic picture data, with liquid crystal display, show.Existing pattern generator generally adopts digital processing device DSP, programmable logic device (PLD) FPGA and random access frame memory device SRAM as main processing block, digital processing unit operation mapping algorithm routine, be responsible for generating graph data, programmable logic device (PLD) has been assisted the generation of complex figure data as coprocessor, random access frame memory device is for register map graphic data.
Along with the development of technology, the resolution of liquid crystal display is more and more higher, needs the image content showing also to become increasingly complex, but require the power consumption of product lower, integrated level is higher, this has higher requirement to graphics generation circuit.There is following defect in current existing pattern generator: circuit scale is huge, integrated level and reliability is not high, figure generation efficiency is low, power consumption can be in any more, be difficult to meet high resolving power and real-time application demand.
Summary of the invention:
Object of the present invention: provide that a kind of integrated level is high, strong adaptability, reliability are high, low in energy consumption, the pattern generator of excellent performance.
In order to adapt to the trend of airborne passenger cabin liquid crystal display to low-power consumption, high integration, light scale of construction development, a kind of high integration, high-performance, low-power consumption pattern generator implementation are proposed, adopt comprehensive programming device as main process chip, its integrated arm processor is as graphic operation primary processor part, adopt DDR3SDRAM frame memory device, significantly improve circuit level.Utilize comprehensive programming device to write, read, empty operation to DDR3SDRAM frame memory device, realize motion graphics and generate and Presentation Function.
Technical scheme of the present invention: a kind of pattern generator based on comprehensive programming device, comprise connected comprehensive programming device and DDR3SDRAM frame memory device, wherein, described comprehensive programming device comprises that arm processor, multiport DDR3SDRAM controller, DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the second data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffer module, the second buffer module, the 3rd buffer module.Wherein multiport DDR3SDRAM controller is deposited module for reading and writing with arm processor, DDR3SDRAM frame, DDR3SDRAM frame memory device is connected; DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the second data conversion module; Sequence generation module and arm processor, DDR3SDRAM frame are deposited module for reading and writing, the first data conversion module, the second data conversion module and are connected.
Described arm processor, be used for carrying out drawing algorithm computing, obtain the operational data of drawing, to multiport DDR3SDRAM controller, send write operation request, by multiport DDR3SDRAM controller, drawing operational data is write to the buffer module in DDR3SDRAM frame memory device.
Described multiport DDR3SDRAM controller, for arbitrating and prioritization processing the three kinds of operator schemes that write, read, empty that receive.
Described DDR3SDRAM frame is deposited module for reading and writing, for being sent and read and empty operation requests to the buffer module of DDR3SDRAM frame memory device by multiport DDR3SDRAM controller.
The first described data conversion module, for converting all-zero signal to the receivable data stream format of DDR3SDRAM module for reading and writing.
The second described data conversion module, converts the digital rgb vision signal that meets liquid crystal display driving sequential standard to for the data stream that DDR3SDRAM module for reading and writing is sent.
Described sequence generation module, for generation of arm processor, multiport DDR3SDRAM controller, the first data conversion module, the required all kinds of clock signals of the second data conversion module work.
Described DDR3SDRAM frame memory device, for carrying out the buffered of draw data, comprise the first buffer module, the second buffer module, the 3rd buffer module, the field sync signal that the operator scheme of described the first buffer module, the second buffer module, the 3rd buffer module is sent take sequence generation module replaces switching as the cycle.
Further, to be arm processor write drawing operational data by DDR3SDRAM controller to certain buffer module in DDR3SDRAM frame memory device to said write operator scheme.Read mode is that DDR3SDRAM frame is deposited module for reading and writing and read draw data by multiport DDR3SDRAM controller certain buffer module from DDR3SDRAM frame memory device.Emptying operator scheme and be DDR3SDRAM frame deposits module for reading and writing and to certain buffer module in DDR3SDRAM frame memory device, writes full remainder certificate by multiport DDR3SDRAM controller.
Beneficial effect of the present invention:
Pattern generator of the present invention is using comprehensive programming device as main process chip, and it is integrated arm processor and programmable logic resource adopts DDR3SDRAM frame memory device, greatly improved integrated level and the reliability of circuit, reduced hardware power consumption.In addition, in DDR3SDRAM frame memory device, be provided with three buffer modules, with the high speed high bandwidth characteristic of DDR3SDRAM, reach the effect to three buffer memory parallel processings, improve the efficiency that figure produces and shows.This pattern generator has the advantages such as circuit level is high, low in energy consumption, volume is little, data bandwidth is high, processing speed is fast, and figure generation efficiency is high, dynamic menu shows smoothness, can compatible multiple resolution graphics picture.
Accompanying drawing explanation
Fig. 1 is the theory diagram of pattern generator of the present invention;
Wherein, the comprehensive programming device of 1-, 2-ARM processor, 3-multiport DDR3SDRAM controller, 4-DDR3SDRAM frame are deposited module for reading and writing, 5-the first data conversion module, 6-the second data conversion module, 7-sequence generation module, 8-DDR3SDRAM frame memory device, 9-the first buffer module, 10-the second buffer module, 11-the 3rd buffer module.
Embodiment
Below by specific embodiment, the present invention is described in detail:
Refer to Fig. 1, it is the theory diagram of pattern generator of the present invention.
A kind of pattern generator based on comprehensive programming device, comprise connected comprehensive programming device and DDR3SDRAM frame memory device, it is characterized in that: described comprehensive programming device comprises that arm processor, multiport DDR3SDRAM controller, DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the second data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffer module, the second buffer module, the 3rd buffer module.Wherein multiport DDR3SDRAM controller is deposited module for reading and writing with arm processor, DDR3SDRAM frame, DDR3SDRAM frame memory device is connected; DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the second data conversion module; Sequence generation module and arm processor, DDR3SDRAM frame are deposited module for reading and writing, the first data conversion module, the second data conversion module and are connected.
Described arm processor, be used for carrying out drawing algorithm computing, obtain the operational data of drawing, to multiport DDR3SDRAM controller, send write operation request, by multiport DDR3SDRAM controller, drawing operational data is write to the buffer module in DDR3SDRAM frame memory device.
Described sequence generation module, for generation of arm processor, multiport DDR3SDRAM controller, the first data conversion module, the required all kinds of clock signals of the second data conversion module work, comprising line synchronizing signal Hsync, the field sync signal Vsync, horizontal blanking signal Hblank, field blanking signal Vblank, the enable signal Enable that meet VSEA standard, also comprise that DDR3SDRAM module for reading and writing frame starting signal Fsync, arm processor interrupt control signal irq.Fsync signal and irq signal are periodic signal, and identical with the Vsync signal period.Described irq interrupts control signal and is used for controlling the arm processor computing of drawing, arm processor often receives irq signal one time, enter interrupt service routine, in interrupt service routine first according on the operator scheme of three buffer modules in DDR3SDRAM in a Vsync signal period, three kinds of corresponding buffer module first addresss of operator scheme are switched, also within the current Vsync signal period, change the operator scheme of three buffer modules, determine that ARM writes the first address of buffer module in DDR3SDRAM and reading and the corresponding buffer module first address of clear operation of DDR3SDRAM module for reading and writing, to read with the corresponding buffer module first address of clear operation and write corresponding register in DDR3SDRAM module for reading and writing by ARM software, then the arm processor calculation process of drawing.DDR3SDRAM frame is deposited module for reading and writing after receiving Fsync enabling signal, according to first address, respectively corresponding buffer module is read and empty operation.
Described multiport DDR3SDRAM controller, for arbitrating and prioritization processing the three kinds of operator schemes that write, read, empty that receive.Write, read, empty three kinds of operator schemes corresponding to three buffer modules in DDR3SDRAM frame memory device.To be arm processor write drawing operational data to certain buffer module in DDR3SDRAM frame memory device to said write operator scheme; Read mode is that DDR3SDRAM frame is deposited module for reading and writing certain buffer module from DDR3SDRAM frame memory device and read draw data; Emptying operator scheme and be DDR3SDRAM frame deposits module for reading and writing and writes full remainder certificate to certain buffer module in DDR3SDRAM frame memory device.The a certain moment, only have a kind of request of access to meet with a response, also only have a buffering in accessed state, but three kinds of request of access all meet with a response within a frame period, also three bufferings are all accessed, and access type is different.
Described DDR3SDRAM frame is deposited module for reading and writing, for writing full remainder certificate by multiport DDR3SDRAM controller to a certain buffer module of DDR3SDRAM frame memory device, or from a certain buffer module, read a frame picture data, the Fsync signal that two kinds of operator schemes are sent by sequence generation module starts, Fsync pulse signal of every appearance, start once access, once frame data corresponding to access.The Fsync signal period is identical with the Vsync signal period.
Described DDR3SDRAM frame memory device, for carrying out the buffered of draw data, comprises the first buffer module, the second buffer module, the 3rd buffer module.The operator scheme of described the first buffer module, the second buffer module, the 3rd buffer module is switched take Vsync signal as the cycle, and the first address of each buffer module is set by arm processor, and first address interval exceedes screen pixels sum.Three buffer module correspondences write, read, empty three kinds of operator schemes.Refer to table 1, in the current Vsync signal period, the mode of operation of three buffer modules is different, and when a certain buffer module is write operation, in next Vsync cycle, same buffer module switches to read operation; When a certain buffer module is read operation, in next Vsync cycle, same buffer module switches to and empties operation; When a certain buffer module operates for emptying, in next Vsync signal period, same buffer module switches to write operation.By this kind of buffer module handover mechanism, to guarantee that the buffer module of carrying out read operation in current frame period has completed write operation within the previous frame cycle, reads up-to-date data from this buffer module; The buffer module that empties operation in current frame period has completed read operation within the previous frame cycle, and this buffer module is emptied to processing; The buffer module of carrying out write operation in current frame period has completed and has emptied operation within the previous frame cycle, and this buffer module is write to current draw data.
Table 1
The first described data conversion module, for converting all-zero signal to DDR3SDRAM module for reading and writing receivable data stream format, by DDR3SDRAM module for reading and writing, after the arbitration of multiport DDR3SDRAM controller, write the buffer module of corresponding clear operation in DDR3SDRAM frame memory device.
The second described data conversion module converts for DDR3SDRAM module for reading and writing is arbitrated to the data stream of reading from the corresponding read operation buffer module of DDR3SDRAM frame memory device through multiport DDR3SDRAM controller the digital rgb vision signal that meets liquid crystal display driving sequential standard to.
The pattern generator that the present invention is based in sum comprehensive programming device writes DDR3SDRAM frame memory device by the graphic operation result of arm processor in comprehensive programmable logic device (PLD), DDR3SDRAM read-write control module is read the draw data that arm processor writes from DDR3SDRAM frame memory device, and the data that write are emptied to processing.The operation that writes, reads, empties to three bufferings in DDR3SDRAM frame memory device is switched by arm processor control take Vsync signal as the cycle, and through multiport DDR3SDRAM controller, has arbitrated three kinds of operations within a Vsync signal period.The present invention can significantly reduce hardware circuit scale, improves circuit reliability, reduces power consumption, and supports multiple resolution graphics.
Described comprehensive programming device, during enforcement, can select the comprehensive programming device CycloneV series of the integrated ARM kernel of altera corp, also can select the comprehensive programming device Zynq-7000 series of the integrated ARM kernel of Xilinx company.After selected comprehensive programming device, sequence generation module, the first data conversion module, the second data conversion module adopt VHDL or the programming of Verilog hardware description language to realize by the inner integrated programmable logic resource of comprehensive programming device, also can adopt pattern input mode to realize.DDR3SDRAM frame is deposited module for reading and writing and can be adopted VHDL or the programming of Verilog hardware description language to realize, and also can adopt the inner integrated IP kernel of comprehensive programming device to realize.
Described DDR3SDRAM frame memory device, during enforcement, can select the DDR3SDRAM storer that Micron company produces to realize, and also can select the similar DDR3SDRAM storer that other companies produce to realize.
Claims (4)
1. the pattern generator based on comprehensive programming device, it is characterized in that, comprise connected comprehensive programming device and DDR3SDRAM frame memory device, wherein, described comprehensive programming device comprises that arm processor, multiport DDR3SDRAM controller, DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the second data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffer module, the second buffer module, the 3rd buffer module; Wherein multiport DDR3SDRAM controller is deposited module for reading and writing with arm processor, DDR3SDRAM frame, DDR3SDRAM frame memory device is connected; DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the second data conversion module; Sequence generation module and arm processor, DDR3SDRAM frame are deposited module for reading and writing, the first data conversion module, the second data conversion module and are connected;
Described arm processor, be used for carrying out drawing algorithm computing, obtain the operational data of drawing, to multiport DDR3SDRAM controller, send write operation request, by multiport DDR3SDRAM controller, drawing operational data is write to the buffer module in DDR3SDRAM frame memory device;
Described multiport DDR3SDRAM controller, for arbitrating and prioritization processing the three kinds of operator schemes that write, read, empty that receive;
Described DDR3SDRAM frame is deposited module for reading and writing, for being sent and read and empty operation requests to the buffer module of DDR3SDRAM frame memory device by multiport DDR3SDRAM controller;
The first described data conversion module, for converting all-zero signal to the receivable data stream format of DDR3SDRAM module for reading and writing;
The second described data conversion module, converts the digital rgb vision signal that meets liquid crystal display driving sequential standard to for the data stream that DDR3SDRAM module for reading and writing is sent;
Described sequence generation module, for generation of arm processor, multiport DDR3SDRAM controller, the first data conversion module, the required all kinds of clock signals of the second data conversion module work;
Described DDR3SDRAM frame memory device, for carrying out the buffered of draw data, comprise the first buffer module, the second buffer module, the 3rd buffer module, the field sync signal that the operator scheme of described the first buffer module, the second buffer module, the 3rd buffer module is sent take sequence generation module replaces switching as the cycle.
2. a kind of pattern generator based on comprehensive programming device as claimed in claim 1, it is characterized in that, further, to be arm processor write drawing operational data by DDR3SDRAM controller to certain buffer module in DDR3SDRAM frame memory device to said write operator scheme.
3. a kind of pattern generator based on comprehensive programming device as claimed in claim 1, it is characterized in that, further, described read mode is that DDR3SDRAM frame is deposited module for reading and writing and read draw data by multiport DDR3SDRAM controller certain buffer module from DDR3SDRAM frame memory device.
4. a kind of pattern generator based on comprehensive programming device as claimed in claim 1, it is characterized in that, further, described in, emptying operator scheme and be DDR3SDRAM frame deposits module for reading and writing and to certain buffer module in DDR3SDRAM frame memory device, writes full remainder certificate by multiport DDR3SDRAM controller.
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| CN105573703A (en) * | 2015-12-20 | 2016-05-11 | 苏州长风航空电子有限公司 | Double-screen different-image graphic generating system |
| TWI665670B (en) * | 2016-12-20 | 2019-07-11 | 美商豪威科技股份有限公司 | Multiport memory architecture |
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