CN103681647B - Encapsulating structure and its manufacture method - Google Patents
Encapsulating structure and its manufacture method Download PDFInfo
- Publication number
- CN103681647B CN103681647B CN201210357070.3A CN201210357070A CN103681647B CN 103681647 B CN103681647 B CN 103681647B CN 201210357070 A CN201210357070 A CN 201210357070A CN 103681647 B CN103681647 B CN 103681647B
- Authority
- CN
- China
- Prior art keywords
- electronic component
- junction point
- conductive junction
- encapsulating structure
- exposed region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A kind of encapsulating structure and its manufacture method, the encapsulating structure include a substrate, multiple first electronic components, at least one second electronic component, one first coating and a line layer.The surface of substrate has one first element area and one second element area.Multiple first electronic components are arranged in the first element area of substrate, and at least one in first electronic component has one first conductive junction point.Second electronic component is arranged at the second element area of substrate.The encapsulating structure forms the first coating with recess using the difference in height of the electronic component on substrate, and the first coating simultaneously has one first exposed region with the first conductive junction point of exposure.Line layer covers at least part recess and the first conductive junction point of exposure.
Description
Technical field
The present invention relates to a kind of encapsulating structure and its manufacture method, and more particularly to, one kind can lift encapsulated space utilization
The encapsulating structure and its manufacture method of rate.
Background technology
Electronic product now has been common in the field of amusement, communication, power conversion, network, computer and consumer products.Electricity
Sub- product is also found in Military Application, aviation, automobile, industrial control unit (ICU) and office equipment.From the point of view of systematic point of view, now
Electronic product stress compact so that the distribution density of electronic component and circuit is too high, and user for system accelerate
Processing speed (processing speed) also increasingly increases with the demand reduced the size, except needing maintenance high-effect and stably
Quality, more necessary saving space is to reach compact purpose.
The efficiency of system is relevant with whole system framework, although the silicon perforation technology (Through of current wafer technique
Silicon Via, TSV) emphasize it is chip-stacked can effectively save space and line length, but the line length of reduction is limited,
Mostly millimicron or micron grade.When the development of electronic product increasingly tends to the form of microminiaturization, it may conform to electrically to go up efficiency steady
Fixed demand and with the encapsulating structure of smaller and relatively thin volume, is always the pursuit in design of electronic products.
The content of the invention
The main purpose of the embodiment of the present invention is to provide a kind of encapsulating structure and its manufacture method, and it is using on substrate
The difference in height of electronic component, forms the first coating with recess, and at least one on substrate will be moved on line layer
The top of electronic component, can reach microminiaturization and reduces the effect of cost.
The embodiment of the present invention provides a kind of encapsulating structure, including a substrate, multiple first electronic components, at least one second electricity
Subcomponent, one first coating and a line layer.There is one first element area and one second yuan on one surface of substrate
Part region.Multiple first electronic components are arranged in the first element area of substrate, in the multiple first electronic component extremely
It is one of few that there is at least one first conductive junction point.At least one second electronic component is arranged at the second element region of substrate
Domain.First coating covers first element area and the second element area, the first coating and with a recess and
At least one first exposed region.Recess is disposed on the upper of at least one second element area, and the first exposed region exposes
At least one first conductive junction point.Line layer covers at least part recess and at least one first conduction of the exposure connects
Point, and line layer is electrically connected at least one first conductive junction point.
Wherein, at least one first exposed region is perforation, and it is naked that the line layer covers described at least one first conformally
Reveal region, to be electrically connected at least one first conductive junction point by least one first exposed region.
Wherein, at least one first exposed region is perforates, at least one first exposed region described in line layer filling,
To be electrically connected at least one first conductive junction point by least one first exposed region.
Wherein, the side wall of the recess and the bottom surface of the recess are crossed to form angle, and the angle is between 90 degree to 135 degree.
Wherein, the side wall of the recess is stairstepping.
Wherein, there is at least one second conductive junction point, first coating also includes at least one in second element area
Second exposed region, at least one second conductive junction point described at least one second exposed region exposure, and the line layer is covered
At least one second conductive junction point of the exposure and it is electrically connected at least one second conductive junction point.
Wherein, first coating also includes at least one the 3rd exposed region, at least one the 3rd exposed region exposure
An at least connection pad on the substrate, and the line layer covers an at least connection pad for the exposure and is electrically connected to described at least one connects
Pad.
Wherein, the encapsulating structure also includes：
Third element region, is arranged on the recess, and the third element region has at least one the 3rd electronic component, described
At least one the 3rd electronic component is electrically connected at least one first conductive junction point by the line layer；And
Second coating, at least one the 3rd electronic component described in covering.
Wherein, at least one the 3rd electronic component is electrically connected at least one second conduction by the line layer and connect
Point.
The embodiment of the present invention separately provides a kind of manufacture method of encapsulating structure, comprises the following steps.First, multiple electricity are configured
Subcomponent is on a substrate, and at least one first electronic component in the multiple electronic component has one first conductive junction point.Connect
, form one first coating to coat the multiple electronic component, wherein the first coating has a recess, recess is located at institute
State at least one second electronic component in multiple electronic components.Then, at least one first is formed on the first coating naked
Reveal region, with least one first conductive junction point described in exposure.Finally, a line layer is formed on the first coating to cover at least
Part recess and at least one first conductive junction point of the exposure, and line layer is electrically connected at least one first conduction
Contact.
Wherein, the manufacture method, which is additionally included on first coating, forms at least one second exposed region, should with exposure
At least one second conductive junction point on substrate, and the line layer covers at least one second conductive junction point and the electric connection of the exposure
To at least one second conductive junction point.
Wherein, the manufacture method, which is additionally included on first coating, forms at least one the 3rd exposed region, should with exposure
An at least connection pad on substrate, and the line layer covers an at least connection pad for the exposure and is electrically connected to described at least one connects
Pad.
Wherein, the manufacture method also includes：
At least one the 3rd electronic component is configured on the recess, and at least one the 3rd electronic component is passed through the circuit
Layer is electrically connected at least one first conductive junction point；And
The second coating is formed, to coat at least one the 3rd electronic component and at least partly line layer.
Wherein, the manufacture method also includes：
At least one the 3rd electronic component is electrically connected at least one second conductive junction point by the line layer.
In summary, the embodiment of the present invention is proposed encapsulating structure and its manufacture method, pass through at least one on substrate
Line layer above electronic component, it is possible to provide electronic system in single encapsulating structure complete electronic component three-dimensional encapsulation, and
Line length can be shortened, to be effectively increased the efficiency of electronic system electrically, and the usable floor area of substrate surface can be reduced, with
Lift space availability ratio of encapsulating structure etc..
To enable the feature and technology contents that are further understood that the present invention, refer to below in connection with the present invention specifically
Bright and accompanying drawing, but these explanations are only used for illustrating the present invention with institute's accompanying drawings, rather than any is made to the interest field of the present invention
Limitation.
Brief description of the drawings
Figure 1A to Figure 1B is the schematic top plan view of the encapsulating structure of one embodiment of the invention in the fabrication process.
Fig. 1 C show diagrammatic cross-section of the encapsulating structure along 1C-1C lines in Figure 1B.
Fig. 1 D show diagrammatic cross-section of the encapsulating structure along 1D-1D lines in Figure 1B
Fig. 2A to Fig. 2 B is the schematic top plan view of the encapsulating structure of another embodiment of the present invention in the fabrication process.
Fig. 3 is the diagrammatic cross-section of the encapsulating structure of another embodiment of the present invention.
Fig. 4 is the diagrammatic cross-section of the encapsulating structure of another embodiment of the present invention.
Fig. 5 is the diagrammatic cross-section of the encapsulating structure of another embodiment of the present invention.
Fig. 6 is the flow chart of the manufacture method of the encapsulating structure of another embodiment of the present invention.
Wherein, description of reference numerals is as follows：
100th, 100 ', 200,300,400 encapsulating structure
101 substrate strips
102 lines of cut
110 substrates
111 first element areas
112 second element areas
113 connection pads
115 loading ends
121 first electronic components
122 second electronic components
123rd, 123 ', 123 " the 3rd electronic component
125 first conductive junction points
127 second conductive junction points
130 first coatings
131 first exposed regions
132 second exposed regions
133 the 3rd exposed regions
135 recesses
137 bottom surfaces
139 side walls
140 line layers
150 third element regions
160 second coatings
G angles
S surfaces
S1 ~ S4 steps
Embodiment
(embodiment of encapsulating structure and its manufacture method)
Also referring to Figure 1A to Fig. 1 D, Figure 1A to Figure 1B is that the encapsulating structure 100 of one embodiment of the invention was being manufactured
Schematic top plan view in journey；Fig. 1 C show diagrammatic cross-section of the encapsulating structure 100 along 1C-1C lines in Figure 1B；Fig. 1 D display figures
Diagrammatic cross-section of the encapsulating structure 100 along 1D-1D lines in 1B.Encapsulating structure 100 includes substrate 110, multiple electronic components (bag
Include the first electronic component 121 and the second electronic component 122), the first coating 130 and line layer 140.As shown in Figure 1A, base
Plate 110 can be any support electronic component (including the first electronic component 121 and second electronic component 122) and can provide electronics
The carrier of element (including the first electronic component 121 and second electronic component 122) electricity connection function, such as printed circuit board (PCB)
(Printed Wiring Board, PWB) or hard circuit board (flex-rigid wiring board).Substrate 110 is included extremely
A few connection pad 113 and top line layer (not illustrating).Connection pad 113 is made by conductive material, to be electrically connected to conducting wire
The plane (not illustrating) of (not illustrating) or other functions.In the present embodiment, at least one described connection pad 113 is ground mat,
And ground plane (not illustrating) is electrically connected to, wherein, connection pad 113 is all located on substrate 110 or is embedded to line layer (not illustrating)
Circuit substrate 110.The surface S of substrate 110 include loading end 115, and loading end 115 have one first element area 111 and
One second element area 112.
First, multiple electronic components (including the first electronic component 121 and second electronic component 122) are configured in substrate 110
On.In the present embodiment, the first element area 111 is configured with multiple first electronic components 121, and the first electronic component 121 is for example
For the passive device of 0402 specification, and at least one first electronic component 121 has first conductive junction point 125.First leads
Electric contact 125 is made by conductive material, to provide electric connection.In the present embodiment, the first conductive junction point 125 is the first electricity
Part welding end (terminal) in subcomponent 121.The quantity of first conductive junction point 125 can be designed according to actual demand,
Embodiments of the invention are not intended to limit.In the encapsulating structure 100 of the present embodiment, the quantity of the first conductive junction point 125 be it is multiple,
But embodiments of the invention are not intended to limit.
Second element area 112 is configured with least one second electronic component 122 and connect with least one second conduction
Point 127, the second electronic component 122 is, for example, control chip.As shown in Figure 1A, the second electronic component 122 can be one, but this
The embodiment of invention is not intended to limit, and the second electronic component 122 in the second element area 112 can be one or more.It is described
At least one second conductive junction point 127 is equally made by conductive material, to provide electric connection, and the second conductive junction point 127
Structure be, for example, metal gasket, tin ball or elargol on substrate 110 etc..The structure of second conductive junction point 127 and quantity are foundations
Actual demand and design, embodiments of the invention are not intended to limit, in other embodiments, and the quantity of the second conductive junction point 127 can
To be only one.It is noted that the species and specification of electronic component 121,122 are designed, this hair according to actual demand
Bright embodiment is not intended to limit.
Then, as shown in Figure 1B, the first coating 130 is formed with coated electric components 121,122, wherein the first coating
130 have recess 135, and recess 135 is located at least one second electronic component 122.First coating 130 is with molding material
Expect (molding material) to produced by the first element area 111 and the second element area 112 one sealing adhesive process of progress
Insulating barrier, with coated electric components 121,122 and substrate 110.Sealing adhesive process is, for example, drape forming technique (over-
Molding process), and the material of the first coating 130 is, for example, epoxy resin or silica gel.Specifically, due to setting
It is less than in the vertical height of at least one second electronic component 122 on the second element area 112 to loading end 115 and is arranged at the
The first electronic component 121 on one element area 111 is to the vertical height of loading end 115, and the first coating 130 is with molding
Material covers the electronic component 121,122 on the first element area 111 and the second element area 112 conformally.Thereby, with formation
The first coating 130 with recess 135, and recess 135 is disposed on the second element area 112, this means, recess 135
It is disposed at least one described second electronic component 122.
Fig. 1 C are referred to, in this specific embodiment, recess 135 has a bottom surface for being roughly parallel to loading end 115
137 and four side walls 139 for being approximately perpendicular to bottom surface 137.The area and shape of bottom surface 137, not less than described at least one
The area and shape of upright projection of individual second electronic component 122 in loading end 115.In addition, in other embodiments, having
First coating 130 of recess 135 can also be used molding mould and be formed by metaideophone shaping or pressure injection technique, or utilize essence
Close milling cutter simultaneously removes the first coating of part 130 to form recess 135 by cutting technique, and embodiments of the invention are not added with herein
To limit.
Please refer to Figure 1B and Fig. 1 C, then, at least one first conductive junction point of correspondence on the first coating 130
125 position forms at least one first exposed region 131, with least one described first conductive junction point 125 of exposure, and
The position of at least one the second conductive junction point 127 of correspondence forms at least one second exposed region 132 on first coating 130,
With at least one described second conductive junction point 127 of exposure.In the present embodiment, the first exposed region 131 and the second exposed region
132 be all perforation, and the method for forming the first exposed region 131 and the second exposed region 132 can all use laser drilling process
(laser drilling process).Specifically, laser drill head (not illustrating) can be respectively aligned to the first conductive junction point 125
And second conductive junction point 127 position, and to the first coating 130 carry out drilling cutting, to remove the coating of part first
130, to form the first exposed region 131 and the second exposed region 132 that minimum diameter is for example all 80 microns.
Thereby, formed at least one first exposed region 131 on the first coating 130 can expose it is described at least one
First conductive junction point 125, and formed at least one second exposed region 132 on the first coating 130 can expose it is described extremely
Few second conductive junction point 127.In addition, the methods that can also use the first coating 130 of other removals, such as electric paste etching,
Chemical etching or machine drilling etc., to form at least one the first exposed region 131 and at least one second exposed region 132,
And at least one the first conductive junction point 125 and at least one second conductive junction point 127 are exposed respectively.It is noted that first
The size and shape and quantity of exposed region 131 and the second exposed region 132 are designed, reality of the invention according to actual demand
Example is applied to be not intended to limit.
For example, in other embodiments, at least one first exposed region 131 can be opening.Further say, extremely
The structure of few first conductive junction point 125 can be part welding end and the elargol or scolding tin that are positioned in part welding end
（solder）, and the flush that the top surface of at least one first conductive junction point 125 can be with the first coating 130.Furthermore,
When carrying out sealing adhesive process to the first element area 111 and the second element area 112 with molding material, can by molding mould so that
Molding material does not cover the top surface of at least one first conductive junction point 125.Therefore, can direct shape after completion sealing adhesive process
Into the first coating 130 with least one the first exposed region 131, that is to say, that, it is not necessary to accurate milling cutter cutting is bored
Hole technique forms the first exposed region 131 of the first coating 130.
In addition, please refer to Figure 1B and Fig. 1 D, the first coating 130 of encapsulating structure 100 more may include at least one
3rd exposed region 133, and at least one connection pad 113 at least one described the 3rd exposed region 133 exposure substrate 110.
Specifically, more at least one the 3rd exposed area can be formed in the position of at least one connection pad 113 of correspondence on the first coating 130
Domain 133, to expose at least one described connection pad 113 on substrate 110.In the present embodiment, the 3rd exposed region 133 can be to wear
Hole, but shape size and quantity is not also any limitation as, and the minimum diameter of the 3rd exposed region 133 is, for example, 80 microns, and is formed
The mode of 3rd exposed region 133 is roughly the same with the mode for forming the first exposed region 131, Gu it is no longer repeated.
It please refer to Figure 1B, Fig. 1 C and Fig. 1 D in the lump again.Finally, line layer 140 is formed on the first coating 130, to cover
Cover recess 135, exposure at least one first conductive junction point 125, exposure at least one second conductive junction point 127 and
At least one exposed connection pad 113, and be electrically connected at least one first conductive junction point 125, at least one second conduction and connect
Point 127 and at least one connection pad 113, and complete encapsulating structure 100.In this specific embodiment, conductive material can be first deposited
Recess 135, at least one first exposed region 131, at least one second exposed region 132 and at least one are covered with conformal
Individual 3rd exposed region 133.Specifically, conductive material covers bottom surface 137 and the side wall 139 of recess 135 conformally, and suitable
The madial wall and at least one first conductive junction point 125 of at least one the first exposed region 131 are covered or fill to shape, with electricity
Property be connected at least one described first conductive junction point 125.
Similarly, conductive material covers or filled conformally the madial wall and extremely of at least one the second exposed region 132
Few second conductive junction point 127, and conformal the madial wall for covering at least one the 3rd exposed region 133 and at least one
Connection pad 113, to be electrically connected at least one described second conductive junction point 127 and at least one described connection pad 113.Then,
The conductive material that patterned features are deposited in the way of laser ablation, to form line layer 140, but forms the mode of patterning
It is not limited.Thereby, line layer 140 can be electrically connected to by least one the first exposed region 131 at least one
One conductive junction point 125, at least one second conductive junction point 127 is electrically connected to by least one second exposed region 132, and
And at least one connection pad 113 is electrically connected to by least one the 3rd exposed region 133.
In the present embodiment, the mode of deposition conductive material is, for example, spraying plating (spray coating), plating
(electroplating), electroless plating (electrolessplating), evaporation or sputter (sputtering) etc..Line layer
140 preferred thickness be between 200 microns to 1000 microns, and line layer 140 can by such as metal material, alloy material, lead
The combined deposition multilayer conductive material of electric high polymer material or above-mentioned material is constituted.In addition, the pattern of line layer 140 is affiliated
Technical field tool usually intellectual can be according to actual service condition demand footpath row design, therefore embodiments of the invention are herein
It is not any limitation as.In other embodiments, the mode for forming line layer 140 can be complete by the patterning shielding of offer one (mask)
Into that is, setting, which is shielded from the first coating, carries out depositing conductive material technique again.
In the present embodiment, encapsulating structure 100 can further include third element region 150, and third element region 150 is arranged at
On recess 135.Third element region 150 can have (or configuration) at least one the 3rd electronic component 123.When the electricity of configuration the 3rd
Subcomponent 123 when on the bottom surface 137 of recess 135, the 3rd electronic component 123 can be electrically connected to by line layer 140 to
Few first conductive junction point 125, at least one second conductive junction point 127 and at least one connection pad 113, are thereby electrically connected to
At least one described first electronic component 121, at least one described second electronic component 122 and at least one described connection pad 113.
As shown in Figure 1B, third element region 150 is arranged at the bottom surface 137 of recess 135.It is noted that third element region 150
Size and shape be according to actual demand and design, embodiments of the invention are not intended to limit, in other embodiments, ternary
Part region 150 may also set up in portion bottom surface 137 and/or the partial sidewall 139 of recess 135 for recess 135.
Specifically, as shown in Figure 1 C, line layer 140 is bottom surface 137 and the side wall 139 for covering recess 135 conformally, and
By at least one first exposed region 131 be electrically connected at least one first conductive junction point 125, by least one second
Exposed region 132 is electrically connected at least one second conductive junction point 127, and passes through at least one electricity of the 3rd exposed region 133
Property is connected at least one connection pad 113.Therefore, at least one the 3rd electronic component 123 being configured on recess 135 can be by line
Road floor 140 be electrically connected at least one first conductive junction point 125, at least one second conductive junction point 127 and at least one connect
Pad 113.
It is noted that in the present embodiment, the 3rd electronic component 123 is, for example, the passive device of 0201 specification, separately
Outside, the species of the 3rd electronic component 123 with specification is designed according to actual demand, and the configuration side of the 3rd electronic component 123
Formula and quantity is according to actual demand and coordinates line layer 140 and design, and embodiments of the invention are not intended to limit.
(another embodiment of encapsulating structure and its manufacture method)
Fig. 2A to Fig. 2 B is refer to, Fig. 2A to Fig. 2 B is the encapsulating structure 100 ' of another embodiment of the present invention in manufacturing process
In schematic top plan view.Encapsulating structure 100 of the encapsulating structure 100 ' and its manufacture method of the present embodiment all with previous embodiment
And its it is substantially similar both manufacture method, and the following different places only between the present embodiment and previous embodiment are carried out in detail
Describe in detail bright.
As shown in Figure 2 A, there is provided circuit substrate bar 101 first.Circuit substrate bar 101 has multiple substrates 110, and substrate
110 be a plurality of line of cut 102 on circuit substrate bar 111 define Lai.Similarly, the loading end of each substrate 110
115 all have one first element area 111 and one second element area 112.Therefore, multiple electronic components can be configured simultaneously
(including the first electronic component 121 and second electronic component 122) is on each substrate 110.
Then, as shown in Figure 2 B, the first coating 130 is formed to coat the multiple electronic component 121,122, and in the
One coating 130 forms multiple recesses 135, and each recess 135 is located at least one second electronic component of each substrate 110
122 it is upper.In the present embodiment, sealing can be carried out in the lump to multiple substrates 110 with molding material (molding material)
Technique, with conformal each substrate 110 of electronic component 121,122 and part coated on each substrate 110.In Fig. 2A to Fig. 2 B
It is in process detail as described in Figure 1A to Fig. 1 D, and the art tool usually intellectual can should easily deduce embodiments thereof,
Therefore be not added with repeating herein.
Finally, along the cutting substrate 110 of line of cut 102, to complete multiple encapsulating structures 100 '.Specifically, knife can be passed through
Have cutting technique (blade sawing process) or laser cutting parameter, cut by the bottom surface of substrate 110, to divide
From substrate 110 and the first coating 130 of the loading end 115 for being covered in substrate 110, and complete multiple encapsulating structures 100 '.
(another embodiment of encapsulating structure and its manufacture method)
Fig. 3 is refer to, Fig. 3 is the diagrammatic cross-section of the encapsulating structure 200 of another embodiment of the present invention.The envelope of the present embodiment
Assembling structure 200 and its manufacture method are all substantially similar with both encapsulating structures 100 and its manufacture method of previous embodiment, and with
Under be described in detail only for the different places between the present embodiment and previous embodiment.
In the present embodiment, encapsulating structure 200 can further include third element region 150, and third element region 150 is arranged at
On recess 135.As shown in figure 3, specifically, configuring at least one the 3rd electronic component 123 ' or 123 " in the bottom of recess 135
On face 137, thereby, the 3rd electronic component 123 ', 123 " is electrically connected at least one first conductive junction point by line layer 140
125 or at least one (not shown) of the second conductive junction point 127 is also electrically connected to depending on actual demand.3rd electronic component 123 ' is
0402 or the passive device of more small dimension, and the 3rd electronic component 123 " is control chip.Therefore on third element region 150
The vertical height of 3rd electronic component 123 ' to loading end 115 is more than the first electronic component on the first electronic component region 111
121 to loading end 115 vertical height, and the 3rd electronic component 123 " on third element region 150 hanging down to loading end 115
Straight height is less than the first electronic component 121 on the first electronic component region 111 to the vertical height of loading end 115, but the 3rd
Electronic component 123 ' and 123 " part specifications and shape are designed according to actual demand, and the present invention is not any limitation as.
Encapsulating structure 200 further includes the second coating 160, to cover third element region 150 and the 3rd electronics thereon
Element.As shown in figure 3, specifically, one second coating 160 can be formed to coat the 3rd electronic component 123 ', 123 ", and wrap
Cover exposed line layer 140 and at least one first exposed region 131.What is more, the second coating 160 can also coat naked
The line layer 140 and at least one second exposed region exposed outside, or also coat depending on actual demand exposed line layer 140
And at least one the 3rd exposed region (not shown).
Second coating 160 is to carry out the insulation produced by a sealing adhesive process to third element region 150 with molding material
Layer, it is at least local to coat the 3rd electronic component 123 ', 123 " and recess 135, what is more, will also coat it is exposed extremely
Small part line layer 140.In this specific embodiment, the second coating 160 is covered conformally on third element region 150
3rd electronic component 123 ', 123 ", recess 135 is at least local and exposed at least part line layer 140.In Fig. 3
Remaining process detail is as described in Figure 1A to Fig. 1 D, and the art tool usually intellectual can should easily deduce embodiments thereof,
It is not added with repeating herein.
(another embodiment of encapsulating structure and its manufacture method)
Fig. 4 is refer to, Fig. 4 is the diagrammatic cross-section of the encapsulating structure 300 of another embodiment of the present invention.The envelope of the present embodiment
Assembling structure 300 and its manufacture method are all substantially similar with both encapsulating structures 100 and its manufacture method of previous embodiment, and with
Under be described in detail only for the difference between the present embodiment and previous embodiment.As shown in figure 4, the present embodiment recess
135 side wall 139 is crossed to form an angle G with bottom surface 137, and angle G is preferably between 90 degree to 135 degree.In the first coating
When forming line layer 140 on 130, conductive material is side wall 139 and the bottom surface 137 for covering recess 135 conformally, and angle G
It is to be designed according to actual demand, to lift the yield and elasticity of deposition conductive material technique, embodiments of the invention are not limited
System.Remaining process detail in Fig. 4 is as described in Figure 1A to Fig. 1 D, and the art tool usually intellectual can should easily deduce it
Embodiment, is not added with repeating herein.
(another embodiment of encapsulating structure and its manufacture method)
Fig. 5 is refer to, Fig. 5 is the diagrammatic cross-section of the encapsulating structure 400 of another embodiment of the present invention.The envelope of the present embodiment
Assembling structure 400 and its manufacture method are all substantially similar with both encapsulating structures 100 and its manufacture method of previous embodiment, and with
Under be described in detail only for the difference between the present embodiment and previous embodiment.As shown in figure 5, the present embodiment recess
135 side wall 139 is stairstepping.When forming line layer 140 on the first coating 130, conductive material is to cover conformally
The side wall 139 of recess 135 and bottom surface 137, and the shape of side wall 139 is designed according to actual demand, is led with lifting deposition
The yield of electric material technique is not intended to limit with elasticity, embodiments of the invention.Remaining process detail such as Figure 1A to Fig. 1 D in Fig. 5
Described, the art tool usually intellectual can should easily deduce embodiments thereof, be not added with repeating herein.
(embodiment of the manufacture method of encapsulating structure)
Above-described embodiment can summarize the manufacture method of encapsulating structure of the present invention, refer to Fig. 6 flow chart.First, match somebody with somebody
Multiple electronic components are put on substrate, there is at least one first electronic component in the multiple electronic component the first conduction to connect
Point (step S1)；The first coating is formed to coat the multiple electronic component, wherein the first coating has recess, recess position
On at least one second electronic component in the multiple electronic component (step S2)；Formed at least on the first coating
One the first exposed region, with least one first conductive junction point (step S3) of exposure；Finally, line is formed on the first coating
Road floor, to cover at least one first conductive junction point of at least part recess and the exposure, and be electrically connected to it is described extremely
Few first conductive junction point (step S4).
According to different product, above-mentioned flow more may include to form at least one second exposed region on the first coating,
To expose at least one second conductive junction point on substrate, and line layer covers at least one second conductive junction point of the exposure
And it is electrically connected at least one described second conductive junction point.Furthermore, above-mentioned flow or more may include the shape on the first coating
Into at least one the 3rd exposed region, to expose at least one connection pad on substrate, and line layer covers the exposure at least
One connection pad and it is electrically connected at least one described connection pad.
In addition, above-mentioned flow formed line layer the step of after, more may include configure at least one the 3rd electronic component in
On recess, and at least one the 3rd electronic component is set to be electrically connected at least one first conductive junction point and at least by line layer
One the second conductive junction point；Next, forming the second coating to coat at least one the 3rd electronic component and at least part
Line layer and at least one first exposed region.What is more, the second coating can also coat exposed line layer and extremely
Few second exposed region, or also coat depending on actual demand exposed line layer and at least one the 3rd exposed region.
In summary, the embodiment of the present invention provides a kind of encapsulating structure and its manufacture method, utilizes the electronics member on substrate
The difference in height of part, first coating of the formation with recess, and the electronic component that will be moved on line layer on base plate carrying face
Top, line layer by first, second and third exposed region of coating be electrically connected to electronic component on substrate and
Connection pad.The encapsulating structure and its manufacture method provided by above-described embodiment can shorten line length, and the length that circuit shortens
Up to millimeter grade, the efficiency of electronic system electrically is effectively increased.
Pass through the line layer above the electronic component on substrate, it is possible to provide electronic system is in completion electricity in single encapsulating structure
The three-dimensional encapsulation of subcomponent so that the design for the line layer being arranged on base plate carrying face is more elastic, can reduce base plate carrying
Line layer area and density needed on face, to reduce the usable floor area in base plate carrying face, lift the space utilization of encapsulating structure
Rate.Furthermore, in encapsulating structure provided in an embodiment of the present invention and its manufacture method, can be dropped by the recess above electronic component
The configuration factor (Form Factor) of low encapsulating structure, contributes to the product design of miniaturization, to increase the bullet of product design
Property, reduce product material and processing cost.
Embodiments of the invention are the foregoing is only, it is not limited to the scope of patent protection of the present invention.It is any ripe
Alike those skilled in the art is practised, is not being departed from spirit and scope of the invention, the change made and the equivalence replacement of retouching are still this hair
In bright scope of patent protection.
Claims (16)
1. a kind of encapsulating structure, it is characterised in that including：
Substrate, the surface of the substrate includes loading end, and the loading end has the first element area and the second element area；
At least one first electronic component, is arranged in first element area of the substrate, at least one first electronic component
In at least one have the first conductive junction point；
At least one second electronic component, is arranged at second element area of the substrate；
First coating, covers at least one first electronic component in first element area and covers second element area
Interior at least one second electronic component, first coating has recess and at least one first exposed region, and the recess is set
On second element area, at least one first conductive junction point described at least one first exposed region exposure；And
Line layer, the covering at least partly recess and at least one first conductive junction point of the exposure, and be electrically connected to described
At least one first conductive junction point；
Wherein, the vertical height of the second electronic component being arranged on second element area to the loading end, which is less than, is arranged at this
The first electronic component on first element area to loading end vertical height, first coating be with molding material conformally
Cover the first electronic component in first element area and the second electronic component in second element area, thus this
The recess is formed on two element region.
2. encapsulating structure as claimed in claim 1, it is characterised in that at least one first exposed region is perforation, the line
Road floor covers at least one first exposed region conformally, to be electrically connected to institute by least one first exposed region
State at least one first conductive junction point.
3. encapsulating structure as claimed in claim 1, it is characterised in that at least one first exposed region is perforation, the line
Road floor filling at least one first exposed region, with described in being electrically connected to by least one first exposed region at least
One first conductive junction point.
4. encapsulating structure as claimed in claim 1, it is characterised in that the bottom surface of the side wall and the recess of the recess is crossed to form
Angle, the angle is between 90 degree to 135 degree.
5. encapsulating structure as claimed in claim 1, it is characterised in that the side wall of the recess is stairstepping.
6. encapsulating structure as claimed in claim 1, it is characterised in that there is at least one second conduction in second element area
Contact, first coating also includes at least one second exposed region, described at least one second exposed region exposure at least
One second conductive junction point, and the line layer covers at least one second conductive junction point of the exposure and is electrically connected to described at least one
Second conductive junction point.
7. encapsulating structure as claimed in claim 6, it is characterised in that first coating also includes at least one the 3rd exposed area
Domain, at least one the 3rd exposed region exposes at least connection pad on the substrate, and the line layer covers an at least connection pad
And it is electrically connected to an at least connection pad.
8. encapsulating structure as claimed in claim 6, it is characterised in that the encapsulating structure also includes：
Third element region, is arranged on the recess, the third element region have at least one the 3rd electronic component, it is described at least
One the 3rd electronic component is electrically connected at least one first conductive junction point by the line layer；And
Second coating, at least one the 3rd electronic component described in covering.
9. encapsulating structure as claimed in claim 8, it is characterised in that at least one the 3rd electronic component passes through the line layer
It is electrically connected at least one second conductive junction point.
10. a kind of manufacture method of encapsulating structure, it is characterised in that including：
Multiple electronic components are configured on the loading end on the surface of substrate, the loading end has the first element area and second yuan
At least one first electronic component in part region, the multiple electronic component has the first conductive junction point, the first electronics member
Part is arranged on first element area；
The first coating is formed, to coat the multiple electronic component, and in first coating formation recess, the recess is located at
On at least one second electronic component in the multiple electronic component, second electronic component is arranged at second element region
On domain；
At least one first exposed region is formed on first coating, with least one first conductive junction point described in exposure；And
Line layer is formed on first coating, it is conductive with cover at least partly recess and the exposure at least one first
Contact, and it is electrically connected at least one first conductive junction point；
Wherein, the vertical height of the second electronic component being arranged on second element area to the loading end, which is less than, is arranged at this
The first electronic component on first element area to loading end vertical height, first coating be with molding material conformally
Cover the first electronic component in first element area and the second electronic component in second element area, thus this
The recess is formed on two element region.
11. the manufacture method of encapsulating structure as claimed in claim 10, it is characterised in that at least one first exposed region
For perforation, the line layer covers at least one first exposed region conformally, to pass through at least one first exposed region
It is electrically connected at least one first conductive junction point.
12. the manufacture method of encapsulating structure as claimed in claim 10, it is characterised in that at least one first exposed region
For perforation, at least one first exposed region described in line layer filling, electrically to be connected by least one first exposed region
It is connected at least one first conductive junction point.
13. the manufacture method of encapsulating structure as claimed in claim 10, it is characterised in that the manufacture method be additionally included in this
At least one second exposed region is formed on one coating, with least one second conductive junction point on the exposure substrate, and the circuit
Layer covers at least one second conductive junction point of the exposure and is electrically connected at least one second conductive junction point.
14. the manufacture method of encapsulating structure as claimed in claim 13, it is characterised in that the manufacture method be additionally included in this
At least one the 3rd exposed region is formed on one coating, to expose at least connection pad on the substrate, and line layer covering should
An exposed at least connection pad and it is electrically connected to an at least connection pad.
15. the manufacture method of encapsulating structure as claimed in claim 13, it is characterised in that the manufacture method also includes：
At least one the 3rd electronic component is configured on the recess, and at least one the 3rd electronic component is passed through line layer electricity
Property be connected at least one first conductive junction point；And
The second coating is formed, to coat at least one the 3rd electronic component and at least partly line layer.
16. the manufacture method of encapsulating structure as claimed in claim 15, it is characterised in that the manufacture method also includes：
At least one the 3rd electronic component is electrically connected at least one second conductive junction point by the line layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210357070.3A CN103681647B (en) | 2012-09-24 | 2012-09-24 | Encapsulating structure and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210357070.3A CN103681647B (en) | 2012-09-24 | 2012-09-24 | Encapsulating structure and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103681647A CN103681647A (en) | 2014-03-26 |
| CN103681647B true CN103681647B (en) | 2017-07-21 |
Family
ID=50318698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210357070.3A Active CN103681647B (en) | 2012-09-24 | 2012-09-24 | Encapsulating structure and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103681647B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499590A (en) * | 2002-11-05 | 2004-05-26 | �¹������ҵ��ʽ���� | Semiconductor device and its mfg. method |
| CN102282661A (en) * | 2009-01-27 | 2011-12-14 | 松下电工株式会社 | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090008766A1 (en) * | 2007-07-02 | 2009-01-08 | Chien-Wei Chang | High-Density Fine Line Structure And Method Of Manufacturing The Same |
| KR101194842B1 (en) * | 2007-09-06 | 2012-10-25 | 삼성전자주식회사 | An semiconductor package embedded Print circuit board |
| US8187920B2 (en) * | 2009-02-20 | 2012-05-29 | Texas Instruments Incorporated | Integrated circuit micro-module |
-
2012
- 2012-09-24 CN CN201210357070.3A patent/CN103681647B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499590A (en) * | 2002-11-05 | 2004-05-26 | �¹������ҵ��ʽ���� | Semiconductor device and its mfg. method |
| CN102282661A (en) * | 2009-01-27 | 2011-12-14 | 松下电工株式会社 | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103681647A (en) | 2014-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9899298B2 (en) | Microelectronic packages having mold-embedded traces and methods for the production thereof | |
| US10440819B2 (en) | Fan-out wafer level packages having preformed embedded ground plane connections | |
| CN104882416B (en) | Semiconductor package part with stacked package ability and preparation method thereof | |
| US9331029B2 (en) | Microelectronic packages having mold-embedded traces and methods for the production thereof | |
| CN102473697B (en) | The electrical interconnection of the stacked die of tortuous configuration | |
| CN102696105B (en) | Chip package with a chip embedded in a wiring body | |
| TWI664696B (en) | Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof | |
| US8822844B1 (en) | Shielding and potting for electrical circuits | |
| US20120020039A1 (en) | Surface-mounted shielded multicomponent assembly | |
| US20040140549A1 (en) | Wiring structure and its manufacturing method | |
| CN101228625B (en) | Semiconductor package with plated connection | |
| KR20090117237A (en) | Electronic components embedded pcb and the method for manufacturing thereof | |
| CN105655316A (en) | Chip-use polymer frame being connected with capacitor in series and having at least one hole | |
| CN103596386B (en) | The method manufacturing the composite circuit board with built-in stopper | |
| CN103187327A (en) | Method for collective production of 3d electronic modules comprising only valid pcbs | |
| CN105280601A (en) | Packaging structure and packaging substrate structure | |
| CN105336629B (en) | The manufacturing method and Electronic Packaging module of Electronic Packaging module | |
| CN101853840B (en) | Structure of embedded line substrate and manufacturing method thereof | |
| JP2021141310A (en) | Substrate structure including embedded semiconductor device, and manufacturing method for the same | |
| CN104396008A (en) | Semiconductor package substrate, package system using the same and method for manufacturing thereof | |
| CN203327375U (en) | Package substrate based on 3D printing | |
| CN104576616B (en) | Module integrated circuit packaging structure and preparation method thereof | |
| CN103681647B (en) | Encapsulating structure and its manufacture method | |
| TWI483377B (en) | Package structure and manufacturing method thereof | |
| CN117480601A (en) | Packaging structure, preparation method thereof, packaging module and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |