CN103681647A - Packaging structure and manufacturing method thereof - Google Patents
Packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN103681647A CN103681647A CN201210357070.3A CN201210357070A CN103681647A CN 103681647 A CN103681647 A CN 103681647A CN 201210357070 A CN201210357070 A CN 201210357070A CN 103681647 A CN103681647 A CN 103681647A
- Authority
- CN
- China
- Prior art keywords
- junction point
- electronic component
- conductive junction
- exposed region
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
Disclosed are a packaging structure and a manufacturing method thereof. The packaging structure includes a substrate, a plurality of first electronic elements, at least one second electronic element, a first cover layer and a circuit layer. The surface of the substrate is provided with a first element area and a second element area. The plurality of first electronic elements are arranged in the first element area of the substrate. At least one of the first electronic elements is provided with a first conductive connection point. The second conductive element is arranged in the second element area. The first cover layer provided with a recess part is formed in the packaging structure through use of the height difference of the electronic elements on the substrate. The first cover layer is provided with a first exposed area so as to expose the first conductive connection point. The circuit layer covers at least part of the recess part and the exposed first conductive connection point.
Description
Technical field
The present invention relates to a kind of encapsulating structure and manufacture method thereof, and particularly relate to a kind of encapsulating structure and manufacture method thereof that promotes encapsulated space utilance.
Background technology
Electronic product has now been common in the field of amusement, communication, power transfer, network, computer and consumer products.Electronic product is also found in Military Application, aviation, automobile, industrial control unit (ICU) and office equipment.From systematic point of view, electronic product is now stressed compact, make the distribution density of electronic component and circuit too high, and user also increases day by day for system speed up processing (processing speed) and the demand of minification, except maintaining high-effect and stable quality, more necessary saving space is to reach compact object.
The usefulness of system is relevant with whole system framework, although silicon puncturing technique (the Through Silicon Via of current wafer technique, TSV) emphasize chip-stackedly can effectively save space and line length, but the line length of reduction is limited, mostly is millimicron or micron grade.When the development of electronic product day by day tends to the form of microminiaturization, can meet the demand that electrically upper usefulness is stable and there is the encapsulating structure of less and thinner volume, be the pursuit in design of electronic products always.
Summary of the invention
The main purpose of the embodiment of the present invention is to provide a kind of encapsulating structure and manufacture method thereof, it utilizes the difference in height of the electronic component on substrate, formation has the first cover layer of recess, and will on line layer, move to the top of at least one electronic component on substrate, can reach microminiaturization and the effect reducing costs.
The embodiment of the present invention provides a kind of encapsulating structure, comprises a substrate, a plurality of the first electronic component, at least one the second electronic component, one first cover layer and a line layer.On one surface of substrate, there is one first element area and one second element area.A plurality of the first electronic components are arranged in the first element area of substrate, in described a plurality of the first electronic components at least one of them has at least one the first conductive junction point.Described at least one the second electronic component is arranged at the second element area of substrate.The first cover layer covers described the first element area and the second element area, and the first cover layer also has a recess and at least one the first exposed region.Recess is be arranged at described at least one the second element area upper, and the first exposed region exposes described at least one the first conductive junction point.Line layer is covered at least one first conductive junction point of small part recess and described exposure, and line layer is to be electrically connected to described at least one the first conductive junction point.
Wherein, described at least one the first exposed region for perforation, this line layer along shape cover described at least one the first exposed region, to be electrically connected to described at least one the first conductive junction point by described at least one the first exposed region.
Wherein, described at least one the first exposed region is perforation, and described at least one the first exposed region of this line layer filling, to be electrically connected to described at least one the first conductive junction point by described at least one the first exposed region.
Wherein, formation angle is intersected in the sidewall of this recess and the bottom surface of this recess, and this angle is between 90 degree to 135 degree.
Wherein, the sidewall of this recess is stairstepping.
Wherein, in this second element area, there is at least one the second conductive junction point, this first cover layer also comprises at least one the second exposed region, described at least one the second exposed region exposes described at least one the second conductive junction point, and this line layer covers at least one second conductive junction point of this exposure and be electrically connected to described at least one the second conductive junction point.
Wherein, this first cover layer also comprises at least one the 3rd exposed region, and described at least one the 3rd exposed region exposes at least one connection pad on this substrate, and this line layer covers at least one connection pad of this exposure and be electrically connected to described at least one connection pad.
Wherein, described encapsulating structure also comprises:
Three element region, is arranged on this recess, and this three element region has at least one the 3rd electronic component, and described at least one the 3rd electronic component is electrically connected to described at least one the first conductive junction point by this line layer; And
The second cover layer, covers described at least one the 3rd electronic component.
Wherein, described at least one the 3rd electronic component is electrically connected to described at least one the second conductive junction point by this line layer.
The embodiment of the present invention separately provides a kind of manufacture method of encapsulating structure, comprises the following steps.First, configure a plurality of electronic components on a substrate, at least one the first electronic component in described a plurality of electronic components has one first conductive junction point.Then, form one first cover layer to be coated described a plurality of electronic component, wherein the first cover layer has a recess, and recess is arranged at least one second electronic component of described a plurality of electronic components.Then, on the first cover layer, form at least one the first exposed region, to expose described at least one the first conductive junction point.Finally, on the first cover layer, form a line layer to be covered at least one first conductive junction point of small part recess and described exposure, and line layer is electrically connected to described at least one the first conductive junction point.
Wherein, this manufacture method is also included in and on this first cover layer, forms at least one the second exposed region, to expose at least one the second conductive junction point on this substrate, and this line layer covers at least one second conductive junction point of this exposure and be electrically connected to described at least one the second conductive junction point.
Wherein, this manufacture method is also included on this first cover layer and forms at least one the 3rd exposed region, and to expose at least one connection pad on this substrate, and this line layer covers at least one connection pad of this exposure and be electrically connected to described at least one connection pad.
Wherein, this manufacture method also comprises:
Configure at least one the 3rd electronic component on this recess, and make described at least one the 3rd electronic component be electrically connected to described at least one the first conductive junction point by this line layer; And
Form the second cover layer, to be coated described at least one the 3rd electronic component and this line layer at least partly.
Wherein, this manufacture method also comprises:
Described at least one the 3rd electronic component is electrically connected to described at least one the second conductive junction point by this line layer.
In sum, encapsulating structure and manufacture method thereof that the embodiment of the present invention proposes, by the line layer of at least one the electronic component top on substrate, can provide electronic system in single encapsulating structure, to complete the three-dimensional encapsulation of electronic component, and can shorten line length, effectively to increase electronic system usefulness electrically, and can reduce the usable floor area of substrate surface, to promote space availability ratio of encapsulating structure etc.
For enabling further to understand feature of the present invention and technology contents, refer to following about detailed description of the present invention and accompanying drawing, but these explanations and appended graphic the present invention that are only used for illustrating but not are done any restriction to interest field of the present invention.
Accompanying drawing explanation
Figure 1A to Figure 1B is the encapsulating structure of one embodiment of the invention schematic top plan view in manufacture process.
Encapsulating structure in Fig. 1 C demonstration Figure 1B is along the generalized section of 1C-1C line.
Encapsulating structure in Fig. 1 D demonstration Figure 1B is along the generalized section of 1D-1D line
Fig. 2 A to Fig. 2 B is the encapsulating structure of another embodiment of the present invention schematic top plan view in manufacture process.
Fig. 3 is the generalized section of the encapsulating structure of another embodiment of the present invention.
Fig. 4 is the generalized section of the encapsulating structure of another embodiment of the present invention.
Fig. 5 is the generalized section of the encapsulating structure of another embodiment of the present invention.
Fig. 6 is the flow chart of manufacture method of the encapsulating structure of another embodiment of the present invention.
Wherein, description of reference numerals is as follows:
100,100 ', 200,300,400 encapsulating structures
101 substrate strip
102 lines of cut
110 substrates
111 first element areas
112 second element areas
113 connection pads
115 loading ends
121 first electronic components
122 second electronic components
123,123 ', 123 " the 3rd electronic component
125 first conductive junction points
127 second conductive junction points
130 first cover layers
131 first exposed regions
132 second exposed regions
133 the 3rd exposed regions
135 recesses
137 bottom surfaces
139 sidewalls
140 line layers
150 three element regions
160 second cover layers
G angle
S surface
S1 ~ S4 step
Embodiment
(embodiment of encapsulating structure and manufacture method thereof)
See also Figure 1A to Fig. 1 D, Figure 1A to Figure 1B is the encapsulating structure 100 of one embodiment of the invention schematic top plan view in manufacture process; Encapsulating structure 100 in Fig. 1 C demonstration Figure 1B is along the generalized section of 1C-1C line; Encapsulating structure 100 in Fig. 1 D demonstration Figure 1B is along the generalized section of 1D-1D line.Encapsulating structure 100 comprises substrate 110, a plurality of electronic component (comprising the first electronic component 121 and the second electronic component 122), the first cover layer 130 and line layer 140.As shown in Figure 1A, substrate 110 can also can provide the carrier of electronic component (comprising the first electronic component 121 and the second electronic component 122) electricity connection function for any support electronic component (comprising the first electronic component 121 and the second electronic component 122), for example printed circuit board (PCB) (Printed Wiring Board, PWB) or hard circuit board (flex-rigid wiring board).Substrate 110 comprises at least one connection pad 113 and top line layer (not illustrating).Connection pad 113 is that electric conducting material is made, to be electrically connected to conducting wire (not illustrating) or the plane of other function (not illustrating).In the present embodiment, described at least one connection pad 113 is ground mat, and is electrically connected to ground plane (not illustrating), and wherein, connection pad 113 is all positioned on substrate 110 or imbeds circuit substrate 110 with line layer (not illustrating).The surperficial S of substrate 110 comprises loading end 115, and loading end 115 has one first element area 111 and one second element area 112.
First, configure a plurality of electronic components (comprising the first electronic component 121 and the second electronic component 122) on substrate 110.In the present embodiment, it is for example the passive device of 0402 specification that the first element area 111 disposes a plurality of the first electronic component 121, the first electronic components 121, and at least one first electronic component 121 has first conductive junction point 125.The first conductive junction point 125 is that electric conducting material is made, so that electric connection to be provided.In the present embodiment, the first conductive junction point 125 is the part welding end (terminal) on the first electronic component 121.The quantity of the first conductive junction point 125 can design according to actual demand, and embodiments of the invention do not limit.In the encapsulating structure 100 of the present embodiment, the quantity of the first conductive junction point 125 is a plurality of, but embodiments of the invention do not limit.
The second element area 112 disposes at least one second electronic component 122 and has at least one second conductive junction point 127, the second electronic component 122 is for example control chip.As shown in Figure 1A, the second electronic component 122 can be one, but embodiments of the invention do not limit, and the second electronic component 122 in the second element area 112 can be one or more.Described at least one second conductive junction point 127 is that electric conducting material is made equally, so that electric connection to be provided, and the structure example of the second conductive junction point 127 metal gasket, tin ball or elargol etc. on substrate 110 in this way.The structure of the second conductive junction point 127 and quantity are to design according to actual demand, and embodiments of the invention do not limit, and in other embodiment, the quantity of the second conductive junction point 127 can be only one.It is worth mentioning that, kind and the specification of electronic component 121,122 are to design according to actual demand, and embodiments of the invention do not limit.
Then, as shown in Figure 1B, form the first cover layer 130 with coated electric components 121,122, wherein the first cover layer 130 has recess 135, and recess 135 is positioned at least one second electronic component 122.The first cover layer 130 is, with mould closure material (molding material), the first element area 111 and the second element area 112 are carried out to the insulating barrier that a sealing adhesive process is produced, with coated electric components 121,122 and substrate 110.Sealing adhesive process is for example drape forming technique (over-molding process), and the material of the first cover layer 130 is for example epoxy resin or silica gel.Particularly, owing to being arranged at least one second electronic component 122 on the second element area 112 vertical height to loading end 115, be less than the first electronic component 121 of being arranged on the first element area 111 to the vertical height of loading end 115, and the first cover layer 130 be with mould closure material along shape cover the electronic component 121,122 on the first element area 111 and the second element area 112.By this, to form first cover layer 130 with recess 135, and recess 135 is to be arranged on the second element area 112, and this means, recess 135 is to be arranged on described at least one second electronic component 122.
Refer to Fig. 1 C, in this specific embodiment, recess 135 has the bottom surface 137 and four sidewalls 139 that are approximately perpendicular to bottom surface 137 that are roughly parallel to loading end 115.The area of bottom surface 137 and shape, be not less than described at least one second electronic component 122 in area and the shape of the upright projection of loading end 115.In addition, in other embodiment, first cover layer 130 with recess 135 also can utilize mould envelope mould and form by metaideophone moulding or pressure injection technique, or utilize accurate milling cutter and remove part the first cover layer 130 to form recess 135 by cutting technique, embodiments of the invention are not limited at this.
Please refer to Figure 1B and Fig. 1 C, then, on the first cover layer 130, the position of corresponding at least one the first conductive junction point 125 forms at least one first exposed region 131, to expose described at least one first conductive junction point 125, and the position of corresponding at least one the second conductive junction point 127 forms at least one second exposed region 132 on the first cover layer 130, to expose described at least one second conductive junction point 127.In the present embodiment, the first exposed region 131 and the second exposed region 132 are all perforation, and the method for formation the first exposed region 131 and the second exposed region 132 can all adopt laser drilling process (laser drilling process).Specifically, laser drill head (not illustrating) can be aimed at respectively to the position of the first conductive junction point 125 and the second conductive junction point 127, and to the cutting of holing of the first cover layer 130, to remove part the first cover layer 130, in order to form minimum diameter, be for example all the first exposed region 131 and second exposed region 132 of 80 microns.
By this, at least one first exposed region 131 being formed on the first cover layer 130 can expose described at least one first conductive junction point 125, and at least one second exposed region 132 being formed on the first cover layer 130 can expose described at least one second conductive junction point 127.In addition, also can adopt other to remove the method for the first cover layer 130, such as electric paste etching, chemical etching or machine drilling etc., to form at least one first exposed region 131 and at least one second exposed region 132, and expose respectively at least one first conductive junction point 125 and at least one second conductive junction point 127.It is worth mentioning that, size and shape and the quantity of the first exposed region 131 and the second exposed region 132 are to design according to actual demand, and embodiments of the invention do not limit.
For example, in other embodiment, at least one first exposed region 131 can be opening.Say further, the structure of at least one the first conductive junction point 125 can be part welding end and is positioned over elargol or the scolding tin (solder) in part welding end, and the end face of described at least one the first conductive junction point 125 can be concordant with the surface of the first cover layer 130.Moreover, while the first element area 111 and the second element area 112 being carried out to sealing adhesive process with mould closure material, can seal mould so that mould closure material does not cover the end face of described at least one the first conductive junction point 125 by mould.Therefore after completing sealing adhesive process, can be formed directly in first cover layer 130 with at least one the first exposed region 131, that is to say, do not need accurate milling cutter cutting or bore process to form the first exposed region 131 of the first cover layer 130.
In addition, please refer to Figure 1B and Fig. 1 D, the first cover layer 130 of encapsulating structure 100 more can comprise at least one the 3rd exposed region 133, and at least one connection pad 113 that described at least one the 3rd exposed region 133 exposes on substrate 110.Specifically, more can on the first cover layer 130, form at least one the 3rd exposed region 133 in the position of corresponding at least one connection pad 113, to expose substrate 110 the above at least one connection pad 113.In the present embodiment, the 3rd exposed region 133 can be perforation, but shape size and quantity are not also limited, the minimum diameter of the 3rd exposed region 133 is for example 80 microns, and the mode that forms the 3rd exposed region 133 is roughly the same with the mode that forms the first exposed region 131, Gu it is no longer repeated.
Please answer and consult in the lump Figure 1B, Fig. 1 C and Fig. 1 D.Finally, on the first cover layer 130, form line layer 140, at least one connection pad 113 with cover part recess 135, at least one first conductive junction point 125 exposing, at least one second conductive junction point 127 exposing and exposure, and be electrically connected at least one first conductive junction point 125, at least one the second conductive junction point 127 and at least one connection pad 113, and complete encapsulating structure 100.In this specific embodiment, can first deposits conductive material with along shape cover recess 135, at least one first exposed region 131, at least one second exposed region 132 and at least one the 3rd exposed region 133.Specifically, electric conducting material along shape cover bottom surface 137 and the sidewall 139 of recess 135, and along shape ground, cover or fill madial wall and at least one first conductive junction point 125 of at least one the first exposed region 131, to be electrically connected to described at least one first conductive junction point 125.
Similarly, electric conducting material along shape cover or fill madial wall and at least one second conductive junction point 127 of at least one the second exposed region 132, and along shape ground, cover madial wall and at least one connection pad 113 of at least one the 3rd exposed region 133, to be electrically connected to described at least one second conductive junction point 127 and described at least one connection pad 113.Then, the electric conducting material being deposited with the mode patterning part of laser ablation, to form line layer 140, but the mode that forms patterning is not limited.By this, line layer 140 can be electrically connected at least one first conductive junction point 125 by least one the first exposed region 131, by at least one second exposed region 132, be electrically connected at least one second conductive junction point 127, and be electrically connected at least one connection pad 113 by least one the 3rd exposed region 133.
In the present embodiment, the mode of deposits conductive material is such as being spraying plating (spray coating), plating (electroplating), electroless plating (electrolessplating), evaporation or sputter (sputtering) etc.The preferred thickness of line layer 140 is between 200 microns to 1000 microns, and line layer 140 can be consisted of the combined deposition multilayer conductive material of for example metal material, alloy material, conducting polymer composite or above-mentioned material.In addition, the pattern of line layer 140 is that affiliated technical field has and conventionally knows that the knowledgeable can be according to the row design of actual service condition demand footpath, therefore embodiments of the invention are not limited at this.In other embodiment, the mode that forms line layer 140 can complete by a patterning shielding (mask) is provided, and arranges to be shielded from the first cover layer, to carry out deposits conductive material technique again.
In the present embodiment, encapsulating structure 100 can more comprise that 150, the three element regions 150, three element region are arranged on recess 135.Three element region 150 can have (or configuration) at least one the 3rd electronic component 123.When configuration the 3rd electronic component 123 is on the bottom surface 137 of recess 135, the 3rd electronic component 123 can be electrically connected at least one first conductive junction point 125, at least one the second conductive junction point 127 and at least one connection pad 113 by line layer 140, is electrically connected to by this described at least one first electronic component 121, described at least one second electronic component 122 and described at least one connection pad 113.As shown in Figure 1B, three element region 150 is arranged at the bottom surface 137 of recess 135.It is worth mentioning that, the size and shape in three element region 150 is to design according to actual demand, embodiments of the invention do not limit, and in other embodiment, three element region 150 also can be arranged at as the part bottom surface 137 of recess 135 and/or the partial sidewall 139 of recess 135.
Specifically, as shown in Figure 1 C, line layer 140 be along shape cover the bottom surface 137 and sidewall 139 of recess 135, and be electrically connected at least one first conductive junction point 125, by least one second exposed region 132, be electrically connected at least one second conductive junction point 127 by least one first exposed region 131, and be electrically connected at least one connection pad 113 by least one the 3rd exposed region 133.Therefore at least one the 3rd electronic component 123, being disposed on recess 135 can be electrically connected at least one first conductive junction point 125, at least one the second conductive junction point 127 and at least one connection pad 113 by line layer 140.
It is worth mentioning that, in the present embodiment, the 3rd electronic component 123 is for example the passive device of 0201 specification, in addition, the kind of the 3rd electronic component 123 and specification are to design according to actual demand, and the configuration mode of the 3rd electronic component 123 is according to actual demand with quantity and coordinates line layer 140 and design, embodiments of the invention do not limit.
(another embodiment of encapsulating structure and manufacture method thereof)
Please refer to Fig. 2 A to Fig. 2 B, Fig. 2 A to Fig. 2 B is the encapsulating structure 100 ' of another embodiment of the present invention schematic top plan view in manufacture process.All the two is roughly similar to the encapsulating structure 100 of previous embodiment and manufacture method thereof for the encapsulating structure 100 ' of the present embodiment and manufacture method thereof, and only for the present embodiment, is elaborated from different the locating between previous embodiment below.
As shown in Figure 2 A, first, provide circuit substrate bar 101.Circuit substrate bar 101 has a plurality of substrates 110, and substrate 110 is defined out by many lines of cut 102 on circuit substrate bar 111.Similarly, the loading end 115 of each substrate 110 all has one first element area 111 and one second element area 112.Therefore, can configure a plurality of electronic components (comprising the first electronic component 121 and the second electronic component 122) on each substrate 110 simultaneously.
Then, as shown in Figure 2 B, form the first cover layer 130 to be coated described a plurality of electronic component 121,122, and form a plurality of recesses 135 in the first cover layer 130, and each recess 135 is positioned at least one the second electronic component 122 upper of each substrate 110.In the present embodiment, can to a plurality of substrates 110, carry out in the lump sealing adhesive process by mould closure material (molding material), with along shape be coated electronic component 121,122 on each substrate 110 and each substrate 110 of part.Its in Fig. 2 A to Fig. 2 B is in process detail as described in Figure 1A to Fig. 1 D, and the art has knows that the knowledgeable should know its execution mode easily by inference conventionally, therefore do not add and repeat at this.
Finally, along line of cut 102 cutting substrates 110, to complete a plurality of encapsulating structures 100 '.Specifically, can pass through cutter cutting technique (blade sawing process) or laser cutting parameter, cut bottom surface by substrate 110, with separating base plate 110 and the first cover layer 130 of being covered in the loading end 115 of substrate 110, and completes a plurality of encapsulating structures 100 '.
(another embodiment of encapsulating structure and manufacture method thereof)
Please refer to Fig. 3, Fig. 3 is the generalized section of the encapsulating structure 200 of another embodiment of the present invention.All the two is roughly similar to the encapsulating structure 100 of previous embodiment and manufacture method thereof for the encapsulating structure 200 of the present embodiment and manufacture method thereof, and only for the present embodiment, is elaborated from different the locating between previous embodiment below.
In the present embodiment, encapsulating structure 200 can more comprise that 150, the three element regions 150, three element region are arranged on recess 135.As shown in Figure 3, specifically, configure at least one the 3rd electronic component 123 ' or 123 " on the bottom surface 137 of recess 135; by this, the 3rd electronic component 123 ', 123 " by line layer 140, be electrically connected at least one first conductive junction point 125 or be also electrically connected at least one second conductive junction point 127 (not shown) depending on actual demand.The 3rd electronic component 123 ' is 0402 or the passive device of small dimension more, and the 3rd electronic component 123 " be control chip.Therefore the 3rd electronic component 123 ' on three element region 150 to the vertical height of loading end 115 is greater than the first electronic component 121 on the first electronic component region 111 to the vertical height of loading end 115, and the 3rd electronic component 123 on three element region 150 " be less than the first electronic component 121 on the first electronic component region 111 to the vertical height of loading end 115 to the vertical height of loading end 115; but the 3rd electronic component 123 ' and 123 " part specifications and shape be to design according to actual demand, the present invention is not limited.
Encapsulating structure 200 more comprises the second cover layer 160, with cover three element region 150 and on the 3rd electronic component.As shown in Figure 3, particularly, can form one second cover layer 160 to be coated the 3rd electronic component 123 ', 123 ", and coated exposed line layer 140 and at least one the first exposed region 131.What is more, the second cover layer 160 also can be coated exposed line layer 140 and at least one the second exposed region, or looks actual demand also coated exposed line layer 140 and at least one the 3rd exposed region (not shown).
The second cover layer 160 is, with mould closure material, the insulating barrier that a sealing adhesive process is produced is carried out in three element region 150, to be coated the 3rd electronic component 123 ', 123 " and recess 135 at least local; what is more, also will be coated exposed at least part of line layer 140.In this specific embodiment, the second cover layer 160 be along shape cover the 3rd electronic component 123 ', 123 on three element region 150 ", recess 135 is at least local and exposed at least part of line layer 140.All the other process details in Fig. 3 are as described in Figure 1A to Fig. 1 D, and the art has knows that the knowledgeable should know its execution mode easily by inference, does not add and repeats at this conventionally.
(another embodiment of encapsulating structure and manufacture method thereof)
Please refer to Fig. 4, Fig. 4 is the generalized section of the encapsulating structure 300 of another embodiment of the present invention.All the two is roughly similar to the encapsulating structure 100 of previous embodiment and manufacture method thereof for the encapsulating structure 300 of the present embodiment and manufacture method thereof, and only for the difference between the present embodiment and previous embodiment, is elaborated below.As shown in Figure 4, the shape G that has angle is intersected in the sidewall of the present embodiment recess 135 139 and bottom surface 137, and angle G is preferably between 90 degree to 135 degree.While forming line layer 140 on the first cover layer 130, electric conducting material be along shape cover sidewall 139 and the bottom surface 137 of recess 135, and angle G designs according to actual demand, to promote yield and the elasticity of deposits conductive material technique, embodiments of the invention do not limit.All the other process details in Fig. 4 are as described in Figure 1A to Fig. 1 D, and the art has knows that the knowledgeable should know its execution mode easily by inference, does not add and repeats at this conventionally.
(another embodiment of encapsulating structure and manufacture method thereof)
Please refer to Fig. 5, Fig. 5 is the generalized section of the encapsulating structure 400 of another embodiment of the present invention.All the two is roughly similar to the encapsulating structure 100 of previous embodiment and manufacture method thereof for the encapsulating structure 400 of the present embodiment and manufacture method thereof, and only for the difference between the present embodiment and previous embodiment, is elaborated below.As shown in Figure 5, the sidewall 139 of the present embodiment recess 135 is stairstepping.While forming line layer 140 on the first cover layer 130, electric conducting material be along shape cover sidewall 139 and the bottom surface 137 of recess 135, and the shape of sidewall 139 is to design according to actual demand, to promote yield and the elasticity of deposits conductive material technique, embodiments of the invention do not limit.All the other process details in Fig. 5 are as described in Figure 1A to Fig. 1 D, and the art has knows that the knowledgeable should know its execution mode easily by inference, does not add and repeats at this conventionally.
(embodiment of the manufacture method of encapsulating structure)
Above-described embodiment can be summarized the manufacture method of encapsulating structure of the present invention, please refer to the flow chart of Fig. 6.First, configure a plurality of electronic components on substrate, at least one first electronic component in described a plurality of electronic components has the first conductive junction point (step S1); Form the first cover layer to be coated described a plurality of electronic component, wherein the first cover layer has recess, and recess is arranged at least one second electronic components of described a plurality of electronic components (step S2); On the first cover layer, form at least one first exposed region, to expose at least one first conductive junction point (step S3); Finally, on the first cover layer, form line layer, to be covered at least one first conductive junction point of small part recess and described exposure, and be electrically connected to described at least one first conductive junction point (step S4).
According to different product, above-mentioned flow process more can be included in and on the first cover layer, form at least one second exposed region, to expose at least one second conductive junction point on substrate, and line layer covers at least one second conductive junction point of described exposure and be electrically connected to described at least one second conductive junction point.Moreover, above-mentioned flow process or more can be included on the first cover layer and form at least one the 3rd exposed region, to expose at least one connection pad on substrate, and line layer covers at least one connection pad of described exposure and be electrically connected to described at least one connection pad.
In addition, above-mentioned flow process is after forming the step of line layer, more can comprise that at least one the 3rd electronic component of configuration is on recess, and make at least one the 3rd electronic component be electrically connected at least one first conductive junction point and at least one the second conductive junction point by line layer; Next, form the second cover layer to be coated at least one the 3rd electronic component and at least part of line layer and at least one the first exposed region.What is more, the second cover layer also can be coated exposed line layer and at least one the second exposed region, or looks actual demand also coated exposed line layer and at least one the 3rd exposed region.
In sum, the embodiment of the present invention provides a kind of encapsulating structure and manufacture method thereof, utilize the difference in height of the electronic component on substrate, formation has the first cover layer of recess, and will on line layer, moving to the top of the electronic component on base plate carrying face, line layer is electrically connected to electronic component and the connection pad on substrate by tectal first, second and third exposed region.The encapsulating structure providing by above-described embodiment and manufacture method thereof can shorten line length, and the length that circuit shortens can reach a millimeter grade, effectively increases electronic system usefulness electrically.
By the line layer of the electronic component top on substrate, can provide electronic system in single encapsulating structure, to complete the three-dimensional encapsulation of electronic component, make the design that is arranged at the line layer on base plate carrying face have more elasticity, can reduce line layer area and density required on base plate carrying face, to reduce the usable floor area of base plate carrying face, promote the space availability ratio of encapsulating structure.Moreover, in the encapsulating structure and manufacture method thereof providing in the embodiment of the present invention, by the recess of electronic component top, can reduce the configuration factor (Form Factor) of encapsulating structure, contribute to microminiaturized product design, to increase the elasticity of product design, reduce product material and processing cost.
The foregoing is only embodiments of the invention, it is not in order to limit scope of patent protection of the present invention.Anyly have the knack of alike skill person, within not departing from spirit of the present invention and scope, the change of doing and the equivalence of retouching are replaced, and are still in scope of patent protection of the present invention.
Claims (16)
1. an encapsulating structure, is characterized in that, comprising:
Substrate, has the first element area and the second element area on the surface of this substrate;
At least one the first electronic component, is arranged in this first element area of this substrate, in described at least one the first electronic component at least one of them has the first conductive junction point;
At least one the second electronic component, is arranged at this second element area of this substrate;
The first cover layer, cover at least one the first electronic component in this first element area and cover at least one the second electronic component in this second element area, this first cover layer has recess and at least one the first exposed region, this recess is arranged on this second element area, and described at least one the first exposed region exposes described at least one the first conductive junction point; And
Line layer, is covered at least one first conductive junction point of this recess of small part and this exposure, and is electrically connected to described at least one the first conductive junction point.
2. encapsulating structure as claimed in claim 1, it is characterized in that, described at least one the first exposed region for perforation, this line layer along shape cover described at least one the first exposed region, to be electrically connected to described at least one the first conductive junction point by described at least one the first exposed region.
3. encapsulating structure as claimed in claim 1, it is characterized in that, described at least one the first exposed region is perforation, and described at least one the first exposed region of this line layer filling, to be electrically connected to described at least one the first conductive junction point by described at least one the first exposed region.
4. encapsulating structure as claimed in claim 1, is characterized in that, formation angle is intersected in the sidewall of this recess and the bottom surface of this recess, and this angle is between 90 degree to 135 degree.
5. encapsulating structure as claimed in claim 1, is characterized in that, the sidewall of this recess is stairstepping.
6. encapsulating structure as claimed in claim 1, it is characterized in that, in this second element area, there is at least one the second conductive junction point, this first cover layer also comprises at least one the second exposed region, described at least one the second exposed region exposes described at least one the second conductive junction point, and this line layer covers at least one second conductive junction point of this exposure and be electrically connected to described at least one the second conductive junction point.
7. encapsulating structure as claimed in claim 6, it is characterized in that, this first cover layer also comprises at least one the 3rd exposed region, described at least one the 3rd exposed region exposes at least one connection pad on this substrate, and this line layer covers at least one connection pad of this exposure and be electrically connected to described at least one connection pad.
8. encapsulating structure as claimed in claim 6, is characterized in that, described encapsulating structure also comprises:
Three element region, is arranged on this recess, and this three element region has at least one the 3rd electronic component, and described at least one the 3rd electronic component is electrically connected to described at least one the first conductive junction point by this line layer; And
The second cover layer, covers described at least one the 3rd electronic component.
9. encapsulating structure as claimed in claim 8, is characterized in that, described at least one the 3rd electronic component is electrically connected to described at least one the second conductive junction point by this line layer.
10. a manufacture method for encapsulating structure, is characterized in that, comprising:
Configure a plurality of electronic components on substrate, at least one the first electronic component in described a plurality of electronic components has the first conductive junction point;
Form the first cover layer, to be coated described a plurality of electronic component, and form recess in this first cover layer, this recess is arranged at least one second electronic component of described a plurality of electronic components;
On this first cover layer, form at least one the first exposed region, to expose described at least one the first conductive junction point; And
On this first cover layer, form line layer, to be covered at least one first conductive junction point of this recess of small part and this exposure, and be electrically connected to described at least one the first conductive junction point.
The manufacture method of 11. encapsulating structures as claimed in claim 10, it is characterized in that, described at least one the first exposed region is perforation, this line layer along shape cover described at least one the first exposed region, to be electrically connected to described at least one the first conductive junction point by described at least one the first exposed region.
The manufacture method of 12. encapsulating structures as claimed in claim 10, it is characterized in that, described at least one the first exposed region is perforation, and described at least one the first exposed region of this line layer filling, to be electrically connected to described at least one the first conductive junction point by described at least one the first exposed region.
The manufacture method of 13. encapsulating structures as claimed in claim 10, it is characterized in that, this manufacture method is also included in and on this first cover layer, forms at least one the second exposed region, to expose at least one the second conductive junction point on this substrate, and this line layer covers at least one second conductive junction point of this exposure and be electrically connected to described at least one the second conductive junction point.
The manufacture method of 14. encapsulating structures as claimed in claim 13, it is characterized in that, this manufacture method is also included in and on this first cover layer, forms at least one the 3rd exposed region, to expose at least one connection pad on this substrate, and this line layer covers at least one connection pad of this exposure and be electrically connected to described at least one connection pad.
The manufacture method of 15. encapsulating structures as claimed in claim 13, is characterized in that, this manufacture method also comprises:
Configure at least one the 3rd electronic component on this recess, and make described at least one the 3rd electronic component be electrically connected to described at least one the first conductive junction point by this line layer; And
Form the second cover layer, to be coated described at least one the 3rd electronic component and this line layer at least partly.
The manufacture method of 16. encapsulating structures as claimed in claim 15, is characterized in that, this manufacture method also comprises:
Described at least one the 3rd electronic component is electrically connected to described at least one the second conductive junction point by this line layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210357070.3A CN103681647B (en) | 2012-09-24 | 2012-09-24 | Encapsulating structure and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210357070.3A CN103681647B (en) | 2012-09-24 | 2012-09-24 | Encapsulating structure and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103681647A true CN103681647A (en) | 2014-03-26 |
| CN103681647B CN103681647B (en) | 2017-07-21 |
Family
ID=50318698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210357070.3A Active CN103681647B (en) | 2012-09-24 | 2012-09-24 | Encapsulating structure and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103681647B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499590A (en) * | 2002-11-05 | 2004-05-26 | �¹������ҵ��ʽ���� | Semiconductor device and its mfg. method |
| US20090008766A1 (en) * | 2007-07-02 | 2009-01-08 | Chien-Wei Chang | High-Density Fine Line Structure And Method Of Manufacturing The Same |
| US20090065920A1 (en) * | 2007-09-06 | 2009-03-12 | Eun-Chul Ahn | Semiconductor package embedded in substrate, system including the same and associated methods |
| US20110163457A1 (en) * | 2009-02-20 | 2011-07-07 | National Semiconductor Corporation | Integrated circuit micro-module |
| CN102282661A (en) * | 2009-01-27 | 2011-12-14 | 松下电工株式会社 | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof |
-
2012
- 2012-09-24 CN CN201210357070.3A patent/CN103681647B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499590A (en) * | 2002-11-05 | 2004-05-26 | �¹������ҵ��ʽ���� | Semiconductor device and its mfg. method |
| US20090008766A1 (en) * | 2007-07-02 | 2009-01-08 | Chien-Wei Chang | High-Density Fine Line Structure And Method Of Manufacturing The Same |
| US20090065920A1 (en) * | 2007-09-06 | 2009-03-12 | Eun-Chul Ahn | Semiconductor package embedded in substrate, system including the same and associated methods |
| CN102282661A (en) * | 2009-01-27 | 2011-12-14 | 松下电工株式会社 | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, and three-dimensional structure, on the surface of which wiring is provided and fabrication method thereof |
| US20110163457A1 (en) * | 2009-02-20 | 2011-07-07 | National Semiconductor Corporation | Integrated circuit micro-module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103681647B (en) | 2017-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102074552B (en) | Semiconductor device packages and manufacturing methods thereof | |
| CN104321864B (en) | Microelectronics Packaging with the non-coplanar, microelectronic component of encapsulating and solderless buildup layer | |
| CN101228625B (en) | Semiconductor package with plated connection | |
| US8822844B1 (en) | Shielding and potting for electrical circuits | |
| CN105280601B (en) | Packaging structure and packaging substrate structure | |
| TW200933765A (en) | Integrated circuit package system for shielding electromagnetic interference | |
| CN102074516A (en) | Semiconductor device packages and methods for manufacturing the same | |
| CN102144291B (en) | Semiconductor substrate, encapsulation and device | |
| US20120037411A1 (en) | Packaging substrate having embedded passive component and fabrication method thereof | |
| US20140198459A1 (en) | Stacked package device and manufacturing method thereof | |
| CN104716114A (en) | Semiconductor device | |
| CN103311225A (en) | Semiconductor package and fabrication method thereof | |
| CN105336629B (en) | The manufacturing method and Electronic Packaging module of Electronic Packaging module | |
| CN103579173A (en) | Semiconductor package and fabrication method thereof | |
| CN103811444B (en) | The manufacture method of electronic installation, system-in-package module and system-in-package module | |
| CN104576616B (en) | Module integrated circuit packaging structure and preparation method thereof | |
| TWI483377B (en) | Package structure and manufacturing method thereof | |
| CN108695299A (en) | Electronic package, bearing structure thereof and manufacturing method thereof | |
| CN103681647A (en) | Packaging structure and manufacturing method thereof | |
| CN103855135A (en) | Three dimensional through-silicon via construction | |
| CN108666279A (en) | Electronic package and manufacturing method thereof | |
| CN202905706U (en) | Three-dimensional packaging structure | |
| CN113140538A (en) | Adapter plate, packaging structure and manufacturing method of adapter plate | |
| WO2024027405A1 (en) | Chip packaging structure and manufacturing method therefor | |
| CN103681610A (en) | Chip laminated structure and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |