CN103646140A - Method for designing XDP based on NUMA computer architecture - Google Patents
Method for designing XDP based on NUMA computer architecture Download PDFInfo
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Abstract
The invention provides a method for designing an XDP based on NUMA computer architecture. An overall controller obtains through an FPGA/CPLD or a BMC/SMC is arranged and is mainly used for controlling the switch of an MUX and an SW so that dynamic intelligent configuration of an XDP link can be achieved and intelligent adaptation of the impedance matched with the link can be achieved through control over the MUX; in addition, the overall controller can further control the SW to achieve Bypass of any CPU so that fault locating can be facilitated. Compared with the prior art, the method for designing the XDP based on the NUMA computer architecture guarantees the largest flexibility of the XDP link, cost is saved, the jig debugging cost can be reduced by over 50%, the practicability is high, and the method is easy to popularize.
Description
Technical field
The present invention relates to Computer Applied Technology field, specifically a kind of XDP method for designing based on NUMA Computer Architecture.
Background technology
For convenience of commissioning examination, Ge great semiconductor manufacturer all can give debugging interface of chip configuration, and jtag interface, due to simplicity of design, allows a plurality of devices to be cascaded, and forms JTAG chain, and each device is distinguished to commissioning examination, by all big enterprises, is extensively adopted.
The jtag interface of Intel CPU is referred to as ITP interface (In Target Probe), enhancing along with debugging complexity, Intel is on the basis of ITP, by this Interface Expanding, be XDP (eXtend Debug Port) interface, by XDP interface, can observe internal memory, breakpoint is set, receive the variety of event of CPU etc., the integrated level of chip is more and more higher, and debugging becomes increasingly complex, and XDP Interface design has become the requisite part of Intel system.
Many Physical layers partitioned computer architecture based on NUMA is because its framework is complicated, and subregion state can independent assortment, the design of the XDP link more complicated that also becomes.Conventional method for designing is as follows at present:
1, take basic smallest partition as module, in each module, design independent XDP link;
2,, under multichannel subregion state, each subregion utilization XDP link separately carries out commissioning examination;
3,, under single partition state, system utilizes the XDP link of modules to complete the JTAG link of this module, between each XDP, by synchronous cable, carries out synchro control.
Adopt this method for designing, although can meet XDP, adjust test request, when multi partition state is debugged, need a plurality of XDP debuggers, and need the synchronous cable of XDP to connect; Not only increased commissioning examination hardware cost, and under the state of multi partition, because system architecture is complicated, structural design is loaded down with trivial details, in a lot of situations, the wiring of the synchronous cable of XDP is very difficult; Due to the unnecessary hardware spending of needs, therefore the reliability of design is also poor.
The XDP method for designing of the many Physical layers partitioned computer architecture based on NUMA in this paper, can overcome the above problems completely.
Summary of the invention
Technical assignment of the present invention is to solve the deficiencies in the prior art, and a kind of XDP method for designing based on NUMA Computer Architecture is provided.
Technical scheme of the present invention realizes in the following manner, this kind of XDP method for designing based on NUMA Computer Architecture, and its specific implementation step is:
One global controller is set, this global controller is realized by FPGA/CPLD or BMC/SMC, its effect is the switching of controlling MUX and SW, realize the dynamic and intelligent configuration of XDP link, by controlling MUX, realize the intelligent adaptation of link matched impedance simultaneously, by controlling SW, realize the bypass functionality of any CPU, and then location fault;
Global controller is obtained system configuration situation, and this situation comprises: system partitioning arranges, i.e. single partition system or multi-partitioned systems; Host node arranges, i.e. single partition system possesses unique host node, and each system of multi-partitioned systems is host node; Bypass arranges, and whether needs to control separately bypass CPU;
Global controller arranges the value of each SW of configuration and MUX according to system partitioning: under multichannel subregion state, each subregion utilization XDP link separately carries out commissioning examination; Under single partition state, system is controlled the switching of MUX by global controller, realizes the dynamic and intelligent configuration of XDP debugging link, and control link impedance simultaneously meets Intel design specifications, realizes an object with 1 XDP completion system debugging.
When described system partitioning adopts multi-partitioned systems, this system is complete symmetry design.
Each CPU all designs Bypass link, i.e. bypass functionality link, and the control signal of Bypass is controlled by CPU signal in place and global controller simultaneously: when CPU is not in place, this position can be by intelligent auto by pass; Global controller is the arbitrary CPU of bypass arbitrarily, locates fault while facilitating commissioning examination.
The beneficial effect that the present invention compared with prior art produced is:
A kind of XDP method for designing based on NUMA Computer Architecture of the present invention is by band external system monitoring management unit detecting system subregion state, intelligence is switched XDP link, the unique XDP link that can realize under single Physical layer Zone system is controlled, and each subregion independence XDP link that also can realize under many Physical layers partitioned computer architecture is controlled; By this intelligent switchover policy, both guaranteed that the XDP under the architecture of multi partition was independent of each other, separate, also guaranteed the simplified design of XDP under single partition architecture, improve debugging and testing efficiency; Can support CPU online/offline intelligence detecting simultaneously, can this CPU of intelligent bypass when CPU offline, guaranteed the maximum flexibility of XDP link; Save cost, can reduce debugging tool cost more than 50%, practical, applied widely, be easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 is structural representation block diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, a kind of XDP method for designing based on NUMA Computer Architecture of the present invention is described in detail below.
As shown in Figure 1, the invention provides a kind of XDP method for designing based on NUMA Computer Architecture, its specific implementation step is:
One global controller is set, this global controller is realized by FPGA/CPLD or BMC/SMC, its effect is the switching of controlling multiplexer MUX and exchange system SW, realize the dynamic and intelligent configuration of XDP link, by controlling MUX, realize the intelligent adaptation of link matched impedance simultaneously, by controlling SW, realize the bypass functionality of any CPU, and then location fault;
Global controller is obtained system configuration situation, and this situation comprises: system partitioning arranges, i.e. single partition system or multi-partitioned systems; Host node arranges, i.e. single partition system possesses unique host node, and each system of multi-partitioned systems is host node; Bypass arranges, and whether needs to control separately bypass CPU;
Take basic smallest partition as module, in each module, design independent XDP link;
Global controller arranges the value of each SW of configuration and MUX according to system partitioning: under multichannel subregion state, each subregion utilization XDP link separately carries out commissioning examination; Under single partition state, system is controlled the switching of MUX by global controller, realizes the dynamic and intelligent configuration of XDP debugging link, and control link impedance simultaneously meets Intel design specifications, realizes an object with 1 XDP completion system debugging.
Concrete setting up procedure as shown in Figure 1, single partition system:
Host node: MUX1～MUX7 is set and is connected to XDP connector, MUX8 and MUX9 disconnected end build-out resistor are set, be connected to from node;
From node: MUX1 and MUX2 are set and are connected to terminal build-out resistor, MUX3 ~ MUX7 is set and disconnects XDP connector, the signal (or transmitting a signal to main XDP) that receives autonomous XDP, arranges MUX8 and MUX9 disconnected end build-out resistor, receives the signal of autonomous node;
Multi-partitioned systems:
Under multi-partitioned systems, each node is host node, and the XDP interface of each node utilization oneself completes commissioning examination, and under multi-partitioned systems, the configuration of each MUX is as follows:
MUX1～MUX7 is set and is connected to XDP connector, MUX8 and MUX9 are set and are connected to terminal build-out resistor;
When described system partitioning adopts multi-partitioned systems, this system is complete symmetry design, as shown in Figure 1: XDP1 or XDP2 all can be used as XDP debugging interface, by the switching of Global Controller, realize XDP link intelligence configuration.(for convenience of signal, only drawn the situation as single partition debugging interface with XDP1 in figure, the interconnecting method with XDP2 during as debugging interface can be processed with reference to XDP1.）。
Each CPU all designs Bypass link, i.e. bypass functionality link, and the control signal of Bypass is controlled by CPU signal in place and global controller simultaneously: when CPU is not in place, this position can be by intelligent auto by pass; Global controller is the arbitrary CPU of bypass arbitrarily, locates fault while facilitating commissioning examination.Under default situations, each SW is by CPU signal controlling in place, and when CPU is in place, TDI and TDO signal, through CPU, add this CPU in XDP link, and when CPU is not in place, TDI is directly connected with TDO signal, without CPU, has realized the automatic Bypass of CPU; In some cases, for convenient location fault, CPU is not removed to operation, can utilize the gating signal of Global Controller control SW, realize the Bypass of CPU simultaneously.
In technique scheme, recommend parts selection: MUX can use the demultiplexing device that model is 74LVC1G3157 to realize, SW can utilize two 74LVC1G3157 to realize; MUX and SW also can realize with other similar device, require its conduction impedance will be lower than 5 Ohm.
The foregoing is only embodiments of the invention, within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (3)
1. the XDP method for designing based on NUMA Computer Architecture, is characterized in that its specific implementation step is:
One global controller is set, this global controller is realized by FPGA/CPLD or BMC/SMC, its effect is the switching of controlling MUX and SW, realize the dynamic and intelligent configuration of XDP link, by controlling MUX, realize the intelligent adaptation of link matched impedance simultaneously, by controlling SW, realize the bypass functionality of any CPU, and then location fault;
Global controller is obtained system configuration situation, and this situation comprises: system partitioning arranges, i.e. single partition system or multi-partitioned systems; Host node arranges, i.e. single partition system possesses unique host node, and each system of multi-partitioned systems is host node; Bypass arranges, and whether needs to control separately bypass CPU;
Global controller arranges the value of each SW of configuration and MUX according to system partitioning: under multichannel subregion state, each subregion utilization XDP link separately carries out commissioning examination; Under single partition state, system is controlled the switching of MUX by global controller, realizes the dynamic and intelligent configuration of XDP debugging link, and control link impedance simultaneously meets Intel design specifications, realizes an object with 1 XDP completion system debugging.
2. a kind of XDP method for designing based on NUMA Computer Architecture according to claim 1, is characterized in that: when described system partitioning adopts multi-partitioned systems, this system is complete symmetry design.
3. a kind of XDP method for designing based on NUMA Computer Architecture according to claim 1, it is characterized in that: each CPU all designs Bypass link, it is bypass functionality link, the control signal of Bypass is controlled by CPU signal in place and global controller simultaneously: when CPU is not in place, this position can be by intelligent auto by pass; Global controller is the arbitrary CPU of bypass arbitrarily, locates fault while facilitating commissioning examination.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105141443A (en) * | 2015-07-23 | 2015-12-09 | 浪潮(北京)电子信息产业有限公司 | Server test system and interface configuration method |
| CN108280002A (en) * | 2018-01-10 | 2018-07-13 | 郑州云海信息技术有限公司 | XDP and DCI mixing debugging interface hardware topologies in 8 road servers of one kind |
| CN110119357A (en) * | 2019-05-15 | 2019-08-13 | 苏州浪潮智能科技有限公司 | A kind of debug hardware circuit |
| CN110825454A (en) * | 2019-10-30 | 2020-02-21 | 苏州浪潮智能科技有限公司 | JTAG link device of server mainboard and design method |
| CN112543125A (en) * | 2020-12-22 | 2021-03-23 | 宁波均联智行科技股份有限公司 | Serial communication system and link switching method applied to same |
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| CN103425582A (en) * | 2013-08-19 | 2013-12-04 | 浪潮电子信息产业股份有限公司 | QPI (Quick Path Interconnect) bus signal integrity testing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105141443A (en) * | 2015-07-23 | 2015-12-09 | 浪潮(北京)电子信息产业有限公司 | Server test system and interface configuration method |
| CN105141443B (en) * | 2015-07-23 | 2018-06-19 | 浪潮(北京)电子信息产业有限公司 | Server test system and interface allocation method |
| CN108280002A (en) * | 2018-01-10 | 2018-07-13 | 郑州云海信息技术有限公司 | XDP and DCI mixing debugging interface hardware topologies in 8 road servers of one kind |
| CN108280002B (en) * | 2018-01-10 | 2021-09-10 | 郑州云海信息技术有限公司 | XDP and DCI hybrid debugging interface hardware topological structure in 8-way server |
| CN110119357A (en) * | 2019-05-15 | 2019-08-13 | 苏州浪潮智能科技有限公司 | A kind of debug hardware circuit |
| CN110119357B (en) * | 2019-05-15 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Debug hardware circuit |
| CN110825454A (en) * | 2019-10-30 | 2020-02-21 | 苏州浪潮智能科技有限公司 | JTAG link device of server mainboard and design method |
| CN112543125A (en) * | 2020-12-22 | 2021-03-23 | 宁波均联智行科技股份有限公司 | Serial communication system and link switching method applied to same |
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