CN102880583B - Device and method for configuring dynamic link of multi-way server - Google Patents
Device and method for configuring dynamic link of multi-way server Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
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Abstract
The invention discloses a device and a method for configuring a dynamic link of a multi-way server. To reasonably verify a multi-way server system structure and realize the interconnection communication of processors, a double-step configuration is adopted in the device and the method for configuring the dynamic link of the multi-way server so as to realize the dynamic transformation of a processor interconnection link from a direct connection mode to an FPGA (field programmable gate array) verification chip. The link initialization of interface logics realized by the multi-way processors and the FPGA chip is realized respectively; the internal interconnection of the interface logics realized by the FPGA chips is realized by adopting the control logic, so that the interconnection communication during the processing period only passes through a test link realized by the FPGA chip. The interconnection link between processors in the multi-way server system is guaranteed to exist at any time, and meanwhile dynamic availability transformation of physical links between processors is realized, the complexity in verification platform hardware design is greatly reduced, and the transparent transmission of the physical links between the processors based on the FPGA chip is accomplished.
Description
Technical field
The present invention relates to high-end server field, be specifically related to a kind of multipath server dynamic link inking device and method.
Background technology
Along with the develop rapidly of computer technology and integrated circuit technique, in order to meet the needs of socio-economic development, high-end server system becomes one of bottleneck of restriction social development key area.Huge data calculate and data analysis, and the performance requirements of message area to server system such as complicated pattern analysis and science budget are high.Therefore need to build huge multipath server system, so that the better application demand adapting to current each field, but be also absorbed in the technical barrier of interconnect verification and system core chipset Design for Verification Platform between multipath server system processor on the other hand.
Summary of the invention
In order to reasonably verify multipath server system architecture, realize the connection communication between each processor, the present invention proposes a kind of multipath server dynamic link inking device and method.
In order to solve the problems of the technologies described above, the invention provides a kind of multipath server dynamic link inking device, comprise configuration module, link initialization control module and multiple processor logic interface,
Described processor logic interface is used for connecting according to the configuration of configuration module and corresponding processor;
Described configuration module is used for for each processor configures a processor logic interface corresponding with described processor, and between processor and corresponding processor logic interface, set up interface link;
Described link initialization control module is used for according to the intraconnection link of each processor logic interface of pre-connection link configuration between each processor, make each processor by with pre-connection link described in the intraconnection link establishment of the interface link of corresponding processor logic interface, each processor logic interface;
Described interface link is the communication link between processor and processor logic interface, and described intraconnection link is the logical communications links between two processor logic interfaces.
Further, the pre-connection link between each processor described is the direct connected link of each processor, and described direct connected link is the communication link between every two processors.
Further, described link initialization control module and multiple processor logic interface, utilize FPGA to realize.
Further, described configuration module is also for before the interface link between each processor of configuration and processor logic interface, and configure the direct connected link of each processor, described direct connected link is the communication link between every two processors.
Further, described link initialization control module also for after totality interconnecting link is set up, is fed back a link to configuration module and to be finished signal;
Described configuration module also for finishing after signal receiving link, breaking part or all direct connected link.
Further, described inking device also comprises monitoring module,
Described monitoring module, for monitoring the duty of link initialization control module and multiple processor logic interface, when any one or multiple processor logic interface and/or link initialization control module operation irregularity, gives a warning.
Further, described duty comprises the interface link connection status of each processor with corresponding processor logic interface and the intraconnection link connection state of each processor logic interface; Described operation irregularity refers to that any one processor is with the interface link of corresponding processor logic interface or the intraconnection chain of any one processor logic interface breaks down or initialization is unsuccessful.
In order to solve the problems of the technologies described above, present invention also offers a kind of multipath server dynamic link collocation method, comprising:
Steps A, configure interface link between each processor and corresponding processor logic interface;
Step B, configure the intraconnection link of each processor logic interface;
Described interface link is the communication link between processor and processor logic interface, and described intraconnection link is the logical communications links between two processor logic interfaces.
Further, before steps A, also comprise: the direct connected link configuring each processor, described direct connected link is the communication link between every two processors.
Further, after stepb, also comprise: breaking part or all direct connected link.
Further, described method also comprises monitoring link initialization control module and the duty of multiple processor logic interface, when any one or multiple processor logic interface and/or link initialization control module operation irregularity, gives a warning.
Further, described duty comprises the interface link connection status of each processor with corresponding processor logic interface and the intraconnection link connection state of each processor logic interface; Described operation irregularity refers to that any one processor is with the interface link of corresponding processor logic interface or the intraconnection chain of any one processor logic interface breaks down or initialization is unsuccessful.
Compared with prior art, multipath server dynamic link inking device of the present invention and method adopt two step configuration to realize processor interconnecting link from direct-connected mode to the dynamic conversion of FPGA proofing chip.Realize the link initialization of the interface logic that multichannel processor and fpga chip realize respectively, the interface logic intraconnection adopting steering logic to realize fpga chip to realize, the test link that during making process, connection communication realizes by means of only fpga chip.Ensure that the interconnecting link moment in multipath server system between processor exists, the dynamic availability simultaneously achieving physical link between processor transforms, greatly reduce the complexity of verification platform hardware design, complete the transparent transmission of physical link between the processor based on fpga chip.And ensure that fpga chip achieves the completeness of interconnect interface protocol logic and system core chipset logic verification platform.
Accompanying drawing explanation
Fig. 1 is the structural representation of two road server dynamic link inking devices of the embodiment of the present invention; Fig. 2 is the structural representation of three road server dynamic link inking devices of the embodiment of the present invention; Fig. 3 is the structural representation of four road server dynamic link inking devices of the embodiment of the present invention; Fig. 4 is the process flow diagram of the multipath server dynamic link collocation method of the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, hereinafter will be described in detail to embodiments of the invention by reference to the accompanying drawings.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combination in any mutually.
The multipath server dynamic link inking device of the embodiment of the present invention and scheme, the feature of interconnecting link project organization between processor in main consideration multipath server system, first multichannel processor and the initialization of fpga chip interface link is realized, adopt steering logic to realize interface internal logic interconnection, complete connection communication between multichannel processor with this.
The multipath server dynamic link inking device that the embodiment of the present invention provides, mainly comprises configuration module 1, link initialization control module 2 and multiple processor logic interface 3,
Described configuration module 1 is for configuring the interface link between each processor and corresponding processor logic interface 3;
Described link initialization control module 2 for configuring the intraconnection link of each processor logic interface 3, make each processor by with the interface link of corresponding processor logic interface 3, the intraconnection link establishment pre-connection link of each processor logic interface 3;
Described interface link is the communication link between processor and processor logic interface 3, and described intraconnection link is the logical communications links between two processor logic interfaces 3.
Wherein, configuration module 1, be equivalent to above-mentioned point out in principle realize being communicated with between multichannel processor with processor logic interface 3;
Each processor and a processor logic interface 3 are connected;
Link initialization control module 2, be equivalent to point out in above-mentioned principle for realizing the intraconnection between processor logic interface 3.
Pre-connection link is the communication link wishing between each processor or prepare to set up.
The multipath server dynamic link inking device of the embodiment of the present invention can also adopt two step collocation method to realize processor interconnecting link from direct-connected mode to the dynamic conversion of FPGA proofing chip:
Described configuration module 1, first the direct connected link of each processor is configured, on the basis that direct connected link initialization completes between the processors, configure the interface link between each processor and processor logic interface 3, configured the intraconnection link of each processor logic interface 3 again by link initialization control module 2, described direct connected link is the communication link between every two processors.
Above-mentioned multipath server dynamic link inking device takes into full account the interface logic design feature that fpga chip realizes, and can realize processor interconnecting link from direct-connected mode to the dynamic conversion of FPGA proofing chip.
Can also after totality interconnecting link be set up, by configuration module 1 breaking part or whole direct connected links.
The direct connected link initially completing configuration is disconnected, the intraconnection link that during making process, connection communication realizes by means of only fpga chip.
Said process, no matter be that processor interconnecting link is from direct-connected mode to the dynamic conversion of FPGA proofing chip, or direct connected link disconnects, the intraconnection link that during making process, connection communication realizes by means of only fpga chip, all ensure that the interconnecting link moment in multipath server system between processor exists, greatly reduce the complexity of verification platform hardware design.
The multipath server dynamic link inking device that the embodiment of the present invention provides, can also comprise monitoring module 4,
Described monitoring module 4 is for monitoring the duty of link initialization control module 2 and multiple processor logic interface 3;
When any one or multiple processor logic interface 3 and/or link initialization control module 2 operation irregularity, give a warning.
Described duty comprises the interface link connection status of each processor with corresponding processor logic interface 3 and the intraconnection link connection state of each processor logic interface 3; Described operation irregularity refers to that any one processor is with the interface link of corresponding processor logic interface 3 or the intraconnection chain of any one processor logic interface 3 breaks down or initialization is unsuccessful.
Connection status and the link initialization state of all links are all shown by monitoring module 4, and when arbitrary link occurs fault, or initialization is unsuccessful, and monitoring module 4 can monitor current malfunction, thus is convenient to analyze and solve failure problems.Such as: when link initialization is unsuccessful, the malfunction residing for link is checked by monitoring module 4, analyzing failure cause; Again such as: when link transmission quality is poor, being checked the quantity of link transmission by monitoring module 4, providing analysis foundation for optimizing link transmission quality further.
The embodiment of the present invention also provides a kind of multipath server dynamic link collocation method,
Described method realizes based on multipath server dynamic link inking device, and described collocation method comprises:
Steps A, configure interface link between each processor and processor logic interface 3;
Step B, configure the intraconnection link of each processor logic interface 3;
Described interface link is the communication link between processor and processor logic interface 3, and described intraconnection link is the logical communications links between two processor logic interfaces 3.
Before steps A, can also comprise: the direct connected link configuring each processor, described direct connected link is the communication link between every two processors.
After stepb, can also comprise: breaking part or all direct connected link.
By configuration module 1, adopt processor direct connected link to realize the initialization of multipath server interconnecting link, realize system interconnection; On the basis that the initialization of processor direct connected link completes, realized the interface link initialization of multichannel processor and processor logic interface 3 respectively by configuration module 1; Complete with processor logic interface 3 respectively on the initialized basis of interface link at multichannel processor, link initialization control module 2 realizes the connection communication of multichannel processor by processor logic interface 3, realize multiple processor logic interface 3 intraconnection, to realize in multipath server system connection communication between multichannel processor with this; On the basis that the initialization of multichannel processor interconnecting link completes, disconnected by configuration module 1 configuration processor direct connected link, realize multichannel processor and realize connection communication by means of only fpga chip.
Two step initialization chip configuration flow processs of above-mentioned dynamic link usability conversion ensure the connection communication of multipath server system, the dynamic availability achieving multipath server system processor interconnecting link transforms, be that fpga chip realizes connection communication by processor direct connected link dynamic conversion, for the design verification of system core chipset provides platform, the implementation method of this dynamic-configuration also effectively reduces complexity and the construction cycle of verification platform hardware design, in high-end server key chip group design verification process, have high using value and technological value.
Embodiment 1
Referring to Fig. 1, the content of the embodiment of the present invention is described.
In the present invention, two step initialization chip configuration flow process implementation methods of dynamic link usability conversion mainly comprise: the intraconnection link of the initialization of processor direct link, interface link initialization between each processor and processor logic interface 3, each processor logic interface 3, disconnect direct connected link.
In the checking of high-end server chipset and system initialization link availability test process, consider the feature of link design structure, for improving system architecture testing efficiency, reduce testing complex degree, adopt two step initialization implementation methods of dynamic link availability conversion, reach the usability testing of high-end server system many transmission links, realize FPGA simultaneously and realize key chip group interface logic availability verification.
System electrification under starting condition, the direct connected link of two processors is configured by configuration module 1, realize a CPU and the 2nd CPU by direct connected link connection communication, now interface link is not communicated with intraconnection link, namely communicates by means of only direct connected link between a CPU with the 2nd CPU.
When direct connected link completes initialization, a CPU and first processor logic interfacing 3 is configured by configuration module 1, and the 2nd interface link of CPU and the second processor logic interface 3, link initialization control module 2 completes the interconnection of first processor logic interfacing 3 and the second processor logic interface 3 simultaneously, therefore a CPU and the 2nd CPU is by the connection communication of intraconnection link, now direct connected link is communicated with while intraconnection link, namely passes through two articles of link communications between a CPU and the 2nd CPU simultaneously.
When intraconnection link completes initialization, the direct connected link configured between a CPU and the 2nd CPU by configuration module 1 is disconnected, now between a CPU and the 2nd CPU by means of only interface link and intraconnection link communication.So far system realizes connection, the conversion of multilink by dynamic-configuration, and opening operation, layoutprocedure completes at system interfaces link initialization process, and remain to there is interoperable links between processor in the process, ensure that the stable operation of system effectively achieves the switching at runtime of system multilink with this, play a great role in high-end server system verification and debug phase.
Embodiment 2
With reference to Fig. 2, the present embodiment is the high-end server system with three path processors, direct connected link wherein between processor, be similar to triangle, wherein three processors are positioned at leg-of-mutton three summits, direct connected link between processor is similar to three sides of a triangle, realizes the communication between every two processors.Similarly, intraconnection link between processor logic interface 3 is also similar to triangle, wherein three processor logic interfaces 3 are positioned at leg-of-mutton three summits, intraconnection link between processor logic interface 3 is similar to three sides of a triangle, realizes the logic communication between every two processor logic interfaces 3.
System realizes connection, the conversion of multilink by dynamic-configuration, and opening operation is consistent with embodiment 1.
Embodiment 3
With reference to Fig. 3, the present embodiment is the high-end server system with four path processors, direct connected link wherein between processor, be similar to quadrilateral, wherein four processors are positioned at four summits of quadrilateral, direct connected link between processor is similar to four edges and two diagonal line of quadrilateral, realizes the communication between every two processors.Similarly, intraconnection link between processor logic interface 3 is also similar to quadrilateral, wherein four processor logic interfaces 3 are positioned at four summits of quadrilateral, intraconnection link between processor logic interface 3 is similar to four edges and two diagonal line of limit shape, realizes the logic communication between every two processor logic interfaces 3.
System realizes connection, the conversion of multilink by dynamic-configuration, and opening operation is consistent with embodiment 1 and 2.
Above embodiment only in order to technical scheme of the present invention and unrestricted to be described, only with reference to preferred embodiment to invention has been detailed description.Those of ordinary skill in the art should be appreciated that and can modify to technical scheme of the present invention or equivalent replacement, and does not depart from the spirit and scope of technical solution of the present invention, all should be encompassed in the middle of right of the present invention.
Claims (12)
1. a multipath server dynamic link inking device, is characterized in that, described inking device comprises configuration module (1), link initialization control module (2) and multiple processor logic interface (3),
Described processor logic interface (3) is for connecting according to the configuration of configuration module (1) and corresponding processor;
Described configuration module (1) for configuring a processor logic interface (3) corresponding with described processor for each processor, and sets up interface link between processor and corresponding processor logic interface (3);
Described link initialization control module (2) for the intraconnection link according to each processor logic interface (3) of the pre-connection link configuration between each processor, make each processor by with pre-connection link described in the intraconnection link establishment of the interface link of corresponding processor logic interface (3), each processor logic interface (3);
Described interface link is the communication link between processor and processor logic interface (3), and described intraconnection link is the logical communications links between two processor logic interfaces (3).
2. inking device as claimed in claim 1, it is characterized in that: the pre-connection link between each processor described is the direct connected link of each processor, described direct connected link is the communication link between every two processors.
3. inking device as claimed in claim 1, is characterized in that: described link initialization control module (2) and multiple processor logic interface (3), utilize FPGA to realize.
4. the inking device as described in claim 1,2 or 3, is characterized in that:
Described configuration module (1) is also for before the interface link between each processor of configuration and processor logic interface (3), configure the direct connected link of each processor, described direct connected link is the communication link between every two processors.
5. inking device as claimed in claim 4, is characterized in that:
Described link initialization control module (2), also for after totality interconnecting link is set up, to finish signal to configuration module (1) feedback link;
Described configuration module (1) also for finishing after signal receiving link, breaking part or all direct connected link.
6. the inking device as described in claim 1 or 2 or 3 or 5, is characterized in that: described inking device also comprises monitoring module (4),
Described monitoring module (4) is for monitoring the duty of link initialization control module (2) and multiple processor logic interface (3), when any one or multiple processor logic interface (3) and/or link initialization control module (2) operation irregularity, give a warning.
7. inking device as claimed in claim 6, is characterized in that: described duty comprises the interface link connection status of each processor with corresponding processor logic interface (3) and the intraconnection link connection state of each processor logic interface (3); Described operation irregularity refers to that any one processor is with the interface link of corresponding processor logic interface (3) or the intraconnection chain of any one processor logic interface (3) breaks down or initialization is unsuccessful.
8. a multipath server dynamic link collocation method, is characterized in that, described method realizes based on the inking device described in claim 1-7 any one, and described collocation method comprises:
Steps A, configure interface link between each processor and corresponding processor logic interface (3);
Step B, configure the intraconnection link of each processor logic interface (3);
Described interface link is the communication link between processor and processor logic interface (3), and described intraconnection link is the logical communications links between two processor logic interfaces (3).
9. collocation method as claimed in claim 8, is characterized in that:
Before steps A, also comprise: the direct connected link configuring each processor, described direct connected link is the communication link between every two processors.
10. collocation method as claimed in claim 9, is characterized in that:
After stepb, also comprise: breaking part or all direct connected link.
11. collocation methods as described in claim 8 or 9 or 10, it is characterized in that: the duty also comprising monitoring link initialization control module (2) and multiple processor logic interface (3), when any one or multiple processor logic interface (3) and/or link initialization control module (2) operation irregularity, give a warning.
12. collocation methods as claimed in claim 11, is characterized in that: described duty comprises the interface link connection status of each processor with corresponding processor logic interface (3) and the intraconnection link connection state of each processor logic interface (3); Described operation irregularity refers to that any one processor is with the interface link of corresponding processor logic interface (3) or the intraconnection chain of any one processor logic interface (3) breaks down or initialization is unsuccessful.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210272129.9A CN102880583B (en) | 2012-08-01 | 2012-08-01 | Device and method for configuring dynamic link of multi-way server |
| PCT/CN2013/070356 WO2014019346A1 (en) | 2012-08-01 | 2013-01-11 | Dynamic link configuration device and method for multipath server |
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| CN201210272129.9A CN102880583B (en) | 2012-08-01 | 2012-08-01 | Device and method for configuring dynamic link of multi-way server |
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| CN104503947B (en) * | 2014-12-16 | 2018-03-16 | 华为技术有限公司 | Multipath server and its signal processing method |
| CN106446311B (en) * | 2015-08-10 | 2019-09-13 | 杭州华为数字技术有限公司 | CPU warning circuit and alarm method |
| CN110389927A (en) * | 2019-06-18 | 2019-10-29 | 苏州浪潮智能科技有限公司 | A kind of four road servers |
| CN116774020B (en) * | 2023-08-16 | 2023-11-14 | 上海燧原科技有限公司 | Chip testing system, method, device and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791016A (en) * | 2004-11-01 | 2006-06-21 | 阿尔卡特公司 | Multi-interface port management |
| CN1859417A (en) * | 2006-04-30 | 2006-11-08 | 西安交通大学 | Method for realizing multiple network device link aggregation |
| CN102141974A (en) * | 2011-04-11 | 2011-08-03 | 复旦大学 | Internuclear communication method of multinuclear processor and circuit structure thereof |
| CN102449621A (en) * | 2011-08-25 | 2012-05-09 | 华为技术有限公司 | Node controller chain switching method, processor system, and nodes |
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| US7152157B2 (en) * | 2003-03-05 | 2006-12-19 | Sun Microsystems, Inc. | System and method for dynamic resource configuration using a dependency graph |
| US7706266B2 (en) * | 2007-03-12 | 2010-04-27 | Citrix Systems, Inc. | Systems and methods of providing proxy-based quality of service |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791016A (en) * | 2004-11-01 | 2006-06-21 | 阿尔卡特公司 | Multi-interface port management |
| CN1859417A (en) * | 2006-04-30 | 2006-11-08 | 西安交通大学 | Method for realizing multiple network device link aggregation |
| CN102141974A (en) * | 2011-04-11 | 2011-08-03 | 复旦大学 | Internuclear communication method of multinuclear processor and circuit structure thereof |
| CN102449621A (en) * | 2011-08-25 | 2012-05-09 | 华为技术有限公司 | Node controller chain switching method, processor system, and nodes |
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Application publication date: 20130116 Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY Co.,Ltd. Assignor: INSPUR (BEIJING) ELECTRONIC INFORMATION INDUSTRY Co.,Ltd. Contract record no.: X2022110000051 Denomination of invention: A Dynamic Link Configuration Device and Method for Multichannel Servers Granted publication date: 20150311 License type: Common License Record date: 20221021 Application publication date: 20130116 Assignee: SUZHOU LANGCHAO INTELLIGENT TECHNOLOGY Co.,Ltd. Assignor: INSPUR (BEIJING) ELECTRONIC INFORMATION INDUSTRY Co.,Ltd. Contract record no.: X2022110000058 Denomination of invention: A Dynamic Link Configuration Device and Method for Multichannel Servers Granted publication date: 20150311 License type: Common License Record date: 20221025 |
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Effective date of registration: 20230727 Address after: 100085, C, building 2-1, No. 2, information road, 1, Beijing, Haidian District Patentee after: INSPUR (BEIJING) ELECTRONIC INFORMATION INDUSTRY Co.,Ltd. Address before: No. 1036, Shandong high tech Zone wave road, Ji'nan, Shandong Patentee before: INSPUR ELECTRONIC INFORMATION INDUSTRY Co.,Ltd. |